CN104102941B - 智能卡、身份识别卡、银行卡、智能卡触板及表面抗氧化方法 - Google Patents
智能卡、身份识别卡、银行卡、智能卡触板及表面抗氧化方法 Download PDFInfo
- Publication number
- CN104102941B CN104102941B CN201410138183.3A CN201410138183A CN104102941B CN 104102941 B CN104102941 B CN 104102941B CN 201410138183 A CN201410138183 A CN 201410138183A CN 104102941 B CN104102941 B CN 104102941B
- Authority
- CN
- China
- Prior art keywords
- smart card
- chip
- contact
- card
- corrosion protection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
- G06K19/07743—External electrical contacts
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/02—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the selection of materials, e.g. to avoid wear during transport through the machine
- G06K19/022—Processes or apparatus therefor
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
- G06K19/0772—Physical layout of the record carrier
- G06K19/07722—Physical layout of the record carrier the record carrier being multilayered, e.g. laminated sheets
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49855—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers for flat-cards, e.g. credit cards
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
- H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
- H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
- H01L2224/1146—Plating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1301—Shape
- H01L2224/13016—Shape in side view
- H01L2224/13018—Shape in side view comprising protrusions or indentations
- H01L2224/13019—Shape in side view comprising protrusions or indentations at the bonding interface of the bump connector, i.e. on the surface of the bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/273—Manufacturing methods by local deposition of the material of the layer connector
- H01L2224/2731—Manufacturing methods by local deposition of the material of the layer connector in liquid form
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/273—Manufacturing methods by local deposition of the material of the layer connector
- H01L2224/2731—Manufacturing methods by local deposition of the material of the layer connector in liquid form
- H01L2224/2732—Screen printing, i.e. using a stencil
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/81395—Bonding interfaces outside the semiconductor or solid-state body having an external coating, e.g. protective bond-through coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/81399—Material
- H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/81455—Nickel [Ni] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/81399—Material
- H01L2224/8149—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/819—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector with the bump connector not providing any mechanical bonding
- H01L2224/81901—Pressing the bump connector against the bonding areas by means of another connector
- H01L2224/81903—Pressing the bump connector against the bonding areas by means of another connector by means of a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
- H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
- H01L2224/83851—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester being an anisotropic conductive adhesive
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9211—Parallel connecting processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/951—Supplying the plurality of semiconductor or solid-state bodies
- H01L2224/95115—Supplying the plurality of semiconductor or solid-state bodies using a roll-to-roll transfer technique
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/27—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
- H01L24/92—Specific sequence of method steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15313—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
- H05K3/244—Finish plating of conductors, especially of copper conductors, e.g. for pads or lands
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Credit Cards Or The Like (AREA)
- Preventing Corrosion Or Incrustation Of Metals (AREA)
Abstract
本发明涉及接触式智能卡、使用该卡的用户身份识别卡、银行卡、智能卡触板、及防止或限止该触板的非贵金属芯片端子连接表面氧化的方法。本发明实施例提供的接触式智能卡包括智能卡触板和集成电路芯片。智能卡触板包括电路基板、设于电路基板的第一侧的读卡器接触元件、以及设于电路基板的背对第一侧的第二侧的芯片连接元件。读卡器接触元件具有贵金属导电表面,芯片连接元件具有非贵金属的芯片端子连接表面。集成电路芯片装设于电路基板的第二侧并与芯片端子连接表面电连接。
Description
技术领域
本发明涉及具有智能卡触板和集成电路芯片的接触式智能卡、具有该种智能卡的用户身份识别卡(SIM)和/或银行卡、防止或限制该种智能卡触板的非贵金属芯片端子连接表面氧化的方法、以及该智能卡触板。
背景技术
智能卡触板已众所周知并被应用于移动通讯设备中的用户身份识别卡(SIM)、银行卡以及其他领域中。该种被熟知的触板在两侧(读卡器接触侧和芯片安装侧)覆盖有金。金提供了抗腐蚀和抗氧化的特性,并实现芯片安装侧与所用的集成电路(IC)芯片之间的引线键合连接(wire-bonded connections)。
然而,在智能卡触板的两侧均使用贵金属增加了制造成本,并且加速了宝贵自然资源的消耗。
因此,本发明力图提供一种解决这个问题的方案。
发明内容
本发明的一方面提供一种接触式智能卡,包括智能卡触板和集成电路芯片。所述智能卡触板包括电路基板、设于所述电路基板的第一侧的读卡器接触元件、以及设于所述电路基板的背对所述第一侧的第二侧的芯片连接元件。所述读卡器接触元件具有贵金属导电表面,所述芯片连接元件具有非贵金属的芯片端子连接表面,所述集成电路芯片装设于所述电路基板的第二侧并与所述芯片端子连接表面电连接。
较佳的,所述贵金属是金或者含金。
较佳的,还包括覆盖所述芯片端子连接表面和所述贵金属导电表面至少其中之一的至少一个腐蚀保护层。
较佳的,所述至少一个腐蚀保护层或每个所述腐蚀保护层是有机金属导电层。
较佳的,所述至少一个腐蚀保护层或每个所述腐蚀保护层是基于巯基的。
较佳的,所述至少一个腐蚀保护层或每个所述腐蚀保护层是自组装单层。
较佳的,所述集成电路芯片被倒装式安装于所述芯片连接元件。
较佳的,还包括连接所述集成电路芯片和所述芯片连接元件的多个导电凸起。
较佳的,所述凸起为尖头的或扁平的。
较佳的,所述凸起设于所述芯片连接元件的第一层上。
本发明的另一方面提供一种用户身份识别卡,包括载板和上述任一种接触式智能卡,所述智能卡由所述载板承载。
本发明的再一方面提供一种银行卡,包括载板和上述任一种接触式智能卡,所述智能卡由所述载板承载。
本发明的第四方面提供一种防止或限制智能卡触板的非贵金属芯片端子连接表面氧化的方法,包括步骤:在使用倒装芯片安装技术安装集成电路芯片之前,在整个非贵金属芯片端子连接表面上形成有机导电腐蚀保护层。
较佳的,所述腐蚀保护层连续覆盖在整个非贵金属芯片端子连接表面上从而形成连接不断的覆盖隔离层。
本发明的第五方面提供一种智能卡触板,包括电路基板以及由所述电路基板承载的电路,所述电路包括设于所述电路基板的第一侧的读卡器接触元件、以及设于所述电路基板的背对所述第一侧的第二侧的芯片连接元件。所述读卡器接触元件具有贵金属导电表面,所述芯片连接元件具有非贵金属的芯片端子连接表面。
附图说明
图1显示了本发明第一实施例提供的智能卡触板;
图2显示了图1所示的智能卡触板的读卡器接触侧;
图3显示了图1所示的智能卡触板的倒装芯片安装侧;
图4是图2所示智能卡触板的沿线A-A的截面图;
图5示出本发明第二实施例提供的智能卡触板的截面图;
图6是智能卡触板的滚动式制造方法的流程图;
图7示出依据图5的智能卡触板以及以一种方法倒装式安装的集成电路芯片的截面示意图;以及
图8示出依据图5的智能卡触板以及以另一种方法倒装式安装的集成电路芯片的截面示意图。
具体实施方式
参考图1到4,本发明第一实施例的智能卡触板10包括电路基板12。电路基板12具有背对而设的读卡器接触侧16和芯片安装侧20。电路基板12的读卡器接触侧16设有读卡器接触元件14。电路基板12的芯片安装侧20设有芯片连接元件18(较佳的为倒装芯片连接元件)。电路基板12较佳的为柔性的和/或可成像的。电路基板12可以印刷有电路、或者可以印刷电路或者可以附加电路。
较佳的,电路基板12是例如可由聚对苯二甲酸乙二醇酯(PET)形成的柔性塑料载体条22,厚度在55到95微米之间(更佳的为75微米)。柔性塑料载体条22可以是可透光的。在本实施例中载体条22是透明的。
电路基板12是可成像的,即基板能在其表面或内部承载或具有电路图形。特别地,电路基板12较佳的为印刷电路薄膜,但也可使用可形成电路图形的其他类型的基板。
尽管电路基板较佳的是柔性的,但也可以使用非柔性的电路基板。
读卡器接触元件14包括若干导电覆盖层(优选采用电镀方式形成),包括基板侧导电层24,中间导电层26、及外部导电层28。基板侧导电层24形成在电路基板12的读卡器接触侧16上。本实施例中,基板侧导电层24由铜构成或含铜。基板侧导电层24的厚度优选的在5微米到25微米之间,更佳的,是或大约是10微米。
中间导电层26形成在基板侧导电层24上。在本实施例中,中间导电层26由镍组成或包含镍的成分。中间导电层26与基板侧导电层24连续不断的接触,优选厚度在1微米到4微米之间,更佳的是2.5微米或大约2.5微米。
外部导电层28形成在中间导电层26上,从而形成读卡器接触表面30。本实施例中,导电层28由金构成或含金。类似地,该外部导电层28与中间导电层26连续不断的接触,优选厚度在0.02微米到0.08微米之间,更佳的,是或大约是0.045微米。
本实施例中,读卡器接触元件14的各层都优选的为金属材质。根据需要,还可以设置更多中间层。
读卡器接触元件14设有触体(contact)C1-C8。优选采用蚀刻的工艺形成所述触体。在本实施例中,湿法蚀刻工艺可被方便地使用。虽然本实施例提供了8个触体,但也可根据需要使用多于或少于8个触体。
示例性的对本实施例中各触体C1-C8的功能描述如下。第一触体C1,被称为电源位(VCC),用于接电源,为卡中的微处理芯片供电;第二触体C2,被称为复位键(RST),用作复位功能,接口设备可通过此触体向智能卡的微处理芯片发出信号启动复位指令序列;第三触体C3,被称为时钟信号位(CLK),通过此触体可将时钟信号提供到微处理芯片,控制运行速度以及为接口设备与智能卡之间的数据通信提供共同的架构;第四触体C4,被称为预留功能位(RFU),是为将来使用预留的;第五触体C5,被称为接地位(GND),用于在接口设备和智能卡之间提供公共地;第六触体C6,被称为编程电压位(VPP),提供编程电源连接用于对第一代智能卡的电可擦只读存储器(EEPROM)进行编程;第七触体C7,也叫输入/输出位(I/O),作为输入/输出端口,在读卡器和智能卡之间提供半双工传输通信通道;第八触体C8,也是预留功能位(RFU),是为未来使用预留出来的。可以重新配置触体C1-C8以便提供替代的功能,或者也可以根据需要互换各个触体的功能。
芯片连接元件18也包括若干导电覆盖层,该若干导电覆盖层形成导电线路19,该导电线路19从集成电路(IC)芯片的端子21延伸到触板端子23,触板端子23穿过柔性塑料载体条22到达对应的触体C1-C8,可以采用电镀的工艺方便地形成导电覆盖层。电路基板12的芯片安装侧20形成第二基板侧导电层32。在本实施例中导电层32由铜构成或含铜。第二基板侧导电层32的厚度优选的在5微米到25微米之间,更佳的,是或大约是10微米。
第二外部导电层34形成在第二基板侧导电层32上,从而形成芯片端子连接表面36。在本实施例中第二外部导电层34由镍构成或含镍,而不是由金构成或含金。第二外部导电层34与第二基板侧导电层32连续不断地接触,厚度较佳的在1微米到4微米之间,更佳的,是或大约是2.5微米。
尽管本实施例中读卡器接触表面30是金的或者含金(主要因为金对环境物质的低反应性以及其具有的美感),但是其他任何合适的导电贵金属(优选如铂一样的贵金属),都可以考虑使用。同样的,连接集成电路(IC)芯片端子的芯片端子连接表面36可以是镍的或含镍。当然,也可以使用其他任何合适的抗腐蚀抗氧化的导电性非贵金属。
较佳的,可以使用倒装芯片安装方式将集成电路(IC)芯片的各端子安装到芯片端子连接表面36上。可以理解,也可使用其他安装方式。集成电路芯片的主体可粘结到电路基板12。
参考图5,本发明第二实施例的智能卡触板10也包括电路基板12(较佳的为柔性的和/或可成像的)、电路基板12的读卡器接触侧16的读卡器接触元件14、电路基板12的芯片安装侧20的芯片连接元件18,芯片安装侧20与读卡器接触侧16背对而设。本实施例中,使用相同的附图标记表示与前一实施例相似或相同的特征,并略去对相同特征的具体描述。
芯片连接元件18包括第二基板侧导电层32(较佳的由铜构成或含铜)。由镍构成或含镍的导电层形成第二中间导电层126。第二外部导电层128是腐蚀保护层138。本实施例中,腐蚀保护层138由有机无孔材料140(优选的为基于巯基的材料)形成。材料140连续不断地形成在第二中间导电层126的整个外表面142上。腐蚀保护层138可形成芯片连接元件18的一部分,或者是在芯片连接元件18上形成的独立的结构。
腐蚀保护层138可以是自组装单层(self-assembled mono layer)144,从而提供连续的覆盖隔离表面146。尽管腐蚀保护层138较佳的是导电的,作为替代,视实际需要,腐蚀保护层138也可以是不导电的。
之所以推荐使用有机无孔基于巯基的材料140是因为这种材料可导电、可透射(本实施例中为透明的),且人接触这种材料时不会过敏。这种腐蚀保护层138保持了与其覆盖的第二中间导电层126一样的导电性。此外,该有机金属腐蚀保护层138缓和了形成自组装单层144过程中产生的镍的氧化。蠕变腐蚀是一种导致电气元件过早损坏的已知现象,其原因在于大气环境中弥漫着越来越多的硫化物。本发明中的腐蚀保护层138形成了一个隔离层以阻止该有害影响。一种合适的可用于此腐蚀保护层的材料可从设于美国马萨诸赛州梅休因市的Parlex公司获得,产品代码为N019292。当然,也可以根据需要使用其他适合的导电性腐蚀保护材料。
虽然不是必须的,但是,在读卡器接触元件14的外部导电层28上覆盖一层第二腐蚀保护层148也是有好处的。好处在于可以减小由金构成或含金的外部导电层28的厚度,同时维持外形的美观。另外,还有一个好处就是使用这种腐蚀保护层148来降低贵金属导电层28暴露在含硫环境中所导致的腐蚀效应。本实施例中,第二腐蚀保护层148是导电的,可具有前述的腐蚀保护层138同样的特征。然而,第二腐蚀保护层148不一定必须是有机金属的。
此外,由于基板侧的非贵金属和导电层24、26通过半电池反应形成原电池(galvanic cell),第二腐蚀保护层148的使用可以减少读卡器接触元件14的电化属性(galvanic nature)。
参考图6,优选地,采用卷对卷工艺(roll-to-roll)以在载体条22上形成若干智能卡触板的方式制造该种智能卡触板10。柔性载体条22由滚动传输系统150送入,通过分级处理形成读卡器接触元件14和芯片连接元件18。参考步骤152和154,可以首先形成读卡器接触元件14和芯片连接元件18其中之一,之后形成另一个。然而,也可以在通过滚动传输系统150送入载体条22的过程中同时形成读卡器接触元件14和芯片连接元件18。
一旦例如通过冲压从载体条22脱离,每个智能卡触板10可以被独立地安装在适当的载体上从而形成所需的智能卡(例如电信用户识别卡(SIM)或银行卡)。
图7和图8示出依据本发明第二实施例的智能卡触板以及以两种不同方法倒装式安装的集成电路芯片。
图7中,智能卡触板100具有第一倒装芯片200。第一倒装芯片200包括多个焊盘202。每个芯片焊盘202连接至一个导电的柱形凸起204。较佳的,柱形凸起204是尖头的,与芯片连接元件18点接触而形成电连接。为防止或避免滑动,使用粘合剂160将倒装芯片200固定至智能卡触板100。较佳的,粘合剂160呈糊状或是薄膜层。较佳的,出于成本考虑,粘合剂160是不导电的。然而,即使比较贵,仍然可以使用各向异性(Z轴)的导电粘合剂。粘合剂160使柱形凸起204与芯片连接元件18保持接触。
作为另一种选择,可以使用图8所示的智能卡触板101。智能卡触板101具有第二倒装芯片300。第二倒装芯片300也包括多个芯片焊盘302,每个焊盘302连接至一个导电扁平凸起304。本实施例中,扁平凸起304呈薄型,与前面的柱状凸起204相比较矮。扁平凸起304抵靠或设于芯片连接元件18的外部导电层128上,由此与最外层形成面接触,从而将芯片300与芯片连接元件18电连接。同样,较佳地可使用粘合剂160固定第二倒装芯片300,以使扁平凸起304与芯片连接元件18保持接触。
本实施例中,柔性电路基板12的读卡器接触侧16较佳的具有四层结构,分别是基板侧导电层24、非贵金属中间导电层26、贵金属外部导电层28、以及第二腐蚀保护层148。
然而,由于本实施例中具有腐蚀保护层148,即使没有非贵金属中间导电层26,也可能有效电连接倒装芯片300和读卡器接触元件14。不设非贵金属中间导电层26可相应地降低智能卡触板的成本。
较佳的,如果在形成智能卡触板的同时将倒装芯片200、300装设至电路基板12,粘合剂160可代替腐蚀保护层138起到防止后续的中间导电层126被氧化或腐蚀的作用,这样可以简化智能卡触板的结构。如果粘合剂160用于此目的,那么贵金属外部导电层28仍然需要第二腐蚀保护层148。
由此,如果将集成电路芯片装至芯片连接元件所使用的粘合剂满足前面所提及的要求,那么粘合剂160可以是合适的腐蚀保护层。
依据本发明的实施例,提供不再需要那么多贵金属的智能卡触板成为可能。进一步的,贵金属可只使用在读卡器接触面。此外,提供具有非贵金属芯片端子连接面的智能卡触板也成为可能,在安装集成电路芯片IC之前,芯片端子连接面不会或基本上不会被腐蚀或氧化。
以上实施例的描述仅以一个例子说明,对于本领域的技术人员来书,在不脱离本发明所附权利要求的前提下,还可以做出若干改进和变形。
Claims (15)
1.一种接触式智能卡,包括智能卡触板(10,100,101)和集成电路芯片(200,300),所述智能卡触板(10,100,101)包括柔性电路基板(12)、设于所述柔性电路基板(12)的第一侧(16)的读卡器接触元件(14)、以及设于所述柔性电路基板(12)的背对所述第一侧(16)的第二侧(20)的芯片连接元件(18);其特征在于:所述读卡器接触元件(14)具有贵金属的外部导电层(28),所述芯片连接元件(18)具有非贵金属的芯片端子连接表面(36),所述集成电路芯片(200,300)装设于所述电路基板(12)的第二侧(20)并与所述芯片端子连接表面(36)电连接,所述芯片端子连接表面(36)覆盖第二外部导电层(128),所述智能卡触板(10,100,101)还包括覆盖所述第二外部导电层(128)的至少一个腐蚀保护层(138),且所述腐蚀保护层(138)未被粘合剂(160)完全覆盖。
2.如权利要求1所述的接触式智能卡,其特征在于,所述贵金属是金或者含金。
3.如权利要求1所述的接触式智能卡,其特征在于,还包括覆盖所述贵金属的外部导电层(28)的至少一个腐蚀保护层(148)。
4.如权利要求3所述的接触式智能卡,其特征在于,所述至少一个腐蚀保护层或每个所述腐蚀保护层是有机金属导电层。
5.如权利要求3所述的接触式智能卡,其特征在于,所述至少一个腐蚀保护层或每个所述腐蚀保护层是基于巯基的。
6.如权利要求3所述的接触式智能卡,其特征在于,所述至少一个腐蚀保护层或每个所述腐蚀保护层是自组装单层。
7.如权利要求1所述的接触式智能卡,其特征在于,所述集成电路芯片(200,300)被倒装式安装于所述芯片连接元件(18)。
8.如权利要求7所述的接触式智能卡,其特征在于,还包括连接所述集成电路芯片(200,300)和所述芯片连接元件(18)的多个导电凸起(204,304)。
9.如权利要求8所述的接触式智能卡,其特征在于,所述凸起为尖头的或扁平的。
10.如权利要求9所述的接触式智能卡,其特征在于,所述凸起(204,304)设于所述芯片连接元件(18)的第一层上。
11.一种用户身份识别卡,包括载板和如权利要求1-10任一项所述的接触式智能卡,所述智能卡由所述载板承载。
12.一种银行卡,包括载板和如权利要求1-10任一项所述的接触式智能卡,所述智能卡由所述载板承载。
13.一种防止或限制智能卡触板(10,100,101)的非贵金属芯片端子连接表面(36)氧化的方法,其特征在于,该方法包括步骤:在柔性电路基板(12)上采用卷对卷工艺同时形成读卡器接触元件(14)与芯片连接元件(18),在使用倒装芯片安装技术安装集成电路芯片(200,300)之前,在整个非贵金属芯片端子连接表面(36)上形成有机导电腐蚀保护层(138),且所述有机导电腐蚀保护层(138)未被粘合剂(160)完全覆盖。
14.如权利要求13所述的方法,其特征在于,所述腐蚀保护层连续覆盖在整个非贵金属芯片端子连接表面(36)上从而形成连接不断的覆盖隔离层。
15.一种智能卡触板(10,100,101),包括柔性电路基板(12)以及由所述柔性电路基板(12)承载的电路,所述电路包括设于所述柔性电路基板(12)的第一侧(16)的读卡器接触元件(14)、以及设于所述柔性电路基板(12)的背对所述第一侧(16)的第二侧(20)的芯片连接元件(18);其特征在于:所述读卡器接触元件(14)具有贵金属的外部导电层(28),所述芯片连接元件(18)具有非贵金属的芯片端子连接表面(36),所述芯片端子连接表面(36)覆盖第二外部导电层(128),所述智能卡触板(10,100,101)还包括覆盖所述第二外部导电层(128)的至少一个腐蚀保护层(138),且所述腐蚀保护层(138)未被粘合剂(160)完全覆盖。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201410138183.3A CN104102941B (zh) | 2013-04-11 | 2014-04-08 | 智能卡、身份识别卡、银行卡、智能卡触板及表面抗氧化方法 |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201310125487 | 2013-04-11 | ||
CN2013101254871 | 2013-04-11 | ||
CN201310125487.1 | 2013-04-11 | ||
CN201410138183.3A CN104102941B (zh) | 2013-04-11 | 2014-04-08 | 智能卡、身份识别卡、银行卡、智能卡触板及表面抗氧化方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN104102941A CN104102941A (zh) | 2014-10-15 |
CN104102941B true CN104102941B (zh) | 2023-10-13 |
Family
ID=50732776
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201420167064.6U Expired - Lifetime CN203894790U (zh) | 2013-04-11 | 2014-04-08 | 智能卡、身份识别卡、银行卡及智能卡触板 |
CN201410138183.3A Active CN104102941B (zh) | 2013-04-11 | 2014-04-08 | 智能卡、身份识别卡、银行卡、智能卡触板及表面抗氧化方法 |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201420167064.6U Expired - Lifetime CN203894790U (zh) | 2013-04-11 | 2014-04-08 | 智能卡、身份识别卡、银行卡及智能卡触板 |
Country Status (6)
Country | Link |
---|---|
US (2) | US9251457B2 (zh) |
EP (2) | EP2790131B1 (zh) |
JP (1) | JP6416491B2 (zh) |
CN (2) | CN203894790U (zh) |
BR (1) | BR102014008914B1 (zh) |
TW (1) | TWI633492B (zh) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB201510252D0 (en) * | 2015-06-12 | 2015-07-29 | Johnson Electric Sa | Coloured smart card module and smart card |
CN107025481B (zh) * | 2016-02-02 | 2021-08-20 | 上海伯乐电子有限公司 | 柔性印制电路板及应用其的智能卡模块和智能卡 |
CN107679611A (zh) * | 2017-10-13 | 2018-02-09 | 四川精工伟达智能技术股份有限公司 | 一种智能卡 |
US11380630B2 (en) | 2020-05-11 | 2022-07-05 | International Business Machines Corporation | Integrated circuit package that measures amount of internal precious material |
Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2000064229A1 (en) * | 1999-04-15 | 2000-10-26 | Amerasia International Technology, Inc. | Contact module, as for a smart card, and method for making same |
US6188580B1 (en) * | 1996-08-08 | 2001-02-13 | Infineon Technologies Ag | Smart card and semiconductor chip for use in a smart card |
US6433359B1 (en) * | 2001-09-06 | 2002-08-13 | 3M Innovative Properties Company | Surface modifying layers for organic thin film transistors |
US20070013396A1 (en) * | 2005-07-14 | 2007-01-18 | Dong-Han Kim | Universal pcb and smart card using the same |
CN1971866A (zh) * | 2005-11-14 | 2007-05-30 | 蒂科电子法国公司 | 智能卡主体及其制造方法、智能卡及其装配方法和载体带 |
US20100159987A1 (en) * | 2008-12-18 | 2010-06-24 | Byoung-Jo Kim | Universal serial bus based subscriber identity module |
CN101770600A (zh) * | 2009-12-31 | 2010-07-07 | 北京握奇数据系统有限公司 | 一种非接触式智能卡及其制作方法 |
CN102360447A (zh) * | 2011-11-01 | 2012-02-22 | 上海祯显电子科技有限公司 | 一种薄膜基板 |
US20120328904A1 (en) * | 2011-06-23 | 2012-12-27 | Xtalic Corporation | Printed circuit boards and related articles including electrodeposited coatings |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61123990A (ja) * | 1984-11-05 | 1986-06-11 | Casio Comput Co Ltd | Icカ−ド |
FR2584235B1 (fr) * | 1985-06-26 | 1988-04-22 | Bull Sa | Procede de montage d'un circuit integre sur un support, dispositif en resultant et son application a une carte a microcircuits electroniques |
JPS6259096A (ja) * | 1985-09-10 | 1987-03-14 | カシオ計算機株式会社 | Icカ−ド |
JPH0569691A (ja) * | 1991-09-17 | 1993-03-23 | Fujitsu General Ltd | Icカード |
US6404643B1 (en) * | 1998-10-15 | 2002-06-11 | Amerasia International Technology, Inc. | Article having an embedded electronic device, and method of making same |
DE10016715C1 (de) * | 2000-04-04 | 2001-09-06 | Infineon Technologies Ag | Herstellungsverfahren für laminierte Chipkarten |
DE10139395A1 (de) * | 2001-08-10 | 2003-03-06 | Infineon Technologies Ag | Kontaktierung von Halbleiterchips in Chipkarten |
DE102006060719A1 (de) * | 2006-12-21 | 2008-06-26 | Infineon Technologies Ag | Chipkartenmodul und Verfahren zur Herstellung eines Chipkartenmoduls |
US20100267419A1 (en) * | 2007-12-10 | 2010-10-21 | Hirotaka Nishizawa | Sim adapter and sim card |
CN102117929A (zh) * | 2010-01-05 | 2011-07-06 | 三星Sdi株式会社 | 二次电池和智能卡 |
CN102395247A (zh) | 2011-10-10 | 2012-03-28 | 青岛琴岛控制器有限公司 | 单面镀金的pcb线路板 |
-
2014
- 2014-04-08 CN CN201420167064.6U patent/CN203894790U/zh not_active Expired - Lifetime
- 2014-04-08 CN CN201410138183.3A patent/CN104102941B/zh active Active
- 2014-04-09 EP EP14164108.4A patent/EP2790131B1/en active Active
- 2014-04-09 EP EP17182828.8A patent/EP3270328B1/en active Active
- 2014-04-10 US US14/249,722 patent/US9251457B2/en active Active
- 2014-04-11 BR BR102014008914-4A patent/BR102014008914B1/pt active IP Right Grant
- 2014-04-11 TW TW103113387A patent/TWI633492B/zh active
- 2014-04-11 JP JP2014081778A patent/JP6416491B2/ja active Active
-
2015
- 2015-12-18 US US14/975,187 patent/US9524459B2/en active Active
Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6188580B1 (en) * | 1996-08-08 | 2001-02-13 | Infineon Technologies Ag | Smart card and semiconductor chip for use in a smart card |
WO2000064229A1 (en) * | 1999-04-15 | 2000-10-26 | Amerasia International Technology, Inc. | Contact module, as for a smart card, and method for making same |
US6433359B1 (en) * | 2001-09-06 | 2002-08-13 | 3M Innovative Properties Company | Surface modifying layers for organic thin film transistors |
US20070013396A1 (en) * | 2005-07-14 | 2007-01-18 | Dong-Han Kim | Universal pcb and smart card using the same |
CN1971866A (zh) * | 2005-11-14 | 2007-05-30 | 蒂科电子法国公司 | 智能卡主体及其制造方法、智能卡及其装配方法和载体带 |
US20100159987A1 (en) * | 2008-12-18 | 2010-06-24 | Byoung-Jo Kim | Universal serial bus based subscriber identity module |
CN101770600A (zh) * | 2009-12-31 | 2010-07-07 | 北京握奇数据系统有限公司 | 一种非接触式智能卡及其制作方法 |
US20120328904A1 (en) * | 2011-06-23 | 2012-12-27 | Xtalic Corporation | Printed circuit boards and related articles including electrodeposited coatings |
CN102360447A (zh) * | 2011-11-01 | 2012-02-22 | 上海祯显电子科技有限公司 | 一种薄膜基板 |
Also Published As
Publication number | Publication date |
---|---|
BR102014008914B1 (pt) | 2022-02-01 |
CN203894790U (zh) | 2014-10-22 |
US9524459B2 (en) | 2016-12-20 |
JP6416491B2 (ja) | 2018-10-31 |
EP3270328A1 (en) | 2018-01-17 |
US9251457B2 (en) | 2016-02-02 |
EP2790131A1 (en) | 2014-10-15 |
JP2014206978A (ja) | 2014-10-30 |
CN104102941A (zh) | 2014-10-15 |
TWI633492B (zh) | 2018-08-21 |
US20160104063A1 (en) | 2016-04-14 |
BR102014008914A2 (pt) | 2014-12-23 |
EP2790131B1 (en) | 2017-09-20 |
EP3270328B1 (en) | 2021-05-26 |
TW201443788A (zh) | 2014-11-16 |
US20140306016A1 (en) | 2014-10-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10810477B2 (en) | Method for producing a circuit for a chip card module and circuit for a chip card module | |
KR101494916B1 (ko) | 듀얼 통신 인터페이스를 갖는 칩 카드 | |
CN104102941B (zh) | 智能卡、身份识别卡、银行卡、智能卡触板及表面抗氧化方法 | |
US10461057B2 (en) | Dual-interface IC card module | |
US10820418B2 (en) | Electronic module, method for manufacturing same and electronic device comprising a module of said type | |
CN105230134A (zh) | 制造柔性印刷电路的方法、通过该方法获得的柔性印刷电路以及包括如该柔性印刷电路的芯片卡模块 | |
US9424507B2 (en) | Dual interface IC card components and method for manufacturing the dual-interface IC card components | |
US20190026621A1 (en) | Method for Manufacturing a Smart Card Module and a Smart Card | |
KR102438037B1 (ko) | 전기 회로, 전기 회로 상에 형성된 칩 카드를 위한 전자 모듈, 및 이러한 전기 회로의 제조 방법 | |
CN107408220B (zh) | 用于制造芯片卡模块的带状衬底 | |
CN203490719U (zh) | 智能卡及智能卡触板 | |
US9633297B2 (en) | IC module, IC card, and IC module substrate | |
JP2008176549A (ja) | デュアルインターフェースicカードとその製造方法、接触・非接触兼用icモジュール | |
JP2002312746A (ja) | Icモジュール及びその製造方法、並びに該icモジュールを装着した携帯可能電子装置 | |
JP2004139207A (ja) | Icモジュール回路基板 | |
KR20230116165A (ko) | 스마트 ic 기판 모듈 및 스마트 ic 기판 | |
JP2006024023A (ja) | 接触式icカード用テープキャリアおよび接触式icカード用接触端子モジュール | |
CN102376673A (zh) | 封装基板及其形成方法 | |
WO2010057933A1 (en) | Integrated circuit device equipped with different connection means |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |