TWI628774B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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TWI628774B
TWI628774B TW106125101A TW106125101A TWI628774B TW I628774 B TWI628774 B TW I628774B TW 106125101 A TW106125101 A TW 106125101A TW 106125101 A TW106125101 A TW 106125101A TW I628774 B TWI628774 B TW I628774B
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defect
layer
substrate
opening
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陳步芳
一斌 盧
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台灣積體電路製造股份有限公司
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Abstract

在一種製造一半導體裝置之方法中,在一基板上執行一熱處理,藉此在該基板之一上部層中形成一無缺陷層,其中該基板之一剩餘層係一本體層。該本體層中之一缺陷密度等於或大於1x10 8cm -3,其中該等缺陷係本體微缺陷。一電子裝置形成於該無缺陷層上方。一開口形成於該無缺陷層中,使得該開口未到達該本體層。用一導電材料填充該開口,藉此形成一通路。移除該本體層,使得暴露該通路之一底部部分。該無缺陷層中之一缺陷密度小於100 cm -3

Description

半導體裝置及其製造方法
本揭露大體上係關於半導體裝置,且更特定言之係關於具有貫穿矽通路之半導體裝置。
藉由以下各者在一半導體晶圓中形成貫穿矽通路(TSV):最初在半導體晶圓(例如,Si基板)中至少部分地形成一開口;及在該開口中形成一導電材料。該TSV將形成於該基板之前表面上之電子裝置(例如,電容器)與形成於該基板之後(背)表面處之一終端電連接。
根據本發明一實施例,一種製造一半導體裝置之方法,其包括:在一基板上執行一熱處理,藉此在該基板之一上部層中形成一無缺陷層,該基板之一剩餘層為一本體層,該本體層包含作為缺陷之本體微缺陷且該本體層中之一缺陷密度等於或大於1×10 8cm -3;在該無缺陷層上方形成一電子裝置;在該無缺陷層中形成一開口,使得該開口未到達該本體層;用一導電材料填充該開口,藉此形成一通路;及移除該本體層,使得暴露該通路之一底部部分,其中該無缺陷層中之一缺陷密度小於100 cm -3。 根據本發明一實施例,一種製造一半導體裝置之方法,其包括:在具有一無缺陷層及一本體層之一基板上方形成一電子裝置;該本體層包含作為缺陷之本體微缺陷且該本體層中之一缺陷密度等於或大於1x10 8cm -3;在該無缺陷層中形成一開口,使得該開口未到達該本體層;用一導電材料填充該開口,藉此形成一通路;及移除該本體層,使得暴露該通路之一底部部分,其中該無缺陷層中之一缺陷密度小於100 cm -3。 根據本發明一實施例,一種半導體裝置,其包括:一第一基板,其具有一第一電子裝置及電連接至該第一電子裝置之一連接終端;及一第二基板,其具有一第二電子裝置及穿過該第二基板且電連接至該第二電子裝置之一通路,其中:該第一基板附接至該第二基板,使得該連接終端與該通路接觸,該通路由該第二基板之一無缺陷層環繞,該無缺陷層之一缺陷密度小於100 cm-3,且該等缺陷係本體微缺陷。
應理解下文揭露提供用於實施本發明實施例之不同特徵之諸多不同實施例或實例。下文描述組件及配置之特定實施例或實例以簡化本揭露。此等當然僅為實例且不意欲為限制。例如,元件之尺寸不受限於所揭露之範圍或值,但可取決於裝置之處理條件及/或所要性質。此外,下文描述中在一第二構件上方或在一第二構件上之一第一構件之形成可包含其中該第一構件及該第二構件形成為直接接觸之實施例,且亦可包含其中可在該第一構件與該第二構件之間形成額外構件,使得該第一構件與該第二構件可不直接接觸之實施例。為簡單及清楚之目的,可依不同比例任意繪製各種構件。 進一步言之,為易於描述,空間相關術語(諸如「底下」、「下方」、「下」、「上方」、「上」及類似者)可在本文中用於描述如圖中所繪示之一元件或構件與另一元件或構件之關係。該等空間相關術語意欲涵蓋除圖中所描繪之定向之外裝置在使用或操作中之不同定向。裝置可依其他方式定向(旋轉90度或以其他定向),且同樣可相應地解釋本文中所使用之空間相關描述詞。此外,術語「由…製成」可意謂「包括」或「由…組成」。 圖1至圖9展示繪示根據本揭露之一實施例之一貫穿矽通路(TSV)結構之一製程之例示性剖面圖。可在美國專利第8,680,682號中找到一TSV之一般製造操作,其之全部內容以引用之方式併入本文中。 在圖1中,提供一基板10。基板10具有一第一(例如,前)側11及與第一側11相對之一第二(後)側12,且可係摻雜有雜質或無摻雜之一本體矽晶圓,或係一絕緣體上矽(SOI)基板之一主動層。基板10可包括其他半導體,諸如IV-IV族化合物半導體(諸如SiC及SiGe)、III-V族化合物半導體(諸如GaAs、GaP、GaN、InP、InAs、InSb、GaAsP、AlGaN、AlInAs、AlGaAs、GalnAs、GalnP、及/或GaInAsP),或其等之組合。 在一實施例中,使用一Si基板(晶圓)。一般而言,如藉由一晶圓製造提供之一矽晶圓包含缺陷,諸如本體微觀缺陷(BMD)。BMD通常指矽中之氧沉澱,且可包含氧沉澱、空隙、內含物、滑移線等。晶體原生粒子(或凹坑)(COP)可包含於BMD中。 電子裝置(例如,MOS電晶體)下方之矽層中之BMD充當一吸氣位(gettering site),以使雜質遠離該等MOS電晶體。可藉由用IR (紅外線)光照明一樣本及用對IR敏感之一攝影機查看該樣本來偵測BMD。 在本揭露之一實施例中,矽基板10中之BMD密度(初始數目)等於或大於1x10 8cm -3。由一CZ方法形成之矽晶圓中之BMD之一典型密度可由工業標準(諸如SEMI標準或JEITA標準)定義。可藉由計數由使用KOH之濕式蝕刻形成之蝕刻凹坑來判定BMD之數目。 在本揭露中,如圖2中所展示,一無缺陷層(無BMD層或剝蝕區) 20形成於基板10之至少前表面(上部表面)區中。在晶圓程序開始時形成無缺陷層20。在一些實施例中,在任何離子植入、圖案化或膜形成操作之前形成無缺陷層20。換言之,用於形成無缺陷層20之操作在如由一晶圓製造商製造之一所謂「裸晶圓」上執行。 在一實施例中,執行一熱處理以形成無BMD層20。該熱處理可包含一快速熱退火(RTA)方法、在一熔爐中加熱或一雷射退火方法。在清潔基板10後,於基板10上執行該熱處理。 在該熱處理中,在一些實施例中,在從約1150℃至約1300℃之一範圍中之一溫度下加熱基板10。在某些實施例中,在從約1200℃至約1250℃之一範圍中之一溫度下加熱基板10。在一些實施例中,溫度係依在從約50℃/sec至約100℃/sec之一範圍中之一溫度升高速率自(例如)室溫(25℃)升高至所要溫度。在一些實施例中,執行該熱處理達在從約5秒至約20秒之一範圍中之一時間段。在某些實施例中,執行該熱處理達在從約10秒至約15秒之範圍中之一時間段。在一些實施例中,在依上述溫度執行該熱處理後,依在從約10℃/sec至約30℃/sec之一範圍中之一冷卻速率執行一冷卻程序。在某些實施例中,依在從約15℃/sec至約25℃/sec之一範圍中之一冷卻速率執行該冷卻程序。該冷卻速率低於該溫度升高速率。應注意,一更低冷卻速率可產生一更寬無缺陷層。可藉由具有不同冷卻速率之多個步驟執行該冷卻程序。在一些實施例中,執行具有一第一冷卻速率之一快速冷卻操作,接著進行具有低於該第一冷卻速率之一第二冷卻速率之一緩慢冷卻操作。在此一情況中,該第一冷卻速率在從約15℃/sec至約30℃/sec之一範圍中且該第二冷卻速率在從約10℃/sec至約25℃/sec之一範圍中。可執行降低冷卻速率之三個或更多步驟。在某些實施例中,該冷卻速率逐漸減小。 藉由調整溫度、處理時間及冷卻速率之一或多個,可控制無缺陷層20之厚度(深度) D1。在一些實施例中,無缺陷層20之厚度D1在從約30 µm至約200 µm之一範圍中。在某些實施例中,D1等於或大於約50 µm且等於或小於100 µm,且在其他實施例中,D1在從約60 µm至約90 µm之一範圍中。基板10之剩餘層被稱作一本體層30,本體層30仍包含等於或大於1x10 8cm -3之BMD。應注意無缺陷層20不應製作得太厚,此係因為電子裝置下方之矽層中之BMD充當吸氣位。 無缺陷層20中之BMD密度實質上為零(例如,小於100 cm -3)。在某些實施例中,無缺陷層20中之BMD密度為零。 在某些實施例中,取決於一種熱處理方法,一無缺陷層亦形成於基板10之底部(後)表面中。 如圖3中所展示,在形成無缺陷層20後,形成絕緣結構(例如,淺溝渠隔離(STI)),執行離子植入操作,且在無缺陷層20上製造電子裝置(諸如MOSFET、金屬接線及接點等)。在圖3中,僅繪示由一層間介電(ILD)層50覆蓋之一MOSFET 40及穿過ILD層50之一接點45作為電子裝置之一概念說明圖。當然,多層接線層、層間介電層及通路/接點或其他被動或主動電子裝置亦形成於基板10上以提供整體電路設計之所要結構及功能需求。可使用任何適當方法在基板之表面內或基板之表面上形成該等電子裝置。 ILD層50藉由化學氣相沉積(CVD)、濺鍍或任何其他適當方法形成於基板10及電子裝置40上方。ILD層50通常具有一平坦化表面且可由氧化矽組成,但可替代地利用其他材料(諸如低介電係數材料)。 接點45延伸穿過ILD層50以與電子裝置40之至少一者電接觸。可藉由使用光微影及蝕刻技術穿過ILD層50形成接點45。接點45可包括一阻障層/黏著層(未展示)以阻止擴散且提供接點45與ILD層50之間之更佳黏著性。在一實施例中,該阻障層由一層或更多層之鈦、氮化鈦、鉭、氮化鉭或類似者形成。可透過CVD、濺鍍或其他技術形成該阻障層。在一些實施例中,該阻障層可形成為約1 nm至約50 nm之一組合厚度。接點45可由任何適當導電材料(諸如一高導電性、低電阻式金屬,元素金屬,過渡金屬或類似者)形成。在一例示性實施例中,接點45由鎢形成,但可替代地利用其他材料(諸如銅、鎳、鈷、鋁或其之一合金)。 如圖4中所展示,一開口60穿過ILD層50形成且形成至基板10之無缺陷層20中。如圖4中所展示,在本揭露中,開口60未到達基板10之本體層30。在一些實施例中,開口60之底部與本體層30之間之距離在從約50 nm至約200 nm之一範圍中。 可藉由將一適當光阻劑(未展示)應用及顯影,且接著蝕刻ILD層50及基板10之無缺陷層20之至少一部分而形成開口60。開口60經形成以至少比形成於基板10內之電子裝置40更遠地延伸至基板10中但未到達本體層30。因此,自基板10之上部表面量測之開口之深度D2小於無缺陷層20之厚度D1。在一些實施例中,深度D2為無缺陷層20之厚度D1之約70%至約95%,且在某些實施例中,D2係D1之約80%至約90%。進一步言之,在一些實施例中,開口60具有在從約2 µm至約70 µm之一範圍中之一直徑W1。 然而,在其他實施例中,可於形成ILD層50之同時或在形成ILD層50之前形成開口60。用以形成開口60之任何形成方法包含在本標的之範疇內。 如圖5中所展示,形成開口60後,一阻障層70及一主導電層75形成於開口60中及ILD層50之上部表面上方。阻障層70保形地形成以覆蓋開口60之側壁及底部,但並不完全填充開口60。在一些實施例中,阻障層70之厚度在從約1 nm至約100 nm之一範圍中,且在其他實施例中,該厚度在從約2 nm至約10 nm之一範圍中。藉由保形地形成阻障層70,該阻障層將沿開口60之側壁及亦沿開口60之底部具有一實質上相等厚度。 可使用將促進一保形形成之一程序(諸如電漿輔助化學氣相沉積(plasma enhanced CVD)、電漿輔助物理氣相沉積(PEPVD)及原子層沈積(ALD))形成阻障層70。 阻障層70包括一層或多個層之Ti、TiN、Ta及TaN。此外,在一些實施例中,可用一合金材料(諸如碳或氟)使阻障層70合金化,但該合金材料含量通常不大於阻障層70之約15%,且可小於阻障層70之約5%。可在ALD、PECVD或PEPVD程序中形成阻障層70期間由前驅物之一者引入該合金材料。 主導電層75可包括銅,但可替代地利用其它適當材料(諸如鋁、其之合金、摻雜多晶矽、其之組合)。可藉由將銅電鍍至阻障層70上,填充及過量填充開口60而形成主導電層75。在一些實施例中,在形成主導電層75之前在該阻障層上形成一晶種層(未展示)。 如圖6中所展示,一旦已填充開口60,即透過一平坦化程序(諸如化學機械拋光(CMP))移除開口60外部之過量阻障層70及主導電層75,藉此形成一通路80。 圖7繪示在形成一TSV中之進一步處理操作。一金屬層95形成於ILD層50上方以連接接點45及通路80。可藉由CVD、PVD或其他適當方法形成金屬層95。儘管在圖7中接點45及通路80藉由一金屬層95直接連接,但此僅係金屬接線之概念之一說明圖。可藉由形成於相同或不同接線層中之兩個或更多金屬層電連接接點45及通路80。 進一步言之,一鈍化層90進一步形成於金屬層95上方,以密封及保護金屬層95。鈍化層90可包含一介電材料(諸如氧化物或氮化矽),但可替代地使用其他適當介電質(諸如一高介電係數介電質或聚醯亞胺)。可使用一PECVD程序形成鈍化層90,但可替代地使用任何其他適當程序。在一些實施例中,鈍化層90之厚度在從約0.6 µm至約1.5 µm之一範圍中。 在某些實施例中,鈍化層90經圖案化以暴露金屬層95之至少一部分。可使用一適當光微影技術圖案化鈍化層90。在開口中,形成一前連接終端(未展示)。 如圖8中所展示,在完成針對基板之前側之製程之後,移除本體層30及無缺陷層20之一底部部分,以暴露位於開口60內之通路80之導電材料75以完成一TSV。可用一研磨程序(諸如一化學機械拋光(CMP)方法)來執行該移除,但可替代地使用其他適當程序(諸如蝕刻)。完全移除本體層30且部分移除無缺陷層20,使得無缺陷層20之剩餘厚度D3變為一所要厚度。在一些實施例中,厚度D3係厚度D1之約50%至約90%。在某些實施例中,D3在從約30 µm至約50 µm之一範圍中。 如圖9中所展示,在暴露通路80之底部後,形成一底部連接終端97。在一些實施例中,一上部連接終端98形成於金屬層95上以用於一外部連接。該上部連接終端及該底部連接終端可包括一導電層(諸如Ni、Au或其之一合金)。 如圖9中所展示,基板中之TSV 80由基板中之無缺陷層20環繞,且無包含BMD之本體層與TSV 80接觸。 如圖10中所展示,在其他實施例中,透過通路(TSV) 80電連接兩個基板。在圖10中,一第一基板100具有類似於圖8中所展示之結構之一結構。一第二基板200藉由相對於圖1至圖9揭露之操作形成,且包含一無缺陷層120、電子裝置140、一接點145、一第一ILD層150、兩個TSV 180、181、金屬層194、195、一第二ILD層190、及底部連接終端196、197。第二基板200進一步包含一連接終端198,藉由該連接終端198電連接第一基板100與第二基板200。當然,可藉由一類似方式堆疊兩個以上基板。 圖11及圖12展示繪示根據本揭露之一實施例之一TSV結構之一製程之例示性剖面圖。如上文所闡述之類似或相同組態、尺寸、程序、材料及/或結構可在下列實施例中被採用,且詳細解釋可被省略。 在圖11中,提供一基板15。基板15具有相同於基板10之組態。如圖12中所展示,一磊晶層20'形成於基板15上方。例如,在此實施例中,基板15係一Si基板(晶圓)且磊晶層20'係一Si磊晶層。形成磊晶層20'之後,執行相對於圖3至圖9揭露之操作。 由於層20'係藉由一磊晶生長方法形成,故磊晶層20'實質上無缺陷(即,無缺陷層)。無缺陷層20'中之BMD密度實質上為0 (例如,小於100 cm -3)。在某些實施例中,無缺陷層20'中之BMD密度為0。 在一些實施例中,無缺陷層20'之厚度D1'在從約30 µm至約200 µm之一範圍中。在某些實施例中,D1'等於或大於約50 µm。基板15可被稱作一本體層30',該本體層30'仍包含等於或大於1x10 8cm -3之BMD。類似於前述實施例,無缺陷層20'之厚度Dl'係使得開口60 (參見圖4)之底部未到達基板15 (本體層30')之一厚度。 圖13展示繪示根據本揭露之另一實施例之一TSV結構之一製程之一例示性剖面圖。如上文所闡述之類似或相同組態、尺寸、程序、材料及/或結構可在下列實施例中被採用,且詳細解釋可被省略。 在此實施例中,無缺陷區22選擇性地形成於基板10之一區域81中,在該區域81中隨後形成開口60 (TSV 80)(參見圖4及圖6)。為了選擇性地施加熱以形成無缺陷區22,例如,可使用一雷射退火方法300。藉由應用雷射300,在約1200℃至約1250℃下局部地加熱基板10,且該被加熱區域變為一無BMD區22。 亦可自基板10之背側應用雷射300。在此一情況中,可從基板10之前表面至基板10之背表面形成無BMD區22。進一步言之,一開口60 (參見圖4)可形成為比圖4中之情況深。 圖14及圖15展示繪示根據本揭露之另一實施例之一TSV結構之一製程之例示性剖面圖。如上文所闡述之類似或相同組態、尺寸、程序、材料及/或結構可在下列實施例中被採用,且詳細解釋可被省略。 在此實施例中,在基板10之一區域81中隨後形成開口60 (TSV 80)。 如圖14中所展示,藉由使用一遮罩圖案410蝕刻基板10以在基板10之一區域81中形成一開口420,在區域81中隨後形成開口60 (TSV 80)。遮罩圖案410可包含一層或多個層之氧化矽及氮化矽。在遮罩圖案410保留於基板10上之情況下,執行一選擇性磊晶生長以在開口420中形成一磊晶層23 (即,一無缺陷層)。隨後,移除遮罩圖案410。在一些實施例中,使用一平坦化操作(諸如化學機械拋光(CMP))以移除一過量磊晶層。 本文描述之各種實施例或實例提供優於既有技術之若干優點。例如,在本揭露中,由於一無缺陷層形成於基板中或基板上且用於一TSV之一開口未到達具有BMD之一本體層,故可防止否則由BMD引起之對TSV之不利效應。進一步言之,由於具有BMD之該本體層仍保持於電子裝置下方,故可將該本體層用作一金屬雜質吸氣層。 應瞭解並非全部優點必須在本文中已論述,對於全部實施例或實例不需要特定優點,且其他實施例或實例可提供不同優點。 根據本揭露之一態樣,在一種製造一半導體裝置之方法中,在一基板上執行一熱處理,藉此在該基板之一上部層中形成一無缺陷層,其中該基板之一剩餘層係一本體層。該本體層包含作為缺陷之本體微缺陷且該本體層中之一缺陷密度等於或大於1x10 8cm -3。一電子裝置形成於該無缺陷層上方。一開口形成於該無缺陷層中,使得該開口未到達該本體層。用一導電材料填充該開口,藉此形成一通路。移除該本體層,使得暴露該通路之一底部部分。該無缺陷層中之一缺陷密度小於100 cm -3。 根據本揭露之另一態樣,在一種製造一半導體裝置之方法中,一電子裝置形成於具有一無缺陷層及一本體層之一基板上方。該本體層包含作為缺陷之本體微缺陷且該本體層中之一缺陷密度等於或大於1×10 8cm -3。一開口形成於該無缺陷層中,使得該開口未到達該本體層。用一導電材料填充該開口,藉此形成一通路。移除該本體層,使得暴露該通路之一底部部分。該無缺陷層中之一缺陷密度小於100 cm -3。 根據本揭露之另一態樣,一半導體裝置包括:一第一基板,其具有一第一電子裝置及電連接至該第一電子裝置之一連接終端;及一第二基板,其具有一第二電子裝置及穿過該第二基板且電連接至該第二電子裝置之一通路。該第一基板附接至該第二基板,使得該連接終端與該通路接觸,且該通路由該第二基板之一無缺陷層環繞。該無缺陷層中之一缺陷密度小於100 cm -3,其中該等缺陷係本體微缺陷。 上文概述若干實施例或實例之特徵,使得熟習此項技術者可更好地理解本揭露之態樣。熟習此項技術者應瞭解其等可輕易使用本揭露作為用於設計或修改用於實施本文介紹之實施例或實例之相同目的及/或達成本文介紹之實施例或實例之相同優點之其他程序及結構之一基礎。熟習此項技術者亦應明白此等等效構造不脫離本揭露之精神及範疇,且其等可在不脫離本揭露之精神及範疇之情況下在本文中進行各種改變、置換及變更。
10 基板/矽基板 11 第一側 12 第二(後)側 15 基板 20 無缺陷層(無BMD層或剝蝕區) 20' 磊晶層/無缺陷層 22 無缺陷區/無BMD區 23 磊晶層 30 本體層 30' 本體層 40 MOSFET/電子裝置 45 接點 50 層間介電(ILD)層 60 開口 70 阻障層 75 主導電層/導電材料 80 通路/貫穿矽通路(TSV) 81 區域 90 鈍化層 95 金屬層 97 底部連接終端 98 上部連接終端 100 第一基板 120 無缺陷層 140 電子裝置 145 接點 150 第一ILD層 180 貫穿矽通路(TSV) 181 貫穿矽通路(TSV) 190 第二ILD層 194 金屬層 195 金屬層 196 底部連接終端 197 底部連接終端 198 連接終端 200 第二基板 300 雷射 410 遮罩圖案 420 開口 D1 厚度(深度) D1' 厚度 D2 深度 D3 剩餘厚度 W1 直徑
當與隨附圖式一起閱讀時,從下文詳細描述最佳理解本揭露。應強調,根據行業中之標準實踐,各種構件未按比例繪製且僅係用於繪示之目的。事實上,為論述之清楚起見,可任意增大或減小各種構件之尺寸。 圖1展示繪示根據本揭露之一實施例之一貫穿矽通路(TSV)結構之一製程之階段之一者之一例示性剖面圖。 圖2展示繪示根據本揭露之一實施例之一貫穿矽通路(TSV)結構之一製程之階段之一者之一例示性剖面圖。 圖3展示繪示根據本揭露之一實施例之一貫穿矽通路(TSV)結構之一製程之階段之一者之一例示性剖面圖。 圖4展示繪示根據本揭露之一實施例之一貫穿矽通路(TSV)結構之一製程之階段之一者之一例示性剖面圖。 圖5展示繪示根據本揭露之一實施例之一貫穿矽通路(TSV)結構之一製程之階段之一者之一例示性剖面圖。 圖6展示繪示根據本揭露之一實施例之一貫穿矽通路(TSV)結構之一製程之階段之一者之一例示性剖面圖。 圖7展示繪示根據本揭露之一實施例之一貫穿矽通路(TSV)結構之一製程之階段之一者之一例示性剖面圖。 圖8展示繪示根據本揭露之一實施例之一貫穿矽通路(TSV)結構之一製程之階段之一者之一例示性剖面圖。 圖9展示繪示根據本揭露之一實施例之一貫穿矽通路(TSV)結構之一製程之階段之一者之一例示性剖面圖。 圖10展示根據本揭露之另一實施例之一例示性裝置結構。 圖11展示繪示根據本揭露之一實施例之一TSV結構之一製程之階段之一者之一例示性剖面圖。 圖12展示繪示根據本揭露之一實施例之一TSV結構之一製程之階段之一者之一例示性剖面圖。 圖13展示繪示根據本揭露之另一實施例之一TSV結構之一製程之一例示性剖面圖。 圖14展示繪示根據本揭露之另一實施例之一TSV結構之一製程之階段之一者之一例示性剖面圖。 圖15展示繪示根據本揭露之另一實施例之一TSV結構之一製程之階段之一者之一例示性剖面圖。

Claims (10)

  1. 一種製造一半導體裝置之方法,其包括:在一基板上執行一熱處理,藉此在該基板之一上部層中形成一無缺陷層,該基板之一剩餘層為一本體層,該本體層包含作為缺陷之本體微缺陷且該本體層中之一缺陷密度等於或大於1×108cm-3;在該無缺陷層上方形成一電子裝置;在該無缺陷層中形成一開口,使得該開口未到達該本體層;用一導電材料填充該開口,藉此形成一通路;及移除該本體層,使得暴露該通路之一底部部分,其中該無缺陷層中之一缺陷密度小於100cm-3
  2. 如請求項1之方法,其中該無缺陷層中之該缺陷密度為零。
  3. 如請求項1之方法,其中在形成該電子裝置之前該無缺陷層之一厚度在從30μm至200μm之一範圍中。
  4. 如請求項1之方法,其中在該熱處理中,在從1010℃至1040℃之一範圍中之一溫度下加熱該基板。
  5. 如請求項4之方法,其中執行該熱處理達在從10秒至15秒之一範圍中之一時間段。
  6. 如請求項5之方法,其中,在執行該熱處理之後,依在從15℃/sec至25℃/sec之一範圍中之一冷卻速率執行一冷卻程序。
  7. 如請求項1之方法,其中在從1200℃至1250℃之一範圍中之一溫度下執行該熱處理。
  8. 如請求項1之方法,其進一步包括:將具有一連接終端之另一基板附接至其中該通路被暴露之該基板之一底部表面,使得該暴露的通路連接至該連接終端。
  9. 一種製造一半導體裝置之方法,其包括:在具有一無缺陷層及一本體層之一基板上方形成一電子裝置;該本體層包含作為缺陷之本體微缺陷且該本體層中之一缺陷密度等於或大於1x108cm-3;在該無缺陷層中形成一開口,使得該開口未到達該本體層;用一導電材料填充該開口,藉此形成一通路;及移除該本體層,使得暴露該通路之一底部部分,其中該無缺陷層中之一缺陷密度小於100cm-3
  10. 一種半導體裝置,其包括:一第一基板,其具有一第一電子裝置及電連接至該第一電子裝置之一連接終端;及一第二基板,其具有一第二電子裝置及穿過該第二基板且電連接至 該第二電子裝置之一通路,其中:該第一基板附接至該第二基板,使得該連接終端與該通路以及該第二基板接觸,該通路由該第二基板之一無缺陷層環繞,該無缺陷層之一缺陷密度小於100cm-3,且該等缺陷係本體微缺陷。
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06295912A (ja) * 1993-04-09 1994-10-21 Toshiba Ceramics Co Ltd シリコンウエハの製造方法およびシリコンウエハ
TW201230279A (en) * 2011-01-03 2012-07-16 Nanya Technology Corp Integrated circuit device and method of forming the same
US20130267046A1 (en) * 2012-04-09 2013-10-10 Zvi Or-Bach Method for fabrication of a semiconductor device and structure
TW201442208A (zh) * 2013-03-07 2014-11-01 Qualcomm Inc 半導體積體電路的單片式三維整合
TW201546902A (zh) * 2014-04-11 2015-12-16 Globalwafers Japan Co Ltd 矽晶圓之熱處理方法、及矽晶圓

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4703129B2 (ja) * 2004-05-06 2011-06-15 富士通セミコンダクター株式会社 半導体装置およびその製造方法、設計方法
US7485508B2 (en) * 2007-01-26 2009-02-03 International Business Machines Corporation Two-sided semiconductor-on-insulator structures and methods of manufacturing the same
US7713852B2 (en) 2007-06-12 2010-05-11 Taiwan Semiconductor Manufacturing Co., Ltd. Methods for forming field effect transistors and EPI-substrate
US7704869B2 (en) * 2007-09-11 2010-04-27 International Business Machines Corporation Method of fabricating ultra-deep vias and three-dimensional integrated circuits using ultra-deep vias
US8853830B2 (en) * 2008-05-14 2014-10-07 Taiwan Semiconductor Manufacturing Company, Ltd. System, structure, and method of manufacturing a semiconductor substrate stack
US8299583B2 (en) * 2009-03-05 2012-10-30 International Business Machines Corporation Two-sided semiconductor structure
US8344513B2 (en) 2009-03-23 2013-01-01 Taiwan Semiconductor Manufacturing Company, Ltd. Barrier for through-silicon via
US8748288B2 (en) * 2010-02-05 2014-06-10 International Business Machines Corporation Bonded structure with enhanced adhesion strength
US8865507B2 (en) * 2011-09-16 2014-10-21 Sionyx, Inc. Integrated visible and infrared imager devices and associated methods
US9786636B2 (en) * 2012-12-22 2017-10-10 Monolithic 3D Inc. Semiconductor device and structure
US9385058B1 (en) * 2012-12-29 2016-07-05 Monolithic 3D Inc. Semiconductor device and structure
US8907494B2 (en) 2013-03-14 2014-12-09 International Business Machines Corporation Electrical leakage reduction in stacked integrated circuits having through-silicon-via (TSV) structures
US9831273B2 (en) * 2013-12-23 2017-11-28 University Of Houston System Flexible single-crystalline semiconductor device and fabrication methods thereof
US9472545B2 (en) * 2014-01-31 2016-10-18 Taiwan Semiconductor Manufacturing Company Limited Semiconductor arrangement with electrostatic discharge (ESD) protection

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06295912A (ja) * 1993-04-09 1994-10-21 Toshiba Ceramics Co Ltd シリコンウエハの製造方法およびシリコンウエハ
TW201230279A (en) * 2011-01-03 2012-07-16 Nanya Technology Corp Integrated circuit device and method of forming the same
US20130267046A1 (en) * 2012-04-09 2013-10-10 Zvi Or-Bach Method for fabrication of a semiconductor device and structure
TW201442208A (zh) * 2013-03-07 2014-11-01 Qualcomm Inc 半導體積體電路的單片式三維整合
TW201546902A (zh) * 2014-04-11 2015-12-16 Globalwafers Japan Co Ltd 矽晶圓之熱處理方法、及矽晶圓

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