CN107887326A - 半导体器件及其制造方法 - Google Patents
半导体器件及其制造方法 Download PDFInfo
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- CN107887326A CN107887326A CN201710367672.XA CN201710367672A CN107887326A CN 107887326 A CN107887326 A CN 107887326A CN 201710367672 A CN201710367672 A CN 201710367672A CN 107887326 A CN107887326 A CN 107887326A
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- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
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Abstract
在制造半导体器件的方法中,对衬底实施热处理,从而在衬底的上层中形成无缺陷层,其中衬底的剩余层是块状层。块状层中的缺陷的密度等于或大于1×108cm‑3,其中缺陷是块状微缺陷。在无缺陷层上方形成电子器件。在无缺陷层中形成开口,使得开口不到达块状层。用导电材料填充开口,从而形成通孔。去除块状层,使得暴露通孔的底部。无缺陷层中的缺陷的密度小于100cm‑3。本发明的实施例还涉及半导体器件。
Description
技术领域
本发明通常涉及半导体器件,并且更具体地,涉及具有硅通孔的半导体器件及其制造方法。
背景技术
通过首先至少部分地在半导体晶圆(例如,Si衬底)中形成开口,并在开口中形成导电材料来在半导体晶圆中形成硅通孔(TSV)。TSV电连接形成在衬底的正面上的电子器件(例如,晶体管)和形成在衬底的后(背)面处的端子。
发明内容
本发明的实施例提供了一种制造半导体器件的方法,包括:对衬底实施热处理,从而在所述衬底的上层中形成无缺陷层,所述衬底的剩余层为块状层,所述块状层包含作为缺陷的块状微缺陷并且所述块状层中的缺陷的密度等于或大于1×108cm-3;在所述无缺陷层上方形成电子器件;在所述无缺陷层中形成开口,使得所述开口不到达所述块状层;用导电材料填充所述开口,从而形成通孔;以及去除所述块状层,使得暴露所述通孔的底部,其中,所述无缺陷层中的缺陷的密度小于100cm-3。
本发明的另一实施例提供了一种制造半导体器件的方法,包括:在具有无缺陷层和块状层的衬底上方形成电子器件,所述块状层包含作为缺陷的块状微缺陷并且所述块状层中的缺陷的密度等于或大于1×108cm-3;在所述无缺陷层中形成开口,使得所述开口不到达所述块状层;用导电材料填充所述开口,从而形成通孔;以及去除所述块状层,使得暴露所述通孔的底部,其中,所述无缺陷层中的缺陷的密度小于100cm-3。
本发明的又一实施例提供了一种半导体器件,包括:第一衬底,具有第一电子器件和电连接至所述第一电子器件的连接端子;以及第二衬底,具有第二电子器件和穿过所述第二衬底并且电连接至所述第二电子器件的通孔,其中:所述第一衬底附接至所述第二衬底,使得所述连接端子与所述通孔接触,所述通孔被所述第二衬底的无缺陷层围绕,所述无缺陷层中的缺陷的密度小于100cm-3,以及所述缺陷是块状微缺陷。
附图说明
当结合附图进行阅读时,从以下详细描述可最佳地理解本发明的各个方面。应该注意,根据工业中的标准实践,各个部件未按比例绘制。实际上,为了清楚的讨论,各种部件的尺寸可以被任意增大或减小。
图1示出了根据本发明的一个实施例示出的用于硅通孔(TSV)结构的制造工艺的一个阶段的示例性截面图。
图2示出了根据本发明的一个实施例示出的用于硅通孔(TSV)结构的制造工艺的一个阶段的示例性截面图。
图3示出了根据本发明的一个实施例示出的用于硅通孔(TSV)结构的制造工艺的一个阶段的示例性截面图。
图4示出了根据本发明的一个实施例示出的用于硅通孔(TSV)结构的制造工艺的一个阶段的示例性截面图。
图5示出了根据本发明的一个实施例示出的用于硅通孔(TSV)结构的制造工艺的一个阶段的示例性截面图。
图6示出了根据本发明的一个实施例示出的用于硅通孔(TSV)结构的制造工艺的一个阶段的示例性截面图。
图7示出了根据本发明的一个实施例示出的用于硅通孔(TSV)结构的制造工艺的一个阶段的示例性截面图。
图8示出了根据本发明的一个实施例示出的用于硅通孔(TSV)结构的制造工艺的一个阶段的示例性截面图。
图9示出了根据本发明的一个实施例示出的用于硅通孔(TSV)结构的制造工艺的一个阶段的示例性截面图。
图10示出了根据本发明的另一实施例的示例性器件结构。
图11示出了根据本发明的一个实施例示出的用于TSV结构的制造工艺的一个阶段的示例性截面图。
图12示出了根据本发明的一个实施例示出的用于TSV结构的制造工艺的一个阶段的示例性截面图。
图13示出了根据本发明的另一实施例示出的TSV结构的制造工艺的示例性截面图。
图14示出了根据本发明的另一实施例示出的用于TSV结构的制造工艺的一个阶段的示例性截面图。
图15示出了根据本发明的另一实施例示出的用于TSV结构的制造工艺的一个阶段的示例性截面图。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然,这些仅仅是实例,而不旨在限制本发明。例如,在以下描述中,在第二部件上方或者上形成第一部件可以包括第一部件和第二部件以直接接触的方式形成的实施例,并且也可以包括在第一部件和第二部件之间可以形成额外的部件,从而使得第一部件和第二部件可以不直接接触的实施例。此外,本发明可在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的,并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且,为了便于描述,在此可以使用诸如“在…下方”、“在…下面”、“下部”、“在…之上”、“上部”等空间相对术语以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外,空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上),并且在此使用的空间相对描述符可以同样地作出相应的解释。
图1至图9示出了根据本发明的一个实施例示出的硅通孔(TSV)结构的制造工艺的示例性截面图。TSV的通常制造操作可以在美国专利号8,680,682中找到,其全部内容结合于此作为参考。例如,首先在衬底上形成层间介电层;之后在层间介电层上形成衬垫和阻挡层;然后在阻挡层上方形成晶种层,在晶种层上镀导电材料;可以通过平坦化操作去除衬底的前侧上的多余的导电材料,之后去除衬底的后侧的部分,以露出导电材料,从而实现TSV。
在图1中,提供衬底10。衬底10具有第一(例如,前)侧11和与第一侧11相对的第二(后)侧12,并且可以是掺杂有杂质或未掺杂的块状硅晶圆或绝缘体上硅(SOI)衬底的有源层。衬底10可以包括诸如SiC和SiGe的Ⅳ-Ⅳ族化合物半导体、诸如GaAs、GaP、GaN、InP、InAs、InSb、GaAsP、AlGaN、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP的Ⅲ-Ⅴ族化合物半导体,或它们的组合的其他半导体。
在一个实施例中,使用Si衬底(晶圆)。通常,由晶圆制造提供的硅晶圆包括诸如块状微缺陷(BMD)的缺陷。BMD通常是指硅中的氧沉淀,并且可以包括氧沉淀、空隙、包含物、滑移线等。晶体起源的颗粒(或凹坑)(COP)可以包括在BMD中。
位于电子器件(例如,MOS晶体管)下面的硅层中的BMD作为吸杂位点以使杂质远离MOS晶体管。可以通过用IR(红外)光照射样品并用对IR敏感的照相机观察样品来检测BMD。
在本发明的一个实施例中,硅衬底10中的BMD密度(初始数)等于或大于1×108cm-3。可以通过诸如SEMI标准或JEITA标准的工业标准来定义通过CZ方法形成的硅晶圆中的BMD的典型密度。可以通过计算由使用KOH的湿蚀刻创建的蚀刻凹坑来确定BMD的数量。
在本发明中,如图2所示,至少在衬底10的正面(上表面)区域中形成无缺陷层(无BMD层或洁净区)20。在晶圆工艺的开始处形成无缺陷层20。在一些实施例中,在任何离子注入、图案化或膜形成操作之前形成无缺陷层20。换言之,在由晶圆制造商制造的所谓的“裸晶圆”上实施用于形成无缺陷层20的操作。
在一个实施例中,实施热处理以形成无BMD层20。热处理可以包括快速热退火(RTA)方法,在炉中加热或激光退火方法。在清洁衬底10之后对衬底10实施热处理。
在一些实施例中,在热处理中,在从约1150℃至约1300℃的范围内的温度处加热衬底10。在特定实施例中,在从约1200℃至约1250℃的范围内的温度处加热衬底10。在一些实施例中,温度以从约50℃/秒至约100℃/秒的范围内的升温速率从例如室温(25℃)增加至所期望的温度。在一些实施例中,热处理实施的时间周期在从约5秒至约20秒的范围内。在特定实施例中,热处理实施的时间周期在从约10秒至约15秒的范围内。在一些实施例中,在上文中的温度下实施热处理之后,以从约10℃/秒至约30℃/秒的范围内的冷却速率实施冷却工艺。在特定实施例中,以从约15℃/秒至约25℃/秒的范围内的冷却速率实施冷却工艺。冷却速率低于升温速率。应当注意,较慢的冷却速率可以创建更宽的无缺陷层。可以通过具有不同冷却速率的多个步骤来实施冷却工艺。在一些实施例中,实施具有第一冷却速率的快速冷却操作,接着进行具有低于第一冷却速率的第二冷却速率的缓慢冷却操作。在这种情况下,第一冷却速率在从约15℃/秒至约30℃/秒的范围内,并且第二冷却速率在从约10℃/秒至约25℃/秒的范围内。可以实施降低冷却速率的三个或多个步骤。在特定实施例中,冷却速率逐渐降低。
通过调节温度、处理时间和冷却速率中的一个或多个,可以控制无缺陷层20的厚度(深度)D1。在一些实施例中,无缺陷层20的厚度D1在从约30μm至约200μm的范围内。在特定实施例中,D1等于或大于约50μm且等于或小于100μm,并且在另一实施例中,D1在约60μm至约90μm的范围内。衬底10的剩余层称为块状层30,其仍含有等于或大于1×108cm-3的BMD。应当注意,无缺陷层20不应该制造得太厚,因为位于电子器件下面的硅层中的BMD用作吸杂位点。
无缺陷层20中的BMD的密度大致为零(例如,小于100cm-3)。在特定实施例中,无缺陷层20中的BMD的密度为零。
在特定实施例中,根据热处理的方法,还在衬底10的底(后)面中形成无缺陷层。
如图3所示,在形成无缺陷层20之后,形成隔离结构(例如,浅沟槽隔离(STI)),实施离子注入操作,并且在无缺陷层上制造诸如MOS FET、金属引线和接触件等的电子器件。在图3中,仅示出被层间介电(ILD)层50覆盖的MOS FET 40和穿过ILD层50的接触件45作为电子器件的概念图。当然,还在衬底10上形成引线层、层间介电层和通孔/接触件的多层,或其他无源或有源电子器件,以提供整体电路设计的期望的结构和功能需求。可以使用任何合适的方法在衬底内或表面上形成电子器件。
通过化学汽相沉积(CVD)、溅射或任何其他合适的方法在衬底10和电子器件40上方形成ILD层50。ILD层50通常具有平坦的表面并且可以由氧化硅构成,但是可以可选地利用诸如低k材料的其他材料。
接触件45延伸穿过ILD层50以电接触电子器件40的至少一个。可通过使用光刻和蚀刻技术穿过ILD层50形成接触件45。接触件45可以包括阻挡层/粘合层(未示出)以防止接触件45和ILD层50之间的扩散并且在接触件45和ILD层50之间提供更好的粘合。在实施例中,阻挡层由钛、氮化钛、钽、氮化钽等的一层或多层形成。可以通过CVD、溅射或其他技术形成阻挡层。在一些实施例中,阻挡层可形成为约1nm至约50nm的组合厚度。接触件45可以由诸如高导电金属、低阻金属、元素金属、过渡金属等任何合适的导电材料形成。在示例性实施例中,接触件45由钨形成,但是可以可选地利用诸如铜、镍、钴、铝或它们的合金的其他材料。
如图4所示,形成穿过ILD层50并进入衬底10的无缺陷层20的开口60。在本发明中,如图4所示,开口60未到达衬底10的块状层30。在一些实施例中,开口60的底部与块状层30之间的距离在从约50nm至约200nm的范围内。
可以通过施加和显影合适的光刻胶(未示出),并且然后蚀刻ILD层50和衬底10的无缺陷层20的至少部分来形成开口60。开口60形成为至少比形成在内部但未到达块状层30的电子器件40更远地延伸入衬底10中。因此,从衬底10的上表面测量的开口的深度D2小于无缺陷层20的厚度D1。在一些实施例中,深度D2为无缺陷层20的厚度D1的约70%至约95%,并且在特定实施例中,D2为D1的约80%至约90%。此外,在一些实施例中,开口60具有在从约2μm至约70μm的范围内的直径W1。
然而,在其他实施例中,可以在ILD层50形成的同时或之前形成开口60。形成开口60的任何形成方法都包括在本主题的范围内。
如图5所示,在形成开口60之后,在开口60中并且在ILD层50的上表面上方形成阻挡层70和主导电层75。共形地形成阻挡层70以覆盖开口60的侧壁和底部,但是不完全填充开口60。在一些实施例中,阻挡层70的厚度在从约1nm至约100nm的范围内,并且在其他实施例中,该厚度在从约2nm至约10nm的范围内。通过共形地形成阻挡层70,阻挡层将具有沿着开口60的侧壁并且还沿着开口60的底部的大致相等的厚度。
可以使用诸如等离子体增强CVD、等离子体增强物理汽相沉积(PEPVD)和原子层沉积(ALD)的促进共形形成的工艺来形成阻挡层70。
阻挡层70包括Ti、TiN、Ta和TaN的一层或多层。此外,在一些实施例中,阻挡层70可以与诸如碳或氟的合金材料合金化,但是合金材料的含量通常不大于阻挡层70的约15%,并且可以小于阻挡层70的约5%。可以在ALD、PECVD或PEPVD工艺中形成阻挡层70期间通过前体之一引入合金材料。
主导电层75可以包括铜,但是可以可选地利用诸如铝、它们的合金、掺杂的多晶硅、它们的组合的其他合适的材料。可以通过将铜电镀到阻挡层70上,填充且过度填充开口60来形成主导电层75。在一些实施例中,在形成主导电层75之前在阻挡层上形成晶种层(未示出)。
如图6所示,一旦已经填充开口60,则通过诸如化学机械抛光(CMP)的平坦化工艺去除开口60外部的多余的阻挡层70和主导电层75,从而形成通孔80。
图7示出在TSV的形成中的进一步的工艺操作。在ILD层50上方形成金属层95以连接接触件45和通孔80。可以通过CVD、PVD或其他合适的方法形成金属层95。虽然在图7中通过一个金属层95直接连接接触件45和通孔80,这仅仅是金属引线的概念的示图。可以通过形成在相同或不同的引线层中的两个或多个金属层电连接接触件45和通孔80。
此外,在金属层95上方进一步形成钝化层90,以密封和保护金属层95。钝化层90可包括诸如氧化物或氮化硅的介电材料,但是可以可选地使用诸如高k电介质或聚酰亚胺的其他合适的电介质。可以使用PECVD工艺形成钝化层90,但是可以可选地使用任何其他合适的工艺。在一些实施例中,钝化层90的厚度在从约0.6μm至约1.5μm的范围内。
在特定实施例中,图案化钝化层90以暴露金属层95的至少一部分。可以使用合适的光刻技术来图案化钝化层90。在开口中,形成前连接端子(未示出)。
如图8所示,在完成用于衬底的前侧的制造工艺之后,去除块状层30和无缺陷层20的底部,以暴露位于开口60内的通孔80的导电材料75,以完成TSV。可以利用诸如化学机械抛光(CMP)方法的研磨工艺来实施去除,但是可以可选地使用诸如蚀刻的其他合适的工艺。完全去除块状层30并且部分地去除无缺陷层20,从而使得无缺陷层20的剩余厚度D3成为期望的厚度。在一些实施例中,厚度D3为厚度D1的约50%至约90%。在特定实施例中,D3在从约30μm至约50μm的范围内。
在暴露通孔80的底部之后,形成如图9所示的底部连接端子97。在一些实施例中,在金属层95上形成上部连接端子98,从而用于外部连接。上部和底部连接端子可以包括诸如Ni、Au或它们的合金的导电层。
如图9所示,衬底中的TSV 80被衬底中的无缺陷层20围绕,并且没有包含BMD的块状层与TSV 80接触。
在其他实施例中,如图10所示,两个衬底通过通孔(TSV)80电连接。在图10中,第一衬底100具有与图8示出的结构类似的结构。通过关于图1至图9公开的操作形成第二衬底200,并且第二衬底200包括无缺陷层120、电子器件140、接触件145、第一ILD层150、两个TSV180、181、金属层194、195、第二ILD层190和底部连接端子196、197。第二衬底200还包括连接端子198,第一衬底100和第二衬底200通过该连接端子198电连接。当然,可以通过类似的方式堆叠多于两个衬底。
图11和图12示出了根据本发明的一个实施例示出的TSV结构的制造工艺的示例性截面图。在以下实施例中可以采用与上述类似或相同的配置、尺寸、工艺、材料和/或结构,并且可以省略详细的说明。
在图11中,提供衬底15。衬底15具有与衬底10相同的配置。如图12所示,可以在衬底15上方形成外延层20’。在本实施例中,例如,衬底15是Si衬底(晶圆),并且外延层20’是Si外延层。在形成外延层20’之后,实施关于图3至图9公开的操作。
由于层20’是通过外延生长方法形成的,所以外延层20’是大致无缺陷的(即,无缺陷层)。无缺陷层20’中的BMD的密度大致为零(例如,小于100cm-3)。在特定实施例中,无缺陷层20’中的BMD的密度为零。
在一些实施例中,无缺陷层20’的厚度D1’在从约30μm至约200μm的范围内。在特定实施例中,D1’等于或大于约50μm。衬底15可称为块状层30’,其仍含有等于或大于1×108cm-3的BMD。类似于前述实施例,无缺陷层20’的厚度D1’为使得开口60的底部(参见图4)未到达衬底15(块状层30’)的厚度。
图13示出了根据本发明的另一实施例示出的TSV结构的制造工艺的示例性截面图。在以下实施例中可以采用与上述类似或相同的配置、尺寸、工艺、材料和/或结构,并且可以省略详细的说明。
在本实施例中,无缺陷区22选择性地形成在衬底10的区域81中,在该区域中后续形成开口60(TSV 80)(参见图4和图6)。为了选择性地施加热以形成无缺陷区22,例如,可以使用激光退火方法300。通过施加激光300,在约1200℃至约1250℃处局部加热衬底10,并且加热区变为无BMD区22。
还可以从衬底10的背侧施加激光300。在这种情况下,可以从衬底10的正面到背面形成无BMD区22。此外,开口60(参见图4)可以形成为比图4的情况更深。
图14和图15示出了根据本发明的另一实施例示出的TSV结构的制造工艺的示例性截面图。在以下实施例中可以采用与上述类似或相同的配置、尺寸、工艺、材料和/或结构,并且可以省略详细的说明。
在该实施例中,在衬底10的区域81中后续形成开口60(TSV 80)。
如图14所示,通过使用掩模图案410蚀刻衬底10,以在衬底10的后续形成开口60(TSV 80)的区域81中形成开口420。掩模图案410可以包括氧化硅和氮化硅的一层或多层。在掩模图案410保留在衬底10上的情况下,实施选择性外延生长以在开口420中形成外延层23,即,无缺陷层。后续地,去除掩模图案410。在一些实施例中,使用诸如化学机械抛光(CMP)的平坦化操作来去除多余的外延层。
本文描述的各个实施例或实例提供了优于现有技术的一些优势。例如,在本发明中,由于在衬底中或衬底上形成无缺陷层,并且用于TSV的开口未到达具有BMD的块状层,因此可以防止由BMD导致的对TSV的不利影响。此外,由于具有BMD的块状层仍然保留在电子器件下面,所以可以将块状层用作金属杂质吸杂层。
应该理解,在此不必讨论所有优势,没有特定的优势是所有实施例或实例都必需的,并且其他实施例或实例可提供不同的优势。
根据本发明的一个方面,在制造半导体器件的方法中,对衬底实施热处理,从而在衬底的上层中形成无缺陷层,其中衬底的剩余层是块状层。块状层包含作为缺陷的块状微缺陷,并且块状层中的缺陷的密度等于或大于1×108cm-3。在无缺陷层上方形成电子器件。在无缺陷层中形成开口,使得开口未到达块状层。用导电材料填充开口,从而形成通孔。去除块状层,使得暴露通孔的底部。无缺陷层中的缺陷的密度小于100cm-3。
在上述方法中,其中,所述无缺陷层中的所述缺陷的密度是零。
在上述方法中,其中,在形成所述电子器件之前,所述无缺陷层的厚度在从30μm至200μm的范围内。
在上述方法中,其中,在形成所述电子器件之前,所述无缺陷层的厚度在从30μm至200μm的范围内,所述开口的深度是所述无缺陷层的厚度的70%至90%。
在上述方法中,其中,在所述热处理中,在从1010℃至1040℃的范围内的温度处加热所述衬底。
在上述方法中,其中,在所述热处理中,在从1010℃至1040℃的范围内的温度处加热所述衬底,所述热处理实施的时间周期在从10秒至15秒的范围内。
在上述方法中,其中,在所述热处理中,在从1010℃至1040℃的范围内的温度处加热所述衬底,所述热处理实施的时间周期在从10秒至15秒的范围内,在实施所述热处理之后,以从15℃/秒至25℃/秒的范围内的冷却速率实施冷却工艺。
在上述方法中,其中,在从1200℃至1250℃的范围内的温度处实施所述热处理。
在上述方法中,其中,用所述导电材料填充所述开口包括:形成阻挡层;以及在所述阻挡层上形成主导电层。
在上述方法中,其中,用所述导电材料填充所述开口包括:形成阻挡层;以及在所述阻挡层上形成主导电层,所述阻挡层包括TiN、Ti、TaN和Ta的至少一种,并且所述主导电层包括Cu或Cu合金。
在上述方法中,还包括:将具有连接端子的另一衬底附接至所述衬底的底面,其中,暴露所述通孔,使得暴露的通孔连接至所述连接端子。
根据本发明的另一方面,在制造半导体器件的方法中,在具有无缺陷层和块状层的衬底上方形成电子器件。块状层包含作为缺陷的块状微缺陷,并且块状层中的缺陷的密度等于或大于1×108cm-3。在无缺陷层中形成开口,使得开口未到达块状层。用导电材料填充开口,从而形成通孔。去除块状层,使得暴露通孔的底部。无缺陷层中的缺陷的密度小于100cm-3。
在上述方法中,其中,所述无缺陷层是形成在所述块状层上的外延层。
在上述方法中,其中,所述无缺陷层是形成在所述块状层上的外延层,所述无缺陷层中的所述缺陷的密度是零。
在上述方法中,其中,所述无缺陷层是形成在所述块状层上的外延层,在形成所述电子器件之前,所述无缺陷层的厚度在从30μm至200μm的范围内。
在上述方法中,其中,所述无缺陷层是形成在所述块状层上的外延层,在形成所述电子器件之前,所述无缺陷层的厚度在从30μm至200μm的范围内,所述开口的深度是所述无缺陷层的厚度的70%至90%。
在上述方法中,其中,用所述导电材料填充所述开口包括:形成阻挡层;以及在所述阻挡层上形成主导电层。
在上述方法中,其中,用所述导电材料填充所述开口包括:形成阻挡层;以及在所述阻挡层上形成主导电层,所述阻挡层包括TiN、Ti、TaN和Ta的至少一种,并且所述主导电层包括Cu或Cu合金。
在上述方法中,还包括:在暴露的通孔上形成底部连接端子。
根据本发明的另一方面,半导体器件包括:具有第一电子器件和电连接至第一电子器件的连接端子的第一衬底;和具有第二电子器件和穿过第二衬底并且电连接至第二电子器件的通孔的第二衬底。第一衬底附接至第二衬底,使得连接端子与通孔接触,并且通孔被第二衬底的无缺陷层围绕。无缺陷层中的缺陷的密度小于100cm-3,其中缺陷是块状微缺陷。
上面概述了若干实施例的特征,使得本领域技术人员可以更好地理解本发明的各方面。本领域技术人员应该理解,他们可以容易地使用本发明作为基础来设计或修改用于实施与在此所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到,这种等同构造并不背离本发明的精神和范围,并且在不背离本发明的精神和范围的情况下,在此他们可以做出多种变化、替换以及改变。
Claims (10)
1.一种制造半导体器件的方法,包括:
对衬底实施热处理,从而在所述衬底的上层中形成无缺陷层,所述衬底的剩余层为块状层,所述块状层包含作为缺陷的块状微缺陷并且所述块状层中的缺陷的密度等于或大于1×108cm-3;
在所述无缺陷层上方形成电子器件;
在所述无缺陷层中形成开口,使得所述开口不到达所述块状层;
用导电材料填充所述开口,从而形成通孔;以及
去除所述块状层,使得暴露所述通孔的底部,
其中,所述无缺陷层中的缺陷的密度小于100cm-3。
2.根据权利要求1所述的方法,其中,所述无缺陷层中的所述缺陷的密度是零。
3.根据权利要求1所述的方法,其中,在形成所述电子器件之前,所述无缺陷层的厚度在从30μm至200μm的范围内。
4.根据权利要求3所述的方法,其中,所述开口的深度是所述无缺陷层的厚度的70%至90%。
5.根据权利要求1所述的方法,其中,在所述热处理中,在从1010℃至1040℃的范围内的温度处加热所述衬底。
6.根据权利要求5所述的方法,其中,所述热处理实施的时间周期在从10秒至15秒的范围内。
7.根据权利要求6所述的方法,其中,在实施所述热处理之后,以从15℃/秒至25℃/秒的范围内的冷却速率实施冷却工艺。
8.根据权利要求1所述的方法,其中,在从1200℃至1250℃的范围内的温度处实施所述热处理。
9.一种制造半导体器件的方法,包括:
在具有无缺陷层和块状层的衬底上方形成电子器件,所述块状层包含作为缺陷的块状微缺陷并且所述块状层中的缺陷的密度等于或大于1×108cm-3;
在所述无缺陷层中形成开口,使得所述开口不到达所述块状层;
用导电材料填充所述开口,从而形成通孔;以及
去除所述块状层,使得暴露所述通孔的底部,
其中,所述无缺陷层中的缺陷的密度小于100cm-3。
10.一种半导体器件,包括:
第一衬底,具有第一电子器件和电连接至所述第一电子器件的连接端子;以及
第二衬底,具有第二电子器件和穿过所述第二衬底并且电连接至所述第二电子器件的通孔,其中:
所述第一衬底附接至所述第二衬底,使得所述连接端子与所述通孔接触,
所述通孔被所述第二衬底的无缺陷层围绕,
所述无缺陷层中的缺陷的密度小于100cm-3,以及
所述缺陷是块状微缺陷。
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