CN110556334B - 用于半导体处理的方法以及半导体结构 - Google Patents

用于半导体处理的方法以及半导体结构 Download PDF

Info

Publication number
CN110556334B
CN110556334B CN201811382303.9A CN201811382303A CN110556334B CN 110556334 B CN110556334 B CN 110556334B CN 201811382303 A CN201811382303 A CN 201811382303A CN 110556334 B CN110556334 B CN 110556334B
Authority
CN
China
Prior art keywords
layer
carbon
precursor gas
dielectric layer
barrier layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201811382303.9A
Other languages
English (en)
Other versions
CN110556334A (zh
Inventor
郭家邦
李亚莲
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN110556334A publication Critical patent/CN110556334A/zh
Application granted granted Critical
Publication of CN110556334B publication Critical patent/CN110556334B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76843Barrier, adhesion or liner layers formed in openings in a dielectric
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/36Carbonitrides
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/455Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
    • C23C16/45523Pulsed gas flow or change of composition over time
    • C23C16/45525Atomic layer deposition [ALD]
    • C23C16/45527Atomic layer deposition [ALD] characterized by the ALD cycle, e.g. different flows or temperatures during half-reactions, unusual pulsing sequence, use of precursor mixtures or auxiliary reactants or activations
    • C23C16/45529Atomic layer deposition [ALD] characterized by the ALD cycle, e.g. different flows or temperatures during half-reactions, unusual pulsing sequence, use of precursor mixtures or auxiliary reactants or activations specially adapted for making a layer stack of alternating different compositions or gradient compositions
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/455Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
    • C23C16/45523Pulsed gas flow or change of composition over time
    • C23C16/45525Atomic layer deposition [ALD]
    • C23C16/45553Atomic layer deposition [ALD] characterized by the use of precursors specially adapted for ALD
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/56After-treatment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041Cleaning
    • H01L21/02057Cleaning during device manufacture
    • H01L21/02068Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/0228Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28556Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/7685Barrier, adhesion or liner layers the layer covering a conductive structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76853Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855After-treatment introducing at least one additional element into the layer
    • H01L21/76856After-treatment introducing at least one additional element into the layer by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76853Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76861Post-treatment or after-treatment not introducing additional chemical elements into the layer
    • H01L21/76862Bombardment with particles, e.g. treatment in noble gas plasmas; UV irradiation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76853Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76865Selective removal of parts of the layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528Geometry or layout of the interconnection structure
    • H01L23/5283Cross-sectional geometry
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45Ohmic electrodes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28556Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H01L21/28562Selective deposition
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32051Deposition of metallic or metal-silicide layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76843Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846Layer combinations
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226Via connections in a multilevel interconnection structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528Geometry or layout of the interconnection structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204Conductive materials
    • H01L23/53209Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53214Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
    • H01L23/53223Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204Conductive materials
    • H01L23/53209Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53233Copper alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204Conductive materials
    • H01L23/53209Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204Conductive materials
    • H01L23/53209Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53257Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal
    • H01L23/53266Additional layers associated with refractory-metal layers, e.g. adhesion, barrier, cladding layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329Insulating materials

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Organic Chemistry (AREA)
  • Metallurgy (AREA)
  • Mechanical Engineering (AREA)
  • Geometry (AREA)
  • Plasma & Fusion (AREA)
  • Ceramic Engineering (AREA)
  • Inorganic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Chemical Vapour Deposition (AREA)

Abstract

本发明描述的实施例一般涉及在半导体处理中形成用于导电部件的阻挡层的一种或多种方法以及形成的半导体结构。在一些实施例中,形成穿过介电层至导电部件的开口。在开口中沿着介电层的侧壁且在导电部件的表面上形成在阻挡层。形成阻挡层包括沉积包括使用前体气体的层。前体气体具有用于在导电部件的表面上的沉积的第一培养时间和用于在介电层的侧壁上的沉积的第二培养时间。第一培养时间大于第二培养时间。在开口中且在阻挡层上形成导电填充材料。

Description

用于半导体处理的方法以及半导体结构
技术领域
本发明的实施例总体涉及半导体领域,更具体地,涉及用于半导体处理的方法以及相应的半导体结构。
背景技术
半导体集成电路(IC)产业经历了指数型增长。IC材料和设计上的技术进步产生了多代IC,其中,每一代都具有比先前一代更小且更复杂的电路。在IC发展过程中,功能密度(例如,单位芯片面积上互连器件的数量)通常在增加,同时几何尺寸(例如,可使用制造工艺创建的最小组件(或线))减小。这种按比例缩小工艺通常通过提高生产效率和降低相关成本来提供益处。然而,按比例缩小也导致了前几代在较大几何尺寸下可能没有提出的挑战。
发明内容
根据本发明的一个方面,提供了一种用于半导体处理的方法,所述方法包括:形成穿过介电层至导电部件的开口;在所述开口中沿着所述介电层的侧壁且在所述导电部件的表面上形成阻挡层,形成所述阻挡层包括使用第一前体气体沉积层,所述第一前体气体具有在所述导电部件的表面上沉积的第一培养时间和在所述介电层的侧壁上沉积的第二培养时间,所述第一培养时间大于所述第二培养时间;以及在所述开口中且在所述阻挡层上形成导电填充材料。
根据本发明的另一个方面,提供了一种半导体结构,包括:第一介电层,位于衬底上方;第一导电部件,位于所述第一介电层中;第二介电层,位于所述第一介电层和所述第一导电部件上方;以及第二导电部件,位于所述第二介电层中并且接触所述第一导电部件;所述第二导电部件包括:阻挡层,沿着所述第二介电层的侧壁并且位于所述第一导电部件的表面上,所述阻挡层在所述第二介电层的侧壁处具有第一厚度,所述阻挡层在所述第一导电部件的表面处具有第二厚度,所述第一厚度大于所述第二厚度;和导电填充材料,位于所述阻挡层上。
根据本发明的又一方面,提供了一种用于半导体处理的方法,所述方法包括:形成穿过介电层至导电部件的开口;在所述开口中沿着所述介电层的侧壁并且在所述导电部件的表面上沉积含碳层,使用原子层沉积(ALD)工艺来沉积所述含碳层,所述原子层沉积工艺包括至少一个第一循环,包括:脉冲调制具有至少25原子百分比的碳浓度的前体气体;以及脉冲调制反应物气体;使所述含碳层致密化包括使所述含碳层暴露于等离子体,其中,在所述致密化之后,所述含碳层是阻挡层;以及在所述开口中且在所述阻挡层上形成导电填充材料。
附图说明
当结合附图进行阅读时,从以下详细描述可最佳地理解本发明的各个方面。应该注意,根据工业中的标准实践,各个部件未按比例绘制。实际上,为了清楚的讨论,各种部件的尺寸可以被任意增大或减小。
图1至图5是根据一些实施例的在用于形成导电部件的示例性方法期间的相应中间结构的截面图。
图6是根据一些实施例的用于形成导电部件中的阻挡层的方法的流程图。
图7是示出根据一些实施例的在导电部件中形成阻挡层的各个方面的图。
图8至图9是根据一些实施例的在用于形成导电部件的另一示例性方法期间的相应中间结构的截面图。
图10至图11是根据一些实施例的在用于形成导电部件的另一示例性方法期间的相应中间结构的截面图。
图12是根据一些实施例的用于形成导电部件中的阻挡层的方法的流程图。
图13是根据一些实施例的用于形成导电部件中的阻挡层的沉积工具的示意图。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然,这些仅仅是实例,而不旨在限制本发明。例如,在以下描述中,在第二部件上方或者上形成第一部件可以包括第一部件和第二部件以直接接触的方式形成的实施例,并且也可以包括在第一部件和第二部件之间可以形成额外的部件,从而使得第一部件和第二部件可以不直接接触的实施例。此外,本发明可在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的,并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且,为了便于描述,在此可以使用诸如“在…下方”、“在…下面”、“下部”、“在…之上”、“上部”等空间相对术语以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外,空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上),并且在此使用的空间相对描述符可以同样地做出相应的解释。
在此描述的实施例一般涉及用于在半导体处理中形成用于导电部件的阻挡层的一种或多种方法。通常,用于沉积层的沉积工艺(诸如原子层沉积(ALD))可以实现具有取决于下面的表面(诸如,介电表面或导电(例如,金属)表面)的培养时间差的前体,其中,在下面的表面上沉积该层。在一些实例中,在ALD工艺中使用富碳氮化钽前体气体来沉积用于实现阻挡层的富碳氮化钽层。在一些实例中,富碳氮化钽前体气体在介电表面上沉积富碳氮化钽层的培养时间小于低于在导电(例如,金属)表面上沉积富碳氮化坦层的培养时间。因此,与介电表面上相比,富碳氮化钽层在导电表面上具有减小的厚度。由于厚度减小,这些厚度有利于降低其上形成有该层的导电部件的电阻,同时在介电表面处保持足够的扩散阻挡性能。一些实例可以进一步实现例如贫碳氮化钽层和富碳氮化钽层,它们一起用于实现阻挡层。可以实现其他优势或益处。
这里描述的一些实施例是在后段制程(BEOL)处理的背景下。可以在其他背景下(诸如在中间段制程(MEOL)处理和其他背景下)实施其他实施例的范围内的其他工艺和结构。相对于所公开的实施例讨论各种修改;然而,可以对所公开的实施例进行其他修改,同时保持在本主题的范围内。本领域的普通技术人员将容易地理解,可以做出的其他修改预期在其他实施例的范围内。尽管以特定的顺序描述方法实施例,但是可以以任何逻辑顺序实施各个其他的方法实施例,并且可以包括比本文所描述的更少或更多的步骤。
图1至图5示出根据一些实施例的在用于形成导电部件的示例性方法期间的相应中间结构的截面图。图1示出在半导体衬底20上方形成第一介电层。半导体衬底20可以是或可以包括掺杂的(例如,用p型或n型掺杂剂)或不掺杂的块状半导体衬底、绝缘体上半导体(SOI)衬底等。在一些实施例中,半导体衬底20的半导体材料可以包括诸如硅(Si)和锗(Ge)的元素半导体;化合物半导体;合金半导体或它们的组合。
各种器件可以位于半导体衬底20上。例如,半导体衬底20可以包括诸如Fin FET(FinFET)、平面FET、垂直全环栅极(VGAA FET)等的场效应晶体管(FET);二极管;电容器;电感器;和其他器件。例如,器件可以完全形成在半导体衬底20内,半导体衬底20的部分和一个或多个上覆层的部分中,和/或完全形成在一个或多上覆层中。本文描述的处理可以用于形成和/或互连器件以形成集成电路。集成电路可以是诸如用于专用集成电路(ASIC)、处理器、存储器或其他电路的任何电路。
第一介电层22位于半导体衬底20之上。第一介电层22可以直接位于半导体衬底20上,或可以在第一介电层22和半导体衬底20之间设置任何数量的其他层。例如,第一介电层22可以是或包括层间电介质(ILD)或金属间电介质(IMD)。例如,第一介电层22可以是或包括具有小于约4.0(诸如约2.0或甚至更小)的k值的低k电介质。在一些实例中,第一介电层22包括磷硅酸盐玻璃(PSG)、硼磷硅酸盐玻璃(BPSG)、氟硅酸盐玻璃(FSG)、SiOxCy、旋涂玻璃、旋涂聚合物、硅碳材料、它们的化合物、它们的复合物或它们的组合。
导电部件24位于第一介电层22中和/或穿过第一介电层22。导电部件24可以是或包括晶体管的栅极结构、至晶体管的栅极结构和/或至晶体管的源极/漏极区的接触插塞、导线和/或导电通孔。例如,第一介电层22可以包括ILD,并且例如导电部件24可以包括使用替换栅极工艺形成在ILD中的栅电极(例如,钨、钴等)。在另一实例中,第一介电层22可以是ILD,并且导电部件24可以包括接触插塞。可以通过形成穿过ILD至例如形成在半导体衬底20上的晶体管的栅电极和/或源极/漏极区的开口来形成接触插塞。接触插塞可以包括粘附层(例如,Ti等)、位于粘附层上的阻挡层(例如,TiN等)以及位于阻挡层上的导电填充材料(例如,钨、钴等)。在又一实例中,第一介电层22可以是IMD,并且导电部件24可以包括导线和/或导电通孔(共同地或单独地称为“互连结构”)。可以通过例如使用镶嵌工艺形成穿过IMD和/或在IMD中的开口和/或凹槽来形成互连结构。互连结构可以包括例如沿着第一介电层22和金属填充材料(例如,铜等)的侧壁的阻挡层(如本文所述)。
蚀刻停止层(ESL)26位于第一介电层22和导电部件24上方。通常,ESL可以提供在形成例如导电通孔时停止蚀刻工艺的一种机制。ESL可以由具有与相邻层或组件不同的蚀刻选择性的介电材料形成。在第一介电层22和导电部件24的顶面上沉积ESL 26。ESL 26可以包括或是氮化硅、碳氮化硅、碳氧化硅、碳氮化物等或它们的组合,并且可以通过化学汽相沉积(CVD)、等离子体增强CVD(PECVD)、ALD或另一沉积技术来沉积。
第二介电层28位于ESL 26上方。例如,第二介电层28可以是或包括IMD。在ESL 26的顶面上沉积第二介电层28。例如,第二介电层28可以是或包括具有小于约4.0(诸如约2.0或甚至更小)的k值的低k电介质。在一些实例中,第二介电层28包括PSG、BPSG、FSG、SiOxCy、旋涂玻璃、旋涂聚合物、硅碳材料、它们的化合物、它们的复合物或它们的组合。可以使用诸如PECVD或可流动CVD(FCVD)的CVD;旋涂涂覆;或另一沉积技术来沉积第二介电层28。在一些实例中,可以实施化学机械平坦化(CMP)或另一平坦化工艺以平坦化第二介电层28的顶面。
图1的配置是用于在此处示出各个方面的实例。在其他实例中,可以包括、省略和/或修改各种其他层。本领域的普通技术人员将容易地理解可以进行的各种修改。
图2示出在ESL 26和第二介电层28中和/或穿过ESL 26和第二介电层28形成至导电部件24的开口30。开口30可以是或可以包括通孔开口、沟槽等。可以诸如在镶嵌工艺中使用光刻和蚀刻工艺形成开口30。蚀刻工艺可以包括反应离子蚀刻(RIE)、中性束蚀刻(NBE)、电感耦合等离子体(ICP)蚀刻等或它们的组合。蚀刻工艺可以是各向异性的。
开口30的侧壁示出为垂直的。在其他实例中,开口30的侧壁可以在朝向或远离开口30的底部的方向上逐渐缩小。例如,开口30可以具有正锥形轮廓或凹角轮廓。
图3示出沿着第二介电层28和ESL 26的侧壁并沿着导电部件24的上表面在开口30中形成阻挡层40。在第二介电层28的上表面上进一步形成阻挡层40。通常,在一些实例中,阻挡层40包括氮化钽。下面相对于图6更详细地描述形成阻挡层40的工艺。如图3所示,阻挡层40沿着导电部件24的上表面具有第一厚度T1并且沿着第二介电层28和ESL 26的侧壁具有第二厚度T2。通常,并且从图6的描述中将变得显而易见,第二厚度T2大于第一厚度T1。
图4示出在阻挡层40上形成填充开口30的导电填充材料42。导电填充材料42可以是或包括诸如铜、钨、钴、铝、钌等或它们的组合的金属填充物。可以通过诸如CVD、物理汽相沉积(PVD)、镀(例如,化学镀)等或它们的组合的任何可接受的沉积工艺沉积导电填充材料42。
图5示出去除多余的导电填充材料42和阻挡层40以在第二介电层28中形成导电部件(包括导电填充材料42和阻挡层40)。可以使用诸如CMP的平坦化工艺来去除多余的导电填充材料42和阻挡层40,以形成齐平的导电填充材料42、阻挡层40和第二介电层28的上表面。如图5所示,可以诸如在镶嵌互连结构中形成导电部件。
尽管在图中未示出,但是可以在第二介电层28和导电部件(包括导电填充材料42和阻挡层40)上方形成一个或多个额外的介电层。额外地,可以在一个或多个额外的介电层中形成与所示导电部件(包括导电填充材料42和阻挡层40)类似地形成的额外的导电部件并且接触所示导电部件的上表面。
图6是根据一些实施例的用于在导电部件中形成阻挡层40的方法的流程图。图6的方法包括实施清洁工艺(操作102)、沉积富碳氮化钽层(操作104)和实施等离子体处理(操作106)。在一些实例中,可以在同一工具室中原位实施清洁工艺、沉积和等离子体处理。
在操作102中,对图2的中间结构实施清洁工艺。清洁工艺可以从形成开口30的蚀刻工艺去除残余的材料,并且可以从导电部件24的顶面去除氧化物。在一些实例中,导电部件24可以是或可以包括铜,铜氧化物通过例如形成开口30的蚀刻工艺、在形成导电部件时的CMP工艺和/或其他工艺在铜的上表面处形成。在这些实例中,清洁工艺可以去除氧化铜。
在一些实例中,清洁工艺包括将图2的中间结构暴露于等离子体。等离子体可以还原形成在导电部件24上的氧化物。等离子体可以是或包括诸如氢气(H2)的还原气体。在一些实例中,等离子体是远程等离子体。
在操作104中,在清洁的中间结构上沉积富碳氮化钽层。图6示出在操作104中用于沉积富碳氮化钽层的ALD工艺,尽管在其他实例中,可以使用另一CVD工艺来沉积富碳氮化钽层。结合操作106的等离子体处理,ALD工艺可以称为等离子体增强ALD(PEALD)。操作104包括:依次脉冲调制(pulsing)室中的富碳氮化钽前体气体(操作110)、净化(操作112)室、脉冲调制室中的反应物气体(操作114)以及净化(操作116)室。在其他实例中,可以改变操作110、112、114和116的顺序,诸如在操作110之前实施操作114。操作110、112、114和116创建ALD工艺的循环。在操作118处,确定是否要重复另一循环,并且如果是,则再次实施从操作110开始的该循环。可以重复进行该循环直到已经实施了预定数量的循环以实现富碳氮化钽层的目标厚度。例如,在一些实例中,要实施的循环的数量在从10个循环至30个循环的范围内。
可以在具有从约2托至约5托的范围内的压力和从约250℃至约350℃,并且更具体地,从约275℃至约325℃的范围内的温度的室中实施ALD工艺。每个脉冲(操作110、114)的保压时间(soak time)可以在从约0.5秒至约10秒的范围内。用于每个净化(操作112、116)的持续时间可以在从约0.5秒至约10秒的范围内。
用于操作110的富碳氮化钽前体气体110可以是或包括Ta,[(3,4-η)-炔]三(N,N-烷基氨基)(Ta[N(CH3)2]3(C6H10))、Ta[N(C2H5)2]3NC(CH3)3等。在一些实例中,富碳氮化钽前体气体可具有等于或大于约25原子百分比(at.%)(诸如在从约25at.%至约40at.%的范围内)的碳浓度。用于操作114的反应物气体可以是或可以包括氨(NH3)、肼(N2H2)等。分别用于操作110、114的富碳氮化钽前体气体和反应物气体可以与载气(可以是诸如氩(Ar)的惰性气体)混合。此外,用于操作112、116的净化的气体可以是诸如氩(Ar)的惰性气体。
使用操作104中的示例性ALD工艺,富碳氮化钽层可以沉积为具有变化的厚度,其中,该变化的厚度取决于在其上沉积该层的表面。在一些实例中,与金属表面(例如,图3中的导电部件24的上表面)相比,所沉积的富碳氮化钽层在介电表面(例如,图3中的第二介电层28和ESL 26的侧壁)上具有更大的厚度。图7示出厚度上的这种差异的各个方面。图7是示出根据沉积循环数所沉积的层的厚度的图。基于实验性的第一数据点212的第一拟合线202示出沉积在低k电介质(例如,SiOxCy材料)的表面上的富碳氮化钽层的厚度,以及基于实验性的第二数据点214的第二拟合线204示出沉积在金属(例如,Cu)的表面上的富碳氮化钽层的厚度。相对于低k电介质的表面上的沉积,金属的表面上的沉积示出为延迟,这可以认为是由于与低k电介质的表面相比,用于金属的表面上的沉积的培养(incubation)时间较长。图7所示的培养时间差220示出较长的培养时间。在一些实例中,培养时间差220可导致低k电介质的表面上的厚度与金属的表面上的厚度之间的差在从约
Figure BDA0001872166380000081
至约
Figure BDA0001872166380000082
的范围内。在用于表面的培养时间过去之后,无论下面的表面如何,沉积的速率大致相同(例如,在彼此相差约3%内,诸如小于约2.1%)。
可以认为,与贫碳氮化钽前体气体相比,富碳氮化钽前体气体具有较大的空间位阻,其减少了金属(例如Cu)上的吸附。富碳氮化钽前体气体的大的有机(例如,含C)基团可以提供可能不与贫碳氮化钽前体气体一起存在的来自金属的排斥力。此外,与金属(例如,Cu)相比,低k电介质(例如,SiOxCy)可以具有较低的吸附激活能,这允许富碳氮化钽前体气体在ALD工艺的较早周期中与低k电介质反应得更多。
在操作106中,使用等离子体工艺处理操作104中沉积的富碳氮化钽层。等离子体工艺可以去除有机杂质。等离子体工艺也可以使富碳氮化钽层致密化,这可以改善层的扩散阻挡性能。在一些实例中,等离子体工艺利用电容耦合等离子体(CCP)。等离子体工艺可以将氢气(H2)与诸如氩气(Ar)的载气一起使用。氢气的流速可以在气体总流速(例如,氢气和载气的组合流速)的从约50%至约95%的范围内。等离子体工艺的压力可以在从约1Torr至约5Torr的范围内。等离子体工艺的温度可以在从约250℃至约350℃的范围内,该温度可以等于操作104中用于沉积的温度。等离子体工艺的等离子体发生器的功率可以在从约100W至约800W的范围内,并且等离子体发生器的频率可以是约13.56MHz,在从约20MHz至约40MHz的范围内或另一频率。等离子体工艺处理的持续时间可以在从约5秒至约120秒的范围内。
富碳氮化钽层可以吸附等离子体和/或与等离子体反应以耗尽富碳氮化钽层的碳并使富碳氮化钽层致密化。在一些实例中,所沉积的富碳氮化钽层可具有等于或大于约15at.%的碳浓度,诸如在从约15at.%至约35at.%的范围内(例如,约20at.%)。所沉积的富碳氮化钽层的密度可以在从约5g/cm3至约7g/cm3的范围内。在等离子体处理之后,可能耗尽来自富碳氮化钽层的碳,因此在等离子体处理之后,富碳氮化钽层可以称为氮化钽层,其可能是贫碳的。此外,氮化钽层可以比所沉积的富碳氮化钽层更致密。在等离子体处理之后,氮化钽层可具有在从约1at.%至约5at.%的范围内的碳浓度。在等离子体处理之后,氮化钽层的密度可以在从约11.0g/cm3至约12.0g/cm3的范围内。在等离子体处理之后,所形成的氮化钽层可以是图3的阻挡层40。
如前所述,阻挡层40的位于导电部件24的上表面上的第一厚度T1小于阻挡层40的位于第二介电层28的侧壁上的第二厚度T2。厚度T1、T2之间的差异很大程度上是由在图6的操作104中在沉积期间的培养时间的差异导致的。在特定实例中,第一厚度T1可以在从约
Figure BDA0001872166380000101
至约
Figure BDA0001872166380000102
的范围内,并且第二厚度T2可以为约
Figure BDA0001872166380000103
因此,在这个特定实例中,第一厚度T1比第二厚度T2小了第二厚度T2的约20%至约30%的范围内的量。在其他实例中,表示为百分比的差异可以根据例如第二厚度T2而变化。如前所述,在培养时间差之后,可以以例如大致相同的速率在例如导电部件24上和第二介电层28上沉积富碳氮化钽层。因此,尽管可以以各种厚度形成阻挡层40,但是厚度T1、T2之间的差异可以保持大致相同,并且随着例如第二厚度T2增加,厚度T1、T2之间的差异占第二厚度T2的百分比越小。
不同的厚度T1、T2可以实现阻挡层40对于第二介电层28的有益的阻挡性能,同时减少导电部件24和导电填充材料42之间的电阻。通常,位于导电部件24和导电填充材料42之间的阻挡层40越薄,导电部件24和导电填充材料42之间的电阻越低。相反地,导电填充材料42和第二介电层28之间的阻挡层40越厚,阻挡层40越能更好地防止导电填充材料42扩散到第二介电层28中。因此,阻挡层40能够通过沿着导电部件24具有较薄的第一厚度T1来实现较低的电阻,并且能够通过沿着第二介电层28的侧壁具有较厚的第二厚度T2来实现有益的阻挡性能。
下面描述的实例使用沉积的碳浓度变化(differential)的氮化钽层实现阻挡层。可以通过多个(例如,两个或多个)子层(例如,多层)和/或通过渐变层来实现碳浓度变化的氮化钽层。在多层实施方式中,通过使用富碳氮化钽前体气体和贫碳氮化钽前体气体中的不同气体或它们不同的混合物,多个子层中的每个可以沉积为具有不同浓度的碳,其中,碳的相应浓度在整个子层中大致均匀。在渐变层实施方式中,通过使用富碳氮化钽前体气体和贫碳氮化钽前体气体中的不同气体或它们不同的混合物,渐变层可以沉积为具有大致连续的浓度渐变的碳。
图8和图9是根据一些实施例的用于形成导电部件的示例性方法期间的相应中间结构的截面图。图8示出以上相对于图1和图2描述的半导体衬底20、第一介电层22、导电部件24、ESL 26、第二介电层28和开口30。
图8还示出沿着第二介电层28和ESL 26的侧壁并且沿着导电部件24的上表面在开口30中形成阻挡层40。在第二介电层28的上表面上进一步形成阻挡层。除其他之外,通过沉积第一子层50和位于第一子层50上的第二子层52来实现阻挡层。通常,在一些实例中,阻挡层包括氮化钽。下面相对于图12更详细地描述用于形成阻挡层的工艺,其中,该工艺包括沉积第一子层50和第二子层52。如图8所示,阻挡层40沿着导电部件24的上表面具有第一厚度T1并且沿着第二介电层28和ESL 26的侧壁具有第二厚度T2。通常,并且从图12的描述中将变得显而易见,第二厚度T2大于第一厚度T1。
图9示出在阻挡层上形成填充开口30的导电填充材料54,并且去除任何多余的导电填充材料54和阻挡层。导电填充材料54可以是或包括诸如铜、钨、钴、铝、钌等或它们的组合的金属填充物。可以通过诸如CVD、PVD、镀(例如,化学镀)等或它们的组合的任何可接受的沉积工艺沉积导电填充材料54。可以使用诸如CMP的平坦化工艺来去除多余的导电填充材料54和阻挡层,以形成齐平的导电填充材料54、阻挡层和第二介电层28的上表面。如图9所示,可以诸如在镶嵌互连结构中形成导电部件。
图10和图11是根据一些实施例的在用于形成导电部件的示例性方法期间的相应中间结构的截面图。图10示出以上相对于图1和图2描述的半导体衬底20、第一介电层22、导电部件24、ESL 26、第二介电层28和开口30。
图10还示出在开口30中沿着第二介电层28和ESL 26的侧壁并且沿着导电部件24的上表面形成阻挡层40。在第二介电层28的上表面上进一步形成阻挡层。除其他之外,通过沉积第一子层60、位于第一子层60上的第二子层62和位于第二子层62上的第三子层64来实现阻挡层。通常,在一些实例中,阻挡层包括氮化钽。下面相对于图12更详细地描述用于形成阻挡层的工艺,其中,该工艺包括沉积第一子层60、第二子层62和第三子层64。如图10所示,阻挡层40沿着导电部件24的上表面具有第一厚度T1并且沿着第二介电层28和ESL 26的侧壁具有第二厚度T2。通常,并且从图12的描述中将变得显而易见,第二厚度T2大于第一厚度T1。
图11示出在阻挡层上形成填充开口30的导电填充材料66,并且去除任何多余的导电填充材料66和阻挡层。导电填充材料66可以是或包括诸如铜、钨、钴、铝、钌等或它们的组合的金属填充物。可以通过诸如CVD、PVD、镀(例如,化学镀)等或它们的组合的任何可接受的沉积工艺沉积导电填充材料66。可以使用诸如CMP的平坦化工艺来去除多余的导电填充材料66和阻挡层,以形成齐平的导电填充材料66、阻挡层和第二介电层28的上表面。如图11所示,可以诸如在镶嵌互连结构中形成导电部件。
图12是根据一些实施例的用于在导电部件中形成图8和图10的阻挡层的方法的流程图。图12的方法包括实施清洁工艺(操作302)、沉积碳浓度变化的氮化钽层(操作304)和实施等离子体处理(操作306)。在一些实例中,可以在相同的工具室中原位实施清洁工艺、沉积和等离子体处理。清洁工艺和等离子体处理可以分别与图6的清洁工艺(操作102)和等离子体处理(操作106)相同或类似,并且因此,为了简洁,这里省略了这些工艺的细节。
操作304沉积其中具有变化的碳浓度的碳浓度变化的氮化钽层。在一些实例中,碳浓度变化的氮化钽层可以是均具有大致均匀但不同浓度的碳(例如,碳浓度步进增加或减少)的多个子层。在一些实例中,碳浓度变化的氮化钽层可以是具有大致连续的碳浓度渐变的层。在一些实例中,碳浓度变化的氮化钽层可以具有一个或多个子层的组合并且具有大致连续的渐变(例如,一个或多个子层均具有均匀浓度,同时一个或多个子层均有渐变浓度)。
在操作304中,在清洁的中间结构上(如相对于图6描述)沉积碳浓度变化的氮化钽层。图12示出在操作304中用于沉积碳浓度变化的氮化钽层的ALD工艺,尽管在其他实例中,可以使用另一CVD工艺来沉积碳浓度变化的氮化钽层。除了其他操作之外,操作304包括依次在室中脉冲调制富碳氮化钽前体气体和贫碳氮化钽前体气体中的一种或混合物(操作312),净化室(操作314),在室中脉冲调制反应物气体(操作316)以及净化室(操作318)。在其他实例中,可以改变操作312、314、316和318的顺序,诸如在操作312之前实施操作316。操作312、314、316和318创建ALD工艺的循环。
在实施初始循环之前,在操作310中,确定将要后续脉冲调制的富碳氮化钽前体气体、贫碳氮化钽前体气体和反应物气体的初始量或流速。可以基于ALD工艺的配方进行操作310处的确定,其可以根据各种设计考虑来实现期望的碳浓度变化的氮化钽层,在下面描述其中的一些。在进行操作310处的确定之后,实施包括操作312、314、316和318的循环。在操作320处,确定是否要重复另一循环。如果是,则在操作322中确定是否要为后续循环改变前体气体和/或反应气体的量。同样可以基于配方进行操作322的确定。如果操作322确定改变该量,然后在操作310中,确定将要后续脉冲调制的富碳氮化钽前体气体、贫碳氮化钽前体气体和反应物气体的量或流率,并且使用所确定的量实施另一循环。如果操作322确定不改变该量,则使用在先前周期中先前确定和实施的量来实施另一循环。可以实施预定数量的循环以实现碳浓度变化的氮化钽层的目标厚度。
可以在具有从约2托至约5托的范围内的压力和从约250℃至约350℃,并且更具体地,从约275℃至约325℃(诸如300℃)的范围内的温度的室中实施ALD工艺。每个脉冲调制(操作312、316)的保压时间可以在从约0.5秒至约10秒的范围内。用于每个净化(操作314、318)的持续时间可以在从约0.5秒至约10秒的范围内。
用于操作312的富碳氮化钽前体气体可以是或包括Ta,[(3,4-η)-炔]三(N,N-烷基氨基)(Ta[N(CH3)2]3(C6H10))、Ta[N(C2H5)2]3NC(CH3)3等。在一些实例中,富碳氮化钽前体气体可具有等于或大于约25at.%(诸如在从约25at.%至约40at.%的范围内)的碳浓度。用于操作312的贫碳氮化钽前体气体可以是或包括Ta[N(CH3)2]5等。在一些实例中,贫碳氮化钽前体气体可具有诸如在从约15at.%至小于约25at.%的范围内的小于约25at.%的碳浓度。用于操作316的反应物气体可以是或可以包括氨(NH3)、肼(N2H2)等。用于操作312、316的富碳氮化钽前体气体、贫碳氮化钽前体气体和反应物气体可以与载气(可以是诸如氩(Ar)的惰性气体)混合。此外,用于操作314、318的净化的气体可以是诸如氩(Ar)的惰性气体。
首先描述操作304的实现以获得图8和图9的阻挡层。在操作304中,使用富碳氮化钽前体气体而不使用贫碳氮化钽前体气体实施第一数量的循环以沉积第一子层50。额外地,可以以诸如等于或小于总流量(例如,组合的反应物气体和载气的流量)的10%的低百分比量在第一数量的循环中脉冲调制反应物气体。通过利用富碳氮化钽前体气体而不利用贫碳氮化钽前体气体来实施第一循环数,参考图6和图7描述的培养时间差可用于沉积在导电部件24的上表面上和第二介电层28的侧壁上具有不同的厚度的第一子层50(例如,富碳氮化钽层),其中,第一子层50在导电部件24的上表面上和第二介电层28的侧壁上具有不同的厚度。在一些实例中,第一循环数允许培养时间差过去(elapse)并且允许第一子层50开始在导电部件24的上表面上生长。因此,在这种实例中,可以实现第一子层50的厚度上(例如,在导电部件24上和第二介电层28上)的最大差异。在其他实例中,第一循环数可能不足以允许培养时间差过去。
为了更具体地将第一子层50的沉积与操作304相关联,在操作310处,前体气体的量确定为将在操作312中脉冲调制的100%富碳氮化钽前体气体和0%贫碳氮化钽前体气体作为前体气体(例如,不考虑载气),并且反应物气体的量确定为等于或小于将在操作316中脉冲调制的总流量(例如,组合的反应物气体和载气的流量)的10%。通过操作320,该循环(操作312、314、316、318)重复了第一循环数,而不通过操作322改变气体。
还在实施第一循环数之后的操作304中,使用贫碳氮化钽前体气体,而不使用富碳氮化钽前体气体实施第二循环数以沉积第二子层52(例如,贫碳氮化钽层)。额外地,可以在第二循环数中以诸如在总流量(例如,组合的反应物气体和载气的流量)的从约10%至约99%的范围内的高的百分比量脉冲调制反应物气体。在一些实例中,使用贫碳氮化钽前体气体的沉积通常不会表现出如上所述的富碳氮化钽前体气体可能发生的选择性。更具体地,在这些实例中,基于在其上沉积该层的下方的表面,通常不存在显著的培养时间差和沉积速率上的显著差异。因此,第二子层52的沉积可以是大致均匀且共形的。第二循环数足以形成具有期望厚度的第二子层52。
为了更具体地将第二子层52的沉积与操作304相关联,在完成第一循环数之后,在操作320处,确定重复该循环以启动第二循环数。在操作322处,确定将改变气体的量。作为响应,在操作310处,前体气体的量确定为将在操作312中脉冲调制的0%富碳氮化钽前体气体和100%贫碳氮化钽前体气体作为前体气体(例如,不考虑载气),并且反应物气体的量确定为将在操作316中脉冲调制的总流量(例如,组合的反应物气体和载气的流量)的从约10%至约99%的范围内。通过操作320,该循环(操作312、314、316、318)重复了第二循环数,而气体后续不会通过操作322改变。在第二循环数结束时,在操作320处,确定将不重复该循环,并且然后实施操作306。
在操作306中,使用等离子体工艺处理在操作304中沉积的碳浓度变化的氮化钽层。通常,等离子体工艺可以去除有机杂质并且还可以使碳浓度变化的氮化钽层致密化。
碳浓度变化的氮化钽层可以吸附等离子体和/或与等离子体反应以耗尽碳浓度变化的氮化钽层的碳并且使碳浓度变化的氮化钽层致密化。具有比贫碳氮化钽层(例如,第二子层52)更高浓度的碳的富碳氮化钽层(例如,第一子层50)可以在操作306中的等离子体处理期间减慢或阻止等离子体的穿透,其可以防止第二介电层28(例如,低k介电层)的一些碳耗尽和损坏。
在一些实例中,富碳氮化钽层可具有等于或大于约15at.%(例如,约20at.%)的碳浓度,诸如在从约15at.%至约35at.%的范围内,并且贫碳氮化钽前体气体可具有小于约15at.%的碳浓度,诸如在从约1at.%至约15at.%的范围内。所沉积的富碳氮化钽层的密度可以在从约5g/cm3至约7g/cm3的范围内,并且所沉积的贫碳氮化钽层的密度可以在从约8g/cm3至约10g/cm3的范围内。在等离子体处理之后,可能耗尽来自富碳氮化钽层和贫碳氮化钽层的碳,并且因此在等离子体处理之后,富碳氮化钽层和贫碳氮化钽层可以称为氮化钽层,该氮化钽层是贫碳的。此外,氮化钽层可以比所沉积的相应子层更致密。在等离子体处理之后,氮化钽层的第一子层50可具有在从约1at.%至约5at.%的范围内的碳浓度,并且氮化钽层的第二子层52可以具有在从约1at.%至约3at.%范围内的碳浓度。例如,第一子层50可以具有比第二子层52更大的碳浓度。在等离子体处理之后,氮化钽层的第一子层50的密度可以在从约10.5g/cm3至约11.5g/cm3的范围内,并且在等离子体处理之后,氮化钽层的第二子层52的密度可以在从约11.5g/cm3至约12.5g/cm3的范围内。例如,第二子层52可以比第一子层50更致密。氮化钽层(例如,包括第一子层50和第二子层52)的密度可以在从约11.0g/cm3至约12.0g/cm3的范围内。在等离子体处理之后,形成的氮化钽层可以是图8的阻挡层。
如前所述,阻挡层在导电部件24的上表面上的第一厚度T1小于阻挡层在第二介电层28的侧壁上的第二厚度T2。厚度T1、T2之间的差异很大程度上是由在图12的操作304中在第一子层50的沉积期间的培养时间的差异导致的。在特定实例中,第一厚度T1可以为约
Figure BDA0001872166380000161
并且第二厚度T2可以为约
Figure BDA0001872166380000162
因此,在这个特定实例中,第一厚度T1比第二厚度T2小了第二厚度T2的约34%的量。在其他实例中,表示为百分比的差异可以根据例如第二厚度T2而变化,类似于先前所描述的。更具体地,第一厚度T1处的第一子层50的厚度可以是约
Figure BDA0001872166380000163
并且第二厚度T2处的第一子层50的厚度可以是约
Figure BDA0001872166380000164
第二子层52的厚度可以大致均匀地为约
Figure BDA0001872166380000165
通过沉积包括富碳氮化钽层和贫碳氮化钽层的碳浓度变化的氮化钽层来形成阻挡层可以实现有益的阻挡性能,同时减少导电部件24与导电填充材料42之间的电阻。通常,如前所述,厚度T1、T2可以实现降低的电阻和有益的阻挡性能。此外,通过沉积贫碳氮化钽层来实施子层可以实现更好的阻挡性能,因为可以实现更大的密度,同时通过沉积富碳氮化钽层来实施子层可以减少或减轻否则可能由等离子体处理导致的第二介电层28(例如,低k电介质)中的损坏和碳耗尽。
接下来描述操作304的实现以获得图10和图11的阻挡层。在操作304中,使用富碳氮化钽前体气体而不使用贫碳氮化钽前体气体实施第一循环数以沉积第一子层60。额外地,可以以诸如等于或小于总流量(例如,组合的反应物气体和载气的流量)的10%的低百分比量在第一循环数中脉冲调制反应物气体。通过利用富碳氮化钽前体气体而不利用贫碳氮化钽前体气体来实施第一循环数,参考图6和图7描述的培养时间差可用于沉积第一子层60(例如,富碳氮化钽层),其中,第一子层60在导电部件24的上表面上和第二介电层28的侧壁上具有不同的厚度。在一些实例中,第一循环数允许培养时间差过去并且允许第一子层60开始在导电部件24的上表面上生长。因此,在这种实例中,可以实现第一子层60的厚度(例如,在导电部件24上和第二介电层28上)上的最大差异。在其他实例中,第一循环数不足以允许培养时间差过去。
为了更具体地将第一子层60的沉积与操作304相关联,在操作310处,前体气体的量确定为将在操作312中脉冲调制的100%富碳氮化钽前体气体和0%贫碳氮化钽前体气体作为前体气体(例如,不考虑载气),并且反应物气体的量确定为等于或小于将在操作316中脉冲调制的总流量(例如,组合的反应物气体和载气的流量)的10%。通过操作320,该循环(操作312、314、316、318)重复了第一循环数,而气体没有通过操作322改变。
还在实施第一数量的循环之后的操作304中,使用贫碳氮化钽前体气体和富碳氮化钽前体气体的混合物实施第二循环数以沉积第二子层62(例如,碳含量适中(carbon-moderate)的氮化钽层)。例如,混合物可以包括体积和流量大约相等的富碳氮化钽前体气体和贫碳氮化钽前体气体。额外地,在第二循环数中可以以总流量(例如,组合的反应物气体和载气的流量)的任何百分比量脉冲调制反应物气体。改变反应物气体的量可以改变所沉积的子层中的碳浓度。通常,假设其他条件相同,反应物气体的流量越大,所沉积的子层中的碳浓度越低,反之,反应物气体的流量越小,则所沉积的子层中的碳浓度越大。
为了更具体地将第二子层62的沉积与操作304相关联,在完成第一循环数之后,在操作320处,确定重复该循环以启动第二循环数。在操作322处,确定将改变气体的量。作为响应,在操作310处,例如,前体气体的量确定为将在操作312中脉冲调制的50%富碳氮化钽前体气体和50%贫碳氮化钽前体气体作为前体气体(例如,不考虑载气),并且反应物气体的量确定为在将操作316中脉冲调制的总流量(例如,组合的反应物气体和载气的流量)的从大于0%至约99%的范围内。通过操作320,该循环(操作312、314、316、318)重复了第二循环数,而后续不通过操作322改变气体。
还在实施第二循环数之后的操作304中,使用贫碳氮化钽前体气体,而不使用富碳氮化钽前体气体实施第三循环以沉积第二子层64(例如,贫碳氮化钽层)。此外,可以在第二循环数中以诸如在总流量(例如,组合的反应物气体和载气的流量)的从约10%至约99%的范围内的高的百分比量脉冲调制反应物气体。
为了更具体地将第三子层64的沉积与操作304相关联,在完成第二循环数之后,在操作320处,确定重复该循环以启动第三循环数。在操作322处,确定将改变气体的量。作为响应,在操作310处,前体气体的量确定为将在操作312中脉冲调制的0%富碳氮化钽前体气体和100%贫碳氮化钽前体气体作为前体气体(例如,不考虑载气),并且反应物气体的量确定为将在操作316中脉冲调制的总流量(例如,组合的反应物气体和载气的流量)的约10%至约99%的范围内。通过操作320,该循环(操作312、314、316、318)重复了第三循环数,而气体后续不会通过操作322改变。在第三循环数结束时,在操作320处,确定将不重复该循环,并且然后实施操作306。
在操作306中,使用等离子体工艺处理在操作304中沉积的碳浓度变化的氮化钽层。通常,等离子体工艺可以去除有机杂质并且还可以使碳浓度变化的氮化钽层致密化。
碳含量适中的氮化钽层(例如,第二子层62)可具有上述富碳氮化钽层和贫碳氮化钽层的性能范围之间的性能。因此,碳浓度变化的氮化钽层可以允许平衡和调整性能以实现期望的阻挡层。可以在碳浓度变化的氮化钽层中使用额外的层。
甚至进一步,通过增大其中通过操作322改变富碳氮化钽前体气体、贫碳氮化钽前体气体和/或反应物气体的相应量的次数,可相应地减少各气体的每次改变之间的循环数,其中,所沉积的碳浓度变化的氮化钽层开始可接近或成为可具有大致连续渐变的碳浓度的渐变层。这可以进一步允许平衡和调整性能以实现期望的阻挡层。
作为特定实例,假设将使用操作304的ALD工艺的19个循环来沉积碳浓度变化的氮化钽层。在用于第一循环的操作310中,待脉冲调制的气体确定为:符合上述说明的100%富碳氮化钽前体气体、0%贫碳氮化钽前体气体和5%反应物气体。第一循环使用这些量。在每个循环之后,在操作322处确定量是否将改变,并且在操作310处,该量确定为:减少5.55%的富碳氮化钽前体气体,增加5.55%的贫碳氮化钽前体气体、增加5%的反应物气体。在最后的循环(例如循环19)中,待脉冲调制的气体确定为:符合上述说明的0%富碳氮化钽前体气体、100%贫碳氮化钽前体气体和95%反应物气体。
图13是根据一些实施例的用于在导电部件中形成阻挡层的沉积工具的示意图。更具体地,沉积工具包括用于输送两种前体的双安瓿(ampoule)供应系统。沉积工具包括室402、第一安瓿404和第二安瓿406。室402中设置衬底保持器408。衬底保持器408在沉积工艺期间保持并固定衬底。室402还包括用于在室402内分配气体的气体喷射器410。流动管线412和阀414配置为并且可操作地将第一安瓿404和第二安瓿406流体连接至室402。流动管线412和阀414被配置且可操作为选择性地将来自第一安瓿404的第一前体A、来自第二安瓿406的第二前体B、一种或多种载气以及反应物气体输送至室,从而用于通过气体喷射器410进行分配。
沉积工具可以用于实施上述的沉积工艺。例如,可以选择性地打开或关闭各种阀414以开始或停止将各种气体输送至室402以实现室402中的环境416。假设第一前体A是富碳氮化钽前体气体且第二前体B是贫碳氮化钽前体气体,则可打开或关闭各种阀414以将仅第一前体A、仅第二前体B、或第一前体A和第二前体B的混合物(具有或不具有载气)输送至室402,从而用于例如脉冲调制操作312。类似地,可以打开或关闭各种阀414以将反应物气体输送至室402,从而用于例如脉冲调制操作316。此外,可以打开或关闭各种阀414以将载气输送至室402,从而用于例如净化操作314、318。
一个实施例是用于半导体处理的方法。形成穿过介电层至导电部件的开口。在开口中沿着介电层的侧壁并且在导电部件的表面上形成阻挡层。形成阻挡层包括沉积包括使用第一前体气体的层。第一前体气体具有用于导电部件的表面上的沉积的第一培养时间和具有用于介电层的侧壁上的沉积的第二培养时间。第一培养时间大于第二培养时间。在开口中且在阻挡层上形成导电填充材料。
在一些实施例中,所述阻挡层在所述介电层的侧壁处具有第一厚度,并且所述阻挡层在所述导电部件的表面处具有第二厚度,所述第一厚度大于所述第二厚度。
在一些实施例中,所述第一前体气体具有至少25原子百分比的碳浓度。
在一些实施例中,所述阻挡层包括氮化钽。
在一些实施例中,形成所述阻挡层还包括:通过所述开口对所述导电部件的表面实施清洁工艺,实施所述清洁工艺包括使用具有还原气体的等离子体;实施原子层沉积(ALD)工艺以沉积所述层,所述原子层沉积工艺包括至少一个循环,所述至少一个循环包括脉冲调制所述第一前体气体并且脉冲调制反应物气体;以及使所述层致密化以形成所述阻挡层,所述致密化包括将所述层暴露于等离子体。
在一些实施例中,沉积所述层包括实施多个循环,所述多个循环中的每个均包括:脉冲调制所述第一前体气体;以及脉冲调制反应物气体。
在一些实施例中,所述层是整体具有至少15原子百分比的碳浓度的含碳氮化钽层。
在一些实施例中,沉积所述层包括:实施多个第一循环;以及在实施所述多个第一循环之后,实施多个第二循环;其中,所述多个第一循环中的每个均包括:脉冲调制所述第一前体气体,而不是第二前体气体,其中,所述第一前体气体具有至少25原子百分比的碳浓度,其中,所述第二前体气体具有小于25原子百分比的碳浓度;和脉冲调制反应物气体;以及其中,所述多个第二循环中的每个均包括:脉冲调制所述第二前体气体,而不是所述第一前体气体;和脉冲调制所述反应物气体。
在一些实施例中,所述层包括:由所述多个第一循环形成的具有至少15原子百分比的碳浓度的第一含碳氮化钽子层;以及由所述多个第二循环形成的具有小于15原子百分比的碳浓度的第二含碳氮化钽子层。
在一些实施例中,沉积所述层包括:实施第一循环;在实施所述第一循环之后,实施第二循环;以及在实施所述第二循环之后,实施第三循环;其中,所述第一循环包括:脉冲调制所述第一前体气体,而不是第二前体气体,其中,所述第一前体气体具有至少25原子百分比的碳浓度,其中,所述第二前体气体具有小于25原子百分比的碳浓度;和脉冲调制反应物气体;以及其中,所述第二循环包括:脉冲调制包括所述第一前体气体和所述第二前体气体的混合物;和脉冲调制所述反应物气体;以及其中,所述第三循环包括:脉冲调制所述第二前体气体,而不是所述第一前体气体;和脉冲调制所述反应物气体。
在一些实施例中,所述层是具有渐变浓度的碳的含碳氮化钽层。
另一实施例是一种结构。该结构包括位于衬底上方的第一介电层、位于第一介电层中的第一导电部件、位于第一介电层和第一导电部件上方的第二介电层、位于第二介电层中且接触第一导电部件的第二导电部件。第二导电部件包括阻挡层和位于阻挡层上的导电填充材料。阻挡层沿着第二介电层的侧壁并且位于第一导电部件的表面上。阻挡层在第二介电层的侧壁处具有第一厚度,并且阻挡层在第一导电部件的表面处具有第二厚度。第一厚度大于第二厚度。
在一些实施例中,所述阻挡层包括氮化钽。
在一些实施例中,所述阻挡层具有在从1原子百分比至5原子百分比的范围内的碳浓度。
在一些实施例中,所述阻挡层具有从11.0g/cm3至12.0g/cm3的范围内的密度。
在一些实施例中,所述阻挡层包括靠近所述第二介电层的侧壁的第一部分和远离所述第二介电层的侧壁的第二部分,所述第一部分的碳浓度大于所述第二部分的碳浓度,其中,所述第二部分的密度大于所述第一部分的密度。
在一些实施例中,所述阻挡层包括靠近所述第二介电层的侧壁的第一部分和远离所述第二介电层的侧壁的第二部分,其中:所述第一部分具有在从1原子百分比至5原子百分比的范围内的碳浓度;所述第二部分具有在从1原子百分比至3原子百分比的范围内的碳浓度;所述第一部分的密度在从10.5g/cm3至11.5g/cm3的范围内;以及所述第二部分的密度在从11.5g/cm3至12.5g/cm3的范围内。
另一实施例是一种用于半导体处理的方法。形成穿过介电层至导电部件的开口。在开口中沿着介电层的侧壁并且在导电部件的表面上沉积含碳层。沉积含碳层包括使用原子层沉积(ALD)工艺。ALD工艺包括至少一个第一循环,其中,该第一循环包括脉冲调制具有至少25原子百分比的碳浓度的前体气体并且脉冲调制反应物气体。使含碳层致密化,并且致密化包括使含碳层暴露于等离子体。在致密化之后,含碳层是阻挡层。在开口中且在阻挡层上形成导电填充材料。
在一些实施例中,所述含碳层是含碳氮化钽层。
在一些实施例中,所述原子层沉积工艺还包括至少一个第二循环,包括:脉冲调制具有小于25原子百分比的碳浓度的前体气体;以及脉冲调制所述反应物气体。
上面概述了若干实施例的特征,使得本领域技术人员可以更好地理解本发明的各方面。本领域技术人员应该理解,他们可以容易地使用本发明作为基础来设计或修改用于实施与在此所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到,这种等同构造并不背离本发明的精神和范围,并且在不背离本发明的精神和范围的情况下,在此他们可以做出多种变化、替换以及改变。

Claims (20)

1.一种用于半导体处理的方法,所述方法包括:
形成穿过介电层至导电部件的开口;
在所述开口中沿着所述介电层的侧壁且在所述导电部件的表面上形成阻挡层,形成所述阻挡层包括使用包含第一前体气体的含碳前体沉积含碳层以及使所述含碳层致密化以形成所述阻挡层,其中,所述第一前体气体具有在所述导电部件的表面上沉积的第一培养时间和在所述介电层的侧壁上沉积的第二培养时间,所述第一培养时间大于所述第二培养时间;以及
在所述开口中且在所述阻挡层上形成导电填充材料,
其中,所述介电层的侧壁上的所述含碳层包括靠近所述侧壁的第一部分和远离所述侧壁的第二部分,所述第一部分的碳浓度大于所述第二部分的碳浓度,
其中,所述第一部分在使用等离子体进行所述致密化期间减慢或阻止等离子体的穿透。
2.根据权利要求1所述的方法,其中,所述阻挡层在所述介电层的侧壁处具有第一厚度,并且所述阻挡层在所述导电部件的表面处具有第二厚度,所述第一厚度大于所述第二厚度。
3.根据权利要求1所述的方法,其中,所述第一前体气体具有至少25原子百分比的碳浓度。
4.根据权利要求1所述的方法,其中,所述阻挡层包括氮化钽。
5.根据权利要求1所述的方法,其中,形成所述阻挡层还包括:
通过所述开口对所述导电部件的表面实施清洁工艺,实施所述清洁工艺包括使用具有还原气体的等离子体;以及
实施原子层沉积(ALD)工艺以沉积所述含碳层,所述原子层沉积工艺包括至少一个循环,所述至少一个循环包括脉冲调制所述第一前体气体并且脉冲调制反应物气体。
6.根据权利要求1所述的方法,其中,沉积所述含碳层包括实施多个循环,所述多个循环中的每个均包括:
脉冲调制所述第一前体气体;以及
脉冲调制反应物气体。
7.根据权利要求6所述的方法,其中,所述含碳层是整体具有至少15原子百分比的碳浓度的含碳氮化钽层。
8.根据权利要求1所述的方法,其中,沉积所述含碳层包括:
实施多个第一循环;以及
在实施所述多个第一循环之后,实施多个第二循环;
其中,所述多个第一循环中的每个均包括:
脉冲调制所述第一前体气体,而不是第二前体气体,其中,所述第一前体气体具有至少25原子百分比的碳浓度,其中,所述第二前体气体具有小于25原子百分比的碳浓度;和
脉冲调制反应物气体;以及
其中,所述多个第二循环中的每个均包括:
脉冲调制所述第二前体气体,而不是所述第一前体气体;和
脉冲调制所述反应物气体。
9.根据权利要求8所述的方法,其中,所述含碳层包括:
由所述多个第一循环形成的具有至少15原子百分比的碳浓度的第一含碳氮化钽子层;以及
由所述多个第二循环形成的具有小于15原子百分比的碳浓度的第二含碳氮化钽子层。
10.根据权利要求1所述的方法,其中,沉积所述含碳层包括:
实施第一循环;
在实施所述第一循环之后,实施第二循环;以及
在实施所述第二循环之后,实施第三循环;
其中,所述第一循环包括:
脉冲调制所述第一前体气体,而不是第二前体气体,其中,所述第一前体气体具有至少25原子百分比的碳浓度,其中,所述第二前体气体具有小于25原子百分比的碳浓度;和
脉冲调制反应物气体;以及
其中,所述第二循环包括:
脉冲调制包括所述第一前体气体和所述第二前体气体的混合物;和
脉冲调制所述反应物气体;以及
其中,所述第三循环包括:
脉冲调制所述第二前体气体,而不是所述第一前体气体;和
脉冲调制所述反应物气体。
11.根据权利要求10所述的方法,其中,所述含碳层是具有渐变浓度的碳的含碳氮化钽层。
12.一种半导体结构,包括:
第一介电层,位于衬底上方;
第一导电部件,位于所述第一介电层中;
第二介电层,位于所述第一介电层和所述第一导电部件上方;以及
第二导电部件,位于所述第二介电层中并且接触所述第一导电部件;所述第二导电部件包括:
阻挡层,沿着所述第二介电层的侧壁并且位于所述第一导电部件的表面上,所述阻挡层在所述第二介电层的侧壁处具有第一厚度,所述阻挡层在所述第一导电部件的表面处具有第二厚度,所述第一厚度大于所述第二厚度;和
导电填充材料,位于所述阻挡层上,
其中,所述阻挡层包括靠近所述第二介电层的侧壁的第一部分和远离所述第二介电层的侧壁而靠近所述导电填充材料的第二部分,所述第一部分的碳浓度大于所述第二部分的碳浓度,其中,所述第二部分的密度大于所述第一部分的密度。
13.根据权利要求12所述的结构,其中,所述阻挡层包括氮化钽。
14.根据权利要求12所述的结构,其中,所述阻挡层具有在从1原子百分比至5原子百分比的范围内的碳浓度。
15.根据权利要求12所述的结构,其中,所述阻挡层具有从11.0g/cm3至12.0g/cm3的范围内的密度。
16.根据权利要求12所述的结构,其中,所述阻挡层的第一部分具有在从1at.%至5at.%的范围内的碳浓度,并且所述阻挡层的第二部分具有在从1at.%至3at.%范围内的碳浓度。
17.根据权利要求12所述的结构,其中,所述阻挡层包括靠近所述第二介电层的侧壁的第一部分和远离所述第二介电层的侧壁的第二部分,其中:
所述第一部分具有在从1原子百分比至5原子百分比的范围内的碳浓度;
所述第二部分具有在从1原子百分比至3原子百分比的范围内的碳浓度;
所述第一部分的密度在从10.5g/cm3至11.5g/cm3的范围内;以及
所述第二部分的密度在从11.5g/cm3至12.5g/cm3的范围内。
18.一种用于半导体处理的方法,所述方法包括:
形成穿过介电层至导电部件的开口;
在所述开口中沿着所述介电层的侧壁并且在所述导电部件的表面上沉积含碳层,使用原子层沉积(ALD)工艺来沉积所述含碳层,其中,所述介电层的侧壁上的所述含碳层包括靠近所述侧壁的第一部分和远离所述侧壁的第二部分,所述第一部分的碳浓度大于所述第二部分的碳浓度,所述原子层沉积工艺包括至少一个第一循环,至少一个第一循环包括:
脉冲调制具有至少25原子百分比的碳浓度的前体气体;以及
脉冲调制反应物气体;
使所述含碳层致密化包括使所述含碳层暴露于等离子体,其中,在所述致密化之后,所述含碳层是阻挡层,其中,所述第一部分在使用等离子体进行所述致密化期间减慢或阻止等离子体的穿透;以及
在所述开口中且在所述阻挡层上形成导电填充材料。
19.根据权利要求18所述的方法,其中,所述含碳层是含碳氮化钽层。
20.根据权利要求18所述的方法,其中,所述原子层沉积工艺还包括至少一个第二循环,包括:
脉冲调制具有小于25原子百分比的碳浓度的前体气体;以及
脉冲调制所述反应物气体。
CN201811382303.9A 2018-05-31 2018-11-20 用于半导体处理的方法以及半导体结构 Active CN110556334B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/993,751 US10741442B2 (en) 2018-05-31 2018-05-31 Barrier layer formation for conductive feature
US15/993,751 2018-05-31

Publications (2)

Publication Number Publication Date
CN110556334A CN110556334A (zh) 2019-12-10
CN110556334B true CN110556334B (zh) 2022-08-23

Family

ID=68576185

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201811382303.9A Active CN110556334B (zh) 2018-05-31 2018-11-20 用于半导体处理的方法以及半导体结构

Country Status (5)

Country Link
US (3) US10741442B2 (zh)
KR (1) KR102210976B1 (zh)
CN (1) CN110556334B (zh)
DE (1) DE102018113674A1 (zh)
TW (1) TWI698919B (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11769692B2 (en) 2018-10-31 2023-09-26 Taiwan Semiconductor Manufacturing Co., Ltd. High breakdown voltage inter-metal dielectric layer
US11251261B2 (en) * 2019-05-17 2022-02-15 Micron Technology, Inc. Forming a barrier material on an electrode

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010021194A (ko) * 1999-08-18 2001-03-15 포만 제프리 엘 가변적인 조성의 칩 배선용 확산 배리어
CN105765696A (zh) * 2013-12-26 2016-07-13 英特尔公司 直接等离子体致密化工艺以及半导体器件
CN107706189A (zh) * 2017-08-22 2018-02-16 长江存储科技有限责任公司 3d nand闪存的接触窗形成方法和接触窗结构
CN107887326A (zh) * 2016-09-30 2018-04-06 台湾积体电路制造股份有限公司 半导体器件及其制造方法

Family Cites Families (53)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3807008A (en) * 1969-05-02 1974-04-30 Texas Instruments Inc Chemical vapor deposition coatings on titanium
JPH01298765A (ja) * 1988-05-27 1989-12-01 Fujitsu Ltd 半導体装置及びその製造方法
US5968333A (en) * 1998-04-07 1999-10-19 Advanced Micro Devices, Inc. Method of electroplating a copper or copper alloy interconnect
US6169024B1 (en) * 1998-09-30 2001-01-02 Intel Corporation Process to manufacture continuous metal interconnects
US6417094B1 (en) * 1998-12-31 2002-07-09 Newport Fab, Llc Dual-damascene interconnect structures and methods of fabricating same
US6245655B1 (en) * 1999-04-01 2001-06-12 Cvc Products, Inc. Method for planarized deposition of a material
JP3976462B2 (ja) * 2000-01-26 2007-09-19 エルピーダメモリ株式会社 半導体装置の製造方法
US6576543B2 (en) 2001-08-20 2003-06-10 Taiwan Semiconductor Manufacturing Co., Ltd. Method for selectively depositing diffusion barriers
US6551893B1 (en) * 2001-11-27 2003-04-22 Micron Technology, Inc. Atomic layer deposition of capacitor dielectric
US6849173B1 (en) * 2002-06-12 2005-02-01 Taiwan Semiconductor Manufacturing Company, Ltd. Technique to enhance the yield of copper interconnections
US6939800B1 (en) 2002-12-16 2005-09-06 Lsi Logic Corporation Dielectric barrier films for use as copper barrier layers in semiconductor trench and via structures
DE10302644B3 (de) * 2003-01-23 2004-11-25 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung einer Metallschicht über einem strukturierten Dielektrikum mittels stromloser Abscheidung unter Verwendung eines Katalysators
DE10303925B4 (de) * 2003-01-31 2007-06-06 Advanced Micro Devices, Inc., Sunnyvale Dielektrische Barrierenschicht für eine Kupfermetallisierungsschicht mit einer über die Dicke hinweg variierenden Siliziumkonzentration und Verfahren zu deren Herstellung
JP4086673B2 (ja) 2003-02-04 2008-05-14 Necエレクトロニクス株式会社 半導体装置及びその製造方法
US6812110B1 (en) * 2003-05-09 2004-11-02 Micron Technology, Inc. Methods of forming capacitor constructions, and methods of forming constructions comprising dielectric materials
US20050082089A1 (en) * 2003-10-18 2005-04-21 Stephan Grunow Stacked interconnect structure between copper lines of a semiconductor circuit
JP3759525B2 (ja) 2003-10-27 2006-03-29 松下電器産業株式会社 半導体装置の製造方法
US20050206000A1 (en) * 2004-03-19 2005-09-22 Sanjeev Aggarwal Barrier for copper integrated circuits
US7282438B1 (en) 2004-06-15 2007-10-16 Novellus Systems, Inc. Low-k SiC copper diffusion barrier films
US7863179B2 (en) * 2006-10-31 2011-01-04 Lam Research Corporation Methods of fabricating a barrier layer with varying composition for copper metallization
JP4224434B2 (ja) 2004-06-30 2009-02-12 パナソニック株式会社 半導体装置及びその製造方法
US7037837B2 (en) 2004-07-29 2006-05-02 Texas Instruments Incorporated Method of fabricating robust nucleation/seed layers for subsequent deposition/fill of metallization layers
US7476618B2 (en) * 2004-10-26 2009-01-13 Asm Japan K.K. Selective formation of metal layers in an integrated circuit
US8025922B2 (en) * 2005-03-15 2011-09-27 Asm International N.V. Enhanced deposition of noble metals
US20070059502A1 (en) * 2005-05-05 2007-03-15 Applied Materials, Inc. Integrated process for sputter deposition of a conductive barrier layer, especially an alloy of ruthenium and tantalum, underlying copper or copper alloy seed layer
US7550385B2 (en) * 2005-09-30 2009-06-23 Intel Corporation Amine-free deposition of metal-nitride films
US7785658B2 (en) 2005-10-07 2010-08-31 Asm Japan K.K. Method for forming metal wiring structure
JP2007281114A (ja) * 2006-04-05 2007-10-25 Sony Corp 半導体装置の製造方法および半導体装置
US20070259519A1 (en) 2006-05-02 2007-11-08 International Business Machines Corporation Interconnect metallization process with 100% or greater step coverage
US7435484B2 (en) 2006-09-01 2008-10-14 Asm Japan K.K. Ruthenium thin film-formed structure
US8242016B2 (en) * 2007-05-14 2012-08-14 Taiwan Semiconductor Manufacturing Company, Ltd. Approach for reducing copper line resistivity
JP5366235B2 (ja) 2008-01-28 2013-12-11 東京エレクトロン株式会社 半導体装置の製造方法、半導体製造装置及び記憶媒体
US7834457B2 (en) * 2008-02-28 2010-11-16 International Business Machines Corporation Bilayer metal capping layer for interconnect applications
JP5343369B2 (ja) * 2008-03-03 2013-11-13 東京エレクトロン株式会社 半導体装置の製造方法、半導体製造装置及び記憶媒体
US7928569B2 (en) * 2008-08-14 2011-04-19 International Business Machines Corporation Redundant barrier structure for interconnect and wiring applications, design structure and method of manufacture
US7977235B2 (en) * 2009-02-02 2011-07-12 Tokyo Electron Limited Method for manufacturing a semiconductor device with metal-containing cap layers
US8344513B2 (en) * 2009-03-23 2013-01-01 Taiwan Semiconductor Manufacturing Company, Ltd. Barrier for through-silicon via
US8916469B2 (en) * 2013-03-12 2014-12-23 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating copper damascene
TW201532247A (zh) * 2013-10-16 2015-08-16 Conversant Intellectual Property Man Inc 形成嵌入動態隨機存取記憶體電容器的成本效益佳的方法
US9306023B2 (en) * 2014-02-06 2016-04-05 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device with gate stacks and method of manufacturing the same
US10163644B2 (en) 2014-02-07 2018-12-25 Taiwan Semiconductor Manufacturing Company Interconnect structure including a conductive feature and a barrier layer on sidewalls and a bottom surface of the conductive feature and method of forming the same
US9847296B2 (en) * 2014-02-14 2017-12-19 Taiwan Semiconductor Manufacturing Company, Ltd. Barrier layer and structure method
US9123785B1 (en) 2014-03-10 2015-09-01 Intermolecular, Inc. Method to etch Cu/Ta/TaN selectively using dilute aqueous HF/HCI solution
US9966339B2 (en) * 2014-03-14 2018-05-08 Taiwan Semiconductor Manufacturing Company Barrier structure for copper interconnect
JP6268008B2 (ja) * 2014-03-17 2018-01-24 東京エレクトロン株式会社 Cu配線の製造方法
US9224686B1 (en) * 2014-09-10 2015-12-29 International Business Machines Corporation Single damascene interconnect structure
US9553100B2 (en) * 2014-12-04 2017-01-24 Sandisk Techologies Llc Selective floating gate semiconductor material deposition in a three-dimensional memory structure
WO2016099570A1 (en) * 2014-12-19 2016-06-23 Intel Corporation Selective deposition utilizing sacrificial blocking layers for semiconductor devices
JP6583081B2 (ja) * 2016-03-22 2019-10-02 東京エレクトロン株式会社 半導体装置の製造方法
US10580650B2 (en) * 2016-04-12 2020-03-03 Tokyo Electron Limited Method for bottom-up formation of a film in a recessed feature
US9837270B1 (en) 2016-12-16 2017-12-05 Lam Research Corporation Densification of silicon carbide film using remote plasma treatment
US9953927B1 (en) * 2017-04-26 2018-04-24 Globalfoundries Inc. Liner replacements for interconnect openings
JP6902958B2 (ja) * 2017-08-02 2021-07-14 東京エレクトロン株式会社 シリコン膜の形成方法および形成装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010021194A (ko) * 1999-08-18 2001-03-15 포만 제프리 엘 가변적인 조성의 칩 배선용 확산 배리어
CN105765696A (zh) * 2013-12-26 2016-07-13 英特尔公司 直接等离子体致密化工艺以及半导体器件
CN107887326A (zh) * 2016-09-30 2018-04-06 台湾积体电路制造股份有限公司 半导体器件及其制造方法
CN107706189A (zh) * 2017-08-22 2018-02-16 长江存储科技有限责任公司 3d nand闪存的接触窗形成方法和接触窗结构

Also Published As

Publication number Publication date
US10741442B2 (en) 2020-08-11
DE102018113674A1 (de) 2019-12-05
CN110556334A (zh) 2019-12-10
US20200083095A1 (en) 2020-03-12
TW202004866A (zh) 2020-01-16
KR20190136879A (ko) 2019-12-10
KR102210976B1 (ko) 2021-02-03
US20200083096A1 (en) 2020-03-12
TWI698919B (zh) 2020-07-11
US11043413B2 (en) 2021-06-22
US11183424B2 (en) 2021-11-23
US20190371660A1 (en) 2019-12-05

Similar Documents

Publication Publication Date Title
US11587829B2 (en) Doping control of metal nitride films
US20080260963A1 (en) Apparatus and method for pre and post treatment of atomic layer deposition
JP2008532271A (ja) 原子層堆積のための表面のプラズマ前処理
US20060281299A1 (en) Method of fabricating silicon carbide-capped copper damascene interconnect
US20230008675A1 (en) High breakdown voltage etch-stop layer
CN110556334B (zh) 用于半导体处理的方法以及半导体结构
CN113314458A (zh) 半导体器件的扩散阻挡部及方法
US11600521B2 (en) Surface modification layer for conductive feature formation
US10950500B2 (en) Methods and apparatus for filling a feature disposed in a substrate
CN110660729B (zh) 半导体装置的形成方法
TWI732294B (zh) 沉積方法及系統
US11024537B2 (en) Methods and apparatus for hybrid feature metallization
KR100528069B1 (ko) 반도체 소자 및 그 제조 방법
US20040082169A1 (en) Deposition of barrier metal in damascene interconnects using metal carbonyl
US20060040490A1 (en) Method of fabricating silicon carbide-capped copper damascene interconnect
KR100788602B1 (ko) 반도체 소자 및 그 금속 배선 형성 방법
KR102403920B1 (ko) 구리 확산을 저감시키기 위한 비정질층 및 이것을 형성하는 방법
JP2006147895A (ja) 半導体装置の製造方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant