TWI734164B - 半導體裝置及其形成方法 - Google Patents
半導體裝置及其形成方法 Download PDFInfo
- Publication number
- TWI734164B TWI734164B TW108128362A TW108128362A TWI734164B TW I734164 B TWI734164 B TW I734164B TW 108128362 A TW108128362 A TW 108128362A TW 108128362 A TW108128362 A TW 108128362A TW I734164 B TWI734164 B TW I734164B
- Authority
- TW
- Taiwan
- Prior art keywords
- layer
- semiconductor device
- barrier layer
- metal
- oxide layer
- Prior art date
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
- H01L21/67184—Apparatus for manufacturing or treating in a plurality of work-stations characterized by the presence of more than one transfer chamber
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
- H01L21/67207—Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
- H01L21/76888—By rendering at least a portion of the conductor non conductive, e.g. oxidation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/564—Details not otherwise provided for, e.g. protection against moisture
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76855—After-treatment introducing at least one additional element into the layer
- H01L21/76856—After-treatment introducing at least one additional element into the layer by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02123—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body inside the bonding area
- H01L2224/02125—Reinforcing structures
- H01L2224/02126—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05005—Structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0501—Shape
- H01L2224/05016—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0502—Disposition
- H01L2224/05022—Disposition the internal layer being at least partially embedded in the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0502—Disposition
- H01L2224/05026—Disposition the internal layer being disposed in a recess of the surface
- H01L2224/05027—Disposition the internal layer being disposed in a recess of the surface the internal layer extending out of an opening
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05075—Plural internal layers
- H01L2224/0508—Plural internal layers being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05124—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05147—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/05166—Titanium [Ti] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/05181—Tantalum [Ta] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/05184—Tungsten [W] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/05186—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
- H01L2224/05559—Shape in side view non conformal layer on a patterned surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05647—Copper [Cu] as principal constituent
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
一種用於形成結合襯墊結構的方法包括在半導體裝置上形成互連結構,在互連結構上形成鈍化層,經由鈍化層形成至少一個開口,至少在開口中形成氧化層,及在氧化層上形成襯墊金屬層。互連結構之一部分由至少一個開口而曝露。
Description
本揭示涉及一種半導體裝置及一種半導體裝置的形成方法。
一半導體裝置包括一或多個導電金屬層以作為金屬互連。導電金屬層經由介電材料與多個裝置元件彼此耦接。導電金屬層形成於彼此上方且定位於多個裝置高度。此外,半導體裝置包括作為襯墊結構之一部分的最上層或頂部金屬層。因此,頂部金屬層可電耦接焊料凸塊或其他外部元件,以便實現與半導體裝置之電連接。
本揭示的一些實施例提供一種半導體裝置的形成方法,其包括在半導體裝置上形成互連結構;在互連結構上形成鈍化層;形成穿過鈍化層的至少一個開口,其中互連結構的一部分被此開口曝露;至少在開口中形成氧化層;及在氧化層上形成襯墊金屬層。
本揭示的一些實施例提供一種半導體裝置,其包括互連結構、第一鈍化層、氧化層及襯墊金屬層。互連結構具有導電部分。第一鈍化層位於導電部分上,且其內具有開口。氧化層位於導電部分的一部分上方,且至少位於第一
鈍化層的開口中。襯墊金屬層直接位於氧化層上,且電連接至導電部分。
本揭示的一些實施例提供一種半導體裝置,其包括互連結構、阻障層、氧化層及襯墊金屬層。互連結構具有導電部分。阻障層電連接至導電部分。氧化層在阻障層上。襯墊金屬層在氧化層上。
10:晶圓處理設備
12:FOUP
14:裝載埠
16:負載鎖定腔室
18:移送腔室
19:移送機器人
20:處理腔室
22:處理腔室
24:通過腔室
26:移送腔室
27:移送機器人
28:處理腔室
30:處理腔室
32:處理腔室
34:通過腔室
100:半導體裝置
102:基板
103:電晶體
1040:介電層
1040-104N:介電層
1041:介電層
1042:介電層
104N:介電層
105:導電插頭
1061:蝕刻停止層
1061-106N:蝕刻停止層
1062:蝕刻停止層
106N:蝕刻停止層
108:淺溝槽隔離
110:互連結構
1121:導電部分
1121-112N:導電部分
1122:導電部分
112N:導電部分
1141:導線
1141-114N:導線
1142:導線
114N:導線
1161:導電通孔
1161-116N:導電通孔
1162:導電通孔
116N:導電通孔
120:結合襯墊結構
130:第一鈍化層
140:阻障層
150:氧化層
160:襯墊金屬層
170:第二鈍化層
212N:導電部分
220:結合襯墊結構
230:第一鈍化層
240:阻障層
250:氧化層
260:襯墊金屬層
270:第二鈍化層
312N:導電部分
320:結合襯墊結構
330:第一鈍化層
340:阻障層
350:氧化層
360:襯墊金屬層
370:第二鈍化層
1032:閘極結構
1034:源極/汲極區域
1036:通道區域
1042:凹槽
1301:開口
1302:第一層
1304:第二層
1402:頂表面
1404:頂表面
1502:頂表面
1702:第一層
1704:第二層
3402:第一層
3404:第二層
3406:第三層
M1:方法
M2:方法
S10:操作
S20:操作
S30:操作
S32:操作
S34:操作
S40:操作
S50:操作
S60:操作
S70:操作
本揭示案之態樣在結合附圖閱讀時從以下詳細說明中得以最佳地理解。應注意,依據行業中之標準慣例,各種特徵並非按比例繪製。事實上,為了論述明晰,各種特徵之尺寸可任意增大或減小。
第1圖係繪示依據本揭示案之一些實施例之具有結合襯墊結構的半導體裝置之示意圖。
第2圖係繪示依據本揭示案之一些實施例之用於形成半導體裝置的結合襯墊結構的方法的流程圖。
第3-11圖係繪示根據第2圖之方法之製造結合襯墊結構的多個階段的橫截面的示意圖。
第12圖係繪示依據本揭示案之一些其他實施例之結合襯墊結構的示意圖。
第13圖係繪示依據本揭示案之又一實施例之結合襯墊結構的示意圖。
第14圖係繪示依據本揭示案之一些實施例之晶圓處理設備的示意圖。
第15圖係繪示依據本揭示案之一些其他實施例的形成半導體裝置之結合襯墊結構的方法的流程圖。
以下揭示案提供眾多不同實施例或實例以用於實施本案提供標的之不同特徵。下文描述元件及佈置之特定實例以簡化本揭示案之一些實施例。當然,此僅係實例,並非意欲限制。例如,下文描述中第一特徵於第二特徵上方或之上的形成可包括第一特徵與第二特徵直接接觸而形成的實施例;及亦可包括第一特徵與第二特徵之間可能形成額外特徵,以使得第一特徵與第二特徵可不直接接觸的實施例。此外,本揭示案之一些實施例可在各種實例中重複元件符號及/或字母。此重複係以簡單與明晰為目的,且其自身不規定本文論述之各種實施例及/或配置之間的關係。
而且,本案可能使用諸如「在...之下」、「在...下方」、「下部」、「在...之上」、「上部」等等空間相對術語以便於描述,以描述一個元件或特徵與另一(或更多個)元件或特徵的關係,如圖式中所示。除圖式中繪示之定向之外,空間相對術語意欲包括元件在使用或操作中的不同定向。設備可能以其他方式定向(旋轉90度或以其他定向),且本案所使用之空間相對描述詞可由此進行同樣理解。
如本文中所使用,「大約」、「約」、「大體上」或「近似」一般應意謂與給定值或範圍相差在20%內、10%內,或5%內。本文給定的數值量係近似的,即意謂在
無明確表述之情況下可推論術語「大約」、「約」、「大體上」或「近似」。
半導體裝置中之結合襯墊結構可包括複數個層,以共同實現與半導體裝置的電連接。然而,結合襯墊結構製造期間的濕氣及/或污染可觸發晶鬚缺陷問題,此問題危害半導體裝置之效能。此外,結合襯墊結構中內應力的局部化可為晶鬚缺陷問題的另一原因。晶鬚缺陷問題是結合襯墊結構的金屬表面上可出現晶鬚狀突出物,從而導致對半導體裝置之短路及/或其他損壞之現象。此外,晶鬚缺陷問題亦可由於結合襯墊結構中存在的壓縮應力而產生。因此,為竭力妥當解決上文提及之問題,依據本揭示案如下所述的多個實施例介紹了一種半導體裝置及形成此半導體裝置之方法。
參看第1圖,第1圖係繪示依據本揭示案之一些實施例之半導體裝置100的示意圖,此半導體裝置具有結合襯墊結構120。在一些實施例中,半導體裝置100可包括被動元件(例如,電阻器、電容器、感應器及保險絲)、主動元件(例如,P-通道場效電晶體(P-channel field effect transistor;PFET)、N-通道場效電晶體(N-channel field effect transistor;NFET)、金屬氧化物半導體場效電晶體(metal-oxide-semiconductor field effect transistor;MOSFET)、互補金屬氧化物半導體(complementary metal-oxide-semiconductor;CMOS)電晶體、高電壓電晶體及高頻電晶體)、其他適合的元件,及/或上述各者之
組合。應注意,熟習本領域技術者可理解,上文提及之實例僅提供用於說明之目的,且並非意謂以任何方式限制本揭示案之一些實施例。其他的電路系統亦可基於各種設計而包含在半導體裝置100中。
如第1圖所示,半導體裝置100具有基板102。在一些實施例中,基板102可由矽、鍺適合之第III-V族化合物材料(例如,砷化鍺(GaA))、上述各者之組合等形成。在一些實施例中,基板102可包括絕緣體上矽(silicon on insulator;SOI)結構。詳細而言,SOI結構可具有形成於絕緣體層上之諸如矽之半導體材料層。絕緣體層可包括埋入式氧化物(buried oxide;BOX)層及/或氧化矽層。應注意,基板102可包括:諸如鍺之另一元素半導體;化合物半導體,包括碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及銻化銦;合金半導體,包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及GaInAsP,或上述各者之組合。此外,亦可採用其他類型之基板,如多層基板、梯度基板,或上述各者之組合。
在一些實施例中,如電晶體103之主動元件形成於基板102上。電晶體包括閘極結構1032、源極/汲極區域1034,及通道區域1036以放大或切換電子信號及電功率。在一些實施例中,淺溝槽隔離(shallow trench isolation;STI)108鄰近於電晶體103以阻止電晶體103與鄰近元件之間的電流洩漏。在一些實施例中,介電層1040經配置以作為間金屬層圍繞電晶體103,且可包括氧化物材
料、極低介電常數介電質(extreme low k dielectric;ELK)、絕緣材料、上述各者之組合等。在一些實施例中,蝕刻停止層1061經配置在介電層1040上,且可包括碳化矽(silicon carbide;SiC)或其他適合的材料。SiC是可在高溫下及/或高電壓下穩定操作之材料,且因此適合於應用至半導體裝置100。
在一些實施例中,半導體裝置100之互連結構110可包括複數個介電層1040、1041、1042……104N(1040-104N)、蝕刻停止層1061、1062……106N(1061-106N)、導電部分1121、1122……112N(1121-112N)、導線1141、1142……114N(1141-114N),及導電通孔1161、1162……116N(1161-116N)。導電部分1121-112N、導線1141-114N,及/或導電通孔1161-116N可經由介電層1040-104N及/或蝕刻停止層1061-106N路由,以在電晶體103與外部電子構件之間形成連接。例如,如第1圖所示,介電層1040、蝕刻停止層1061、介電層1041、蝕刻停止層1062、介電層1042、蝕刻停止層106N,及介電層104N以自下而上之序列經排列及堆疊。導電插頭105經由介電層1040及/或蝕刻停止層1061路由以形成導電部分1121與閘極結構1032之間及/或導線1141與源極/汲極區域1034之間的連接。導電部分1121及導線1141可耦接至彼此。導電通孔1162可橋接導線1141與導線1142。如上文提及之類似結構配置亦可應用於導線1142、導電通孔116N、導線114N、導電部分1122,及導電部分112N。在一些實施例中,
導電插頭105、導線1141-114N,及導電通孔1161-116N亦可沿非線性路徑排列,以在電晶體103與結合襯墊結構120之間形成連接。在一些實施例中,導電插頭105、導線1141-114N、導電通孔1161-116N及導電部分1121-112N可包括基於金屬之材料,例如銅(Cu),此等材料具有優良導電特性。
在一些實施例中,互連結構110可藉由鑲嵌製程、雙鑲嵌製程、上述兩者之組合或類似者而形成。例如,溝槽蝕刻製程可經執行以形成複數個溝槽。隨後,類似於銅之金屬材料可提供在溝槽中作為電傳輸介質。因此,互連結構110可形成為半導體裝置100中積體電路之一部分。
在一些實施例中,第一鈍化層130定位於互連結構110上。第一鈍化層130可包括氧化物、氮化物、未摻雜矽玻璃(undoped silicate glass;USG)、上述各者之組合等。在一些實施例中,第二鈍化層170定位於第一鈍化層130上。第二鈍化層170可包括氧化物、氮化物、未摻雜矽玻璃(undoped silicate glass;USG)、上述各者之組合等。第一鈍化層130及/或第二鈍化層170經配置以保護下層元件免受外界環境之腐蝕、刮劃,及/或損害。在一些實施例中,第一鈍化層130可包括多層結構,如第一層1302及第二層1304。例如,第一層1302可包括氮化矽(silicon nitride;SiN)及第二層1304可包括未摻雜矽玻璃(undoped silicate glass;USG)。在一些實施例中,第二鈍化層170可包括多層結構,如第一層1702及第二層
1704。例如,第一層1702可包括未摻雜矽玻璃(undoped silicate glass;USG)及第二層1704可包括氮化矽(silicon nitride;SiN)。應注意,第一鈍化層130及第二鈍化層170之結構配置是實例,且並非意欲限制。
在一些實施例中,結合襯墊結構120經由第一鈍化層130及第二鈍化層170而配置,以使得半導體裝置100可經由結合襯墊結構120結合並連接至外部電子構件。更特定而言,結合襯墊結構120(藉由矩形虛線強調)可為堆疊結構,此結構包括導電部分112N、第一鈍化層130、阻障層140、氧化層150、襯墊金屬層160,及第二鈍化層170。由於氧化層150可分隔阻障層140與襯墊金屬層160,因此可阻隔並防止由阻障層140產生的污染及/或濕氣在襯墊金屬層160上產生負面影響,諸如在金屬層160上產生晶鬚缺陷。應注意,結合襯墊結構120中的上文提及之元件的結構配置可基於各種設計而調整。此外,下文將介紹關於結合襯墊結構120之更詳細的描述。
參看第2圖,第2圖係繪示依據本揭示案之一些實施例之用於形成結合襯墊結構120的方法M1的流程圖。更特定而言,第2圖繪示用於製造半導體裝置100中所含的結合襯墊結構120的一示例性實施例。方法M1可包括半導體裝置100之製造製程中之相應部分。應注意,下文介紹的每一方法僅為實例,且並非意欲限制本揭示案之一些實施例中超出專利申請範圍中明確所述範圍以外的內容。可在每一方法之前、期間及之後提供額外操作。描述的一些操作可在
額外的製造製程實施例中被替換、消除,或移動。此外,為了明晰且易於解釋,圖式之一些元件已簡化。
第3圖至第10圖係繪示根據第2圖之方法M1製造半導體裝置100中之結合襯墊結構120的多個階段的橫截面示意圖。更特定而言,下文將結合第3圖至第11圖中繪示的橫截面,引述第2圖中之操作S10至S70,以便共同描述製造細節及結合襯墊結構120之結構。
參看第3圖。提供介電層104N。更特定而言,介電層104N是結合襯墊結構120之中間結構。應注意,為了明晰且易於解釋本揭示案之一些實施例,半導體裝置100之一部分被特別地繪示。
在一些實施例中,結合襯墊結構120之介電層104N可包括整塊矽、摻雜矽、未摻雜矽、介電材料、其他適合的元素,或上述各者之組合。此外,結合襯墊結構120之介電層104N可為金屬間介電(inter-metal dielectric;IMD)層。在一些實施例中,IMD層可由磷矽酸鹽玻璃(phosphosilicate glass;PSG)、硼磷矽酸鹽玻璃(borophosphosilicate glass;BPSG)、氟矽酸鹽玻璃(fluorosilicate glass;FSG)、SiOxCy、旋塗玻璃、旋塗聚合物、矽碳材料、低介電常數介電材料、上述各者之化合物、上述各者之合成物、上述各者之組合等經由任何適合方法(例如旋塗塗佈、化學氣相沉積(chemical vapor deposition;CVD)、電漿增強CVD(plasma-enhanced CVD;PECVD)、上述各者之組合等)而製成。
參看第4圖。凹槽1042(或溝槽)形成於介電層104N中。凹槽1042可藉由任何適合的蝕刻製程而形成,如濕式蝕刻、乾式蝕刻、上述各者之組合等。在一些實施例中,氫氧化四甲銨(TMAH)用於各向異性濕式蝕刻製程。在一些實施例中,乾式蝕刻製程係藉由蝕刻氣體而實施,此蝕刻氣體包含O2、Cl2、HBr、He、NF3、CO2、CxHyFx、Ar、N2、H2、上述各者之組合等。在一些實施例中,凹槽1042具有傾斜側壁。在一些實施例中,介電層104N之凹槽1042可藉由任何適合的製程而形成,如鑲嵌製程、雙鑲嵌製程、上述各者之組合等,以便基於各種設計而形成具有所欲形狀之溝槽。在一些實施例中,另一凹槽(第4圖中未繪示)形成於介電層104N中以用於形成導線114N。亦即,凹槽1042及用於形成導線114N之凹槽可在同一蝕刻製程中形成。
參看第5圖。互連結構110之導電部分112N形成於凹槽1042中。根據上文針對第1圖提及的描述,導電部分112N可經由介電層104N路由以連接導線114N,以使得互連結構110之導電部分112N、導線114N,及導電通孔116N可成為外部電子構件與半導體裝置100中之如電晶體103之元件之間的電連接的一部分。導電材料112N可包括導電材料,如銅、鋁、鎢、上述各者之組合等。在一些實施例中,互連結構110之導電部分112N可藉由任何適合的製程而形成,如鑲嵌製程、雙鑲嵌製程、上述各者之組合等,以便利
用導電材料填充凹槽1042。在一些實施例中,導線114N可隨著導電部分112N而形成。
在一些實施例中,半導體裝置100之導電部分112N(及導線114N)可進一步在導電部分112N與介電層104N之間包括一或更多個阻障層或黏附層,以便防止由於從導電部分112N至介電層104N中之金屬擴散而發生金屬污染。此外,阻障層或黏附層可包括鈦、氮化鈦、鉭、氮化鉭、上述各者之組合等,且可藉由使用化學氣相沉積(chemical vapor deposition;CVD)、物理氣相沉積(physical vapor deposition;PVD)、原子層沉積(atomic layer deposition;ALD),及上述各者之組合等而形成。
在一些實施例中,導電部分112N(及導線114N)可藉由於第4圖之結構上方沉積導電材料而形成,此導電材料可填充凹槽1042(及用於形成導線114N的凹槽)且亦可覆蓋介電層104N。隨後,可實施平坦化操作以利用介電層104N之頂表面來平坦化導電材料之頂表面,以形成導電部分112N(及導線114N)。而且,平坦化操作可包括使用化學機械研磨(chemical mechanical polishing;CMP)製程。因此,如第5圖所示,導電部分112N之頂表面可與介電層104N之頂表面共面。
應注意,方法M1可始於操作S10,此操作包括在半導體裝置100之基板102上形成互連結構110。另外,執行結合襯墊結構120的製造製程,如第3圖至第5圖中所繪
示,以使得互連結構110之導電部分112N可作為中間結構形成於介電層104N中,且被介電層104N曝露。
參看第6圖。方法M1可繼續進行操作S20,此操作包括在互連結構110上形成第一鈍化層130。更特定而言,第一鈍化層130形成於導電部分112N及介電層104N上。第一鈍化層130可包括氧化物、氮化物、介電材料、上述各者之組合等。第一鈍化層130可具有硬質非反應性特性,此特性保護下層元件免受外界環境之腐蝕、刮劃,及/或損害。
在一些實施例中,如第1圖中所示,第一鈍化層130可包括多層結構,如第一層1302及第二層1304,如第1圖所示。例如,第一層1302可包括氮化矽(SiN),而第二層1304可包括未摻雜矽酸鹽玻璃(undoped silicate glass;USG),反之亦然。多層結構可經由不同的沉積製程、其他適合的製程等逐層形成。因此,第一鈍化層130的配置可基於各種設計而調整,例如第一鈍化層130之材料可基於此鈍化層下方的元件材料而選擇,以使得此鈍化層的保護效果可得以改良。
參看第7圖。方法M1可繼續進行操作S30,此操作包括在形成穿過第一鈍化層130的至少一個開口1301。更特定而言,第一鈍化層130可經圖案化及/或蝕刻以在此鈍化層中形成開口1301,以使得開口1301可曝露導電部分112N之頂表面的一部分。在一些實施例中,可選擇性實施至少一個蝕刻製程,如濕式蝕刻、光化學蝕刻、乾式
蝕刻、電漿蝕刻,或上述各者之組合,以產生具有定向或各向異性結構的開口1301。例如,如第7圖所示,開口1301具有彎曲及/或向下收斂之側壁。在一些實施例中,開口1301可對準導電部分112N之頂表面的中心,以使得結合襯墊結構120可經配置以對稱於導電部分112N之頂表面的法線。在一些其他實施例中,開口1301可不對準導電部分112N之頂表面的中心。只要開口1301曝露導電部分112N,則實施例即符合本揭示案之一些實施例範疇。應注意,開口1301可作為接觸開口、通孔等。
參看第8圖。方法M1可繼續進行操作S40,此操作包括經由開口1301在互連結構110的導電部分112N上沉積阻障層140。更特定而言,阻障層140係沉積在第7圖之結構上方,且特定而言,阻障層140經由開口1301沉積在導電部分112N的一部分上。在一些實施例中,阻障層140可包括基於鉭(Ta)之材料,如鉭、氮化鉭(TaN)、上述各者之組合等。在一些實施例中,阻障層140可藉由至少一個沉積製程而形成,該製程諸如物理氣相沉積(physical vapor deposition;PVD)、原子層沉積、化學氣相沉積、電漿增強原子層沉積、分子束磊晶、離子束輔助沉積、上述各者之組合等。如第8圖所示,阻障層140可具有厚度h1且可覆蓋導電部分112N及第一鈍化層130,以密封曝露的導電部分112N。因此,阻障層140可保護導電部分112N免遭外界損害,及/或防止導電部分112N與隨後將形成於其上的任何元件之間發生相互擴散。
參看第9圖。方法M1可繼續進行操作S50,此操作包括氧化阻障層140之頂表面1402,如第8圖所示,以在阻障層140上形成氧化層150。更特定而言,如第9圖所示,氧化層150藉由使用至少一個氧化製程而立即形成於阻障層140之頂表面1404上方。在一些實施例中,氧化層150可包括金屬氧化物。氧化層150及阻障層140包括同一金屬。若阻障層140由氮化鉭製成,則氧化層150可包括基於鉭(Ta)之材料、TaxOy、上述各者之組合等。在一些實施例中,氧化層150可能不含氮。或者,氧化層150之氮濃度低於氧化層150之氧濃度。此外,因為基於鉭之材料可包括其內具有細小間隔或孔的多孔結構,因此氧化層150可捕獲由阻障層140產生的濕氣及/或污染,且亦防止結合襯墊結構120中之內應力的局部化。因此,結合襯墊結構120之可能的晶鬚缺陷問題可得以減緩。
在一些實施例中,氧化製程包含將阻障層140之頂表面1402曝露於氧化劑氣體達一時段。此外,可提供氧化劑氣體以覆蓋及氧化阻障層140之頂表面1402。氧化劑氣體可包括氮氣及氧氣。氮氣大體上為惰性,以使得可防止氮與阻障層140之間相互作用。經由調整氮與氧之流量比,可適當控制阻障層140之氧化以形成具有所欲結構及/或特性之氧化層150。在一些實施例中,提供至阻障層140的氮氣與氧氣之流量比範圍可在約1/1000與約1000/1之間。例如,當氮流率為約1標準立方釐米每分鐘(sccm)時,氧流率將為約1000sccm,反之亦然。若氧化製程流量比超出上文
提及之範圍,則氧化層150可能產生非所欲結構及/或特性,且該非所欲結構及/或特性不利地影響半導體裝置100的效能。
另一方面,在一些實施例中,氧化製程時段之範圍可在約10秒與約600秒之間。若時段大於約600秒,則氧化層150將過於厚,且不利地影響電傳輸。換言之,結合襯墊結構120之接觸電阻可能增大。相反,若時段小於約10秒,則氧化層150將過於薄,而無法提供足夠結構強度及/或不足以抵禦晶鬚缺陷問題。
此外,在一些實施例中,可在約25℃(或室溫)與約100℃之間的範圍的溫度下實施氧化製程。若溫度高於約100℃,則氧化層150之接觸電阻可能增大。相反,若溫度低於約25℃,則氧化層150可能產生非所欲結構,且該結構不利地影響半導體裝置100的效能。
因此,氧化層150的厚度h3可基於各種設計而可控,例如在約1Å(埃)與約500Å的範圍中。若厚度h3大於500Å,氧化層150將過於厚,且不利地影響電傳輸。相反,若厚度h3小於約1Å,則氧化層150將過於薄,而無法提供足夠結構強度及/或不足以抵禦晶鬚缺陷問題。
在一些實施例中,由於審慎且可控的氧化製程,氧化層150的厚度可基於各種設計而調整。更特定言之,氧化製程可將阻障層140的頂部轉化為氧化層150。亦即,氧化層150之形成可涉及消耗阻障層140之一部分。此外,在氧化製程期間,針對第8圖中之阻障層140,阻障層140
的頂部可從其頂表面1402向下轉化,而氧化層150的一部分可從其頂表面1402向上形成。換言之,氧化層150可從阻障層140的頂表面1402起形成,如第8圖中所示。
例如,第8圖中的阻障層140的厚度可標記為h1,第9圖中的阻障層140的厚度可標記為h2,且第9圖中的氧化層150的厚度可標記為h3。當氧化製程可從阻障層140的頂表面1402起消耗阻障層140時,厚度h1將大於厚度h2。由於阻障層140的消耗,第8圖中之阻障層140的頂表面1402可向下轉化至第9圖中之阻障層140的頂表面1404。此外,當氧化層150的一部分可從阻障層140的頂表面1402起向上形成時,厚度h2及厚度h3之和將大於厚度h1。此外,在一些實施例中,厚度h3可小於厚度h2。
依據上文提及的關於阻障層140及氧化層150的描述,應理解氧化層150可從阻障層140的頂部直接轉化,且亦可同時從阻障層140的頂表面1402形成。因此,氧化層150可與阻障層140共形,例如,氧化層150的頂表面1502可共形於阻障層140的頂表面1404。
另一方面,因為氧化層150係藉由氧化阻障層140的頂部而形成,氧化層150成分可大體上與阻障層140相同。在一些實施例中,氧化層150的鉭基材料可大體上與阻障層140相同。此外,由於氧化劑氣體連續提供達一時段,正在生長的氧化層150的頂部可比其底部曝露於更多氧化劑氣體,以使得氧化層150的氧濃度可在離開阻障層140的氧化層150的側面上達到峰值,亦即,在鄰近於襯墊金屬
層160的氧化層150側面,此襯墊金屬層隨後形成於氧化層150上。亦即,氧化層150的氧濃度可向下降低。應注意,上文提及的濃度是定義為混合物(例如,氧化層150)中一組分(例如,氧)的實體數值除以混合物體積所得的數值濃度。
參看第10圖。方法M1可繼續進行操作S60,此操作包括在氧化層150上形成襯墊金屬層160。更特定言之,襯墊金屬層160可包括鋁(Al)基材料、銅(Cu)基材料、上述各者之組合物等,以便實現向半導體裝置100之電連接。在一些實施例中,襯墊金屬層160可藉由上文提及的沉積製程中至少一者而形成。由於如上所述阻障層140及氧化層150的配置,導電部分112N與襯墊金屬層160之間的相互擴散可被阻止。另一方面,如上文所論述,氧化層150可具有多孔結構以包含由阻障層140產生的濕氣及/或污染。此外,多孔結構亦可充當緩衝物以減輕阻障層140及襯墊金屬層160之間內應力的局部化。因此,襯墊金屬層160上之可能的晶鬚缺陷問題可減輕。
在一些實施例中,在襯墊金屬層160形成之後,可實施至少一個蝕刻製程以圖案化阻障層140、氧化層150,及襯墊金屬層160。在一些實施例中,第一鈍化層130亦可經蝕刻。經由至少一個蝕刻製程,可實現針對結合襯墊結構120的所欲結構配置。
參看第11圖。方法M1可繼續進行操作S70,此操作包括在襯墊金屬層160及第一鈍化層130上形成第二鈍
化層170。更特定言之,第二鈍化層170可形成於第一鈍化層130、阻障層140、氧化層150,及襯墊金屬層160上。例如,第二鈍化層170可藉由上文提及的沉積製程中至少一者而形成。第二鈍化層170可包括氧化物、氮化物、介電材料,上述各者之組合等。因此,第二鈍化層170可保護下層元件免受外界環境的腐蝕、刮劃,及/或損壞。
在一些實施例中,第二鈍化層170可包括多層結構,如第一層1702及第二層1704,如第1圖所示。例如,第一層1702可包括未摻雜矽酸鹽玻璃(undoped silicate glass;USG)及第二層1704可包括氮化矽(SiN)。多層結構可經由不同沉積製程、其他適合的製程等逐層形成。因此,第二鈍化層170的保護效果可增大。
在一些實施例中,可隨後對第11圖中的結構實施化學機械研磨(chemical mechanical polishing;CMP)製程,以使得襯墊金屬層160可曝露,如第1圖中所示,且預備好進行外部電子構件的結合及/或接觸。此外,根據不同結合及/或接觸條件,可對第1圖中結構實施類似於蝕刻製程的額外製程,以便可隨後在襯墊金屬層160上實現所欲形狀,例如溝槽,以提升結合及/或接觸。
在一些實施例中,覆蓋層可進一步形成於曝露的襯墊金屬層160上,以提供平滑表面以用於外部電子構件的結合及/或接觸。在一些實施例中,覆蓋層可包括具有優良導電特性的金屬材料,如純鋁、鋁基合金、任何適合的金屬材料,及上述各者之組合。應注意,鋁基合金可為純鋁與
以下金屬材料中至少一者的組合,如:鈀(Pd)、鎳(Ni)、金(Au)、鉑(Pt)、釕(Ru)、銠(Rh)、銥(Ir)、鈰(Ce)及鉬(Mo)。
參看第12圖,其繪示依據本揭示案之一些其他實施例的結合襯墊結構220的示意圖。由於第12圖的一些元件類似於第11圖的彼等相應元件,下文將不再重複彼等類似元件的描述。如第12圖中所示,導電部分212N形成有矩形橫截面。第一鈍化層230具有垂直側壁,此等側壁之間形成有開口。類似地,阻障層240、氧化層250、襯墊金屬層260,及第二鈍化層270可基於各種設計,藉由上述任何適合的製程依序形成於導電部分212N及第一鈍化層230上。
參看第13圖,其繪示依據本揭示案之又一實施例的結合襯墊結構320的示意圖。由於第13圖的一些元件類似於第12圖的彼等相應元件,下文將不再重複彼等類似元件的描述。類似地,阻障層340、氧化層350、襯墊金屬層360,及第二鈍化層370可基於各種設計,藉由上述任何適合的製程依序形成於導電部分312N及第一鈍化層330上。在一些實施例中,當襯墊金屬層360及其上層元件被圖案化時,第一鈍化層330未經蝕刻,以使得其頂表面可具有均勻高度。
在一些實施例中,阻障層340可包括多層結構。如第13圖所示,阻障層340可包括三個相應的層。而且,第一層3402、第二層3404,及第三層3406可以自下而上的順序排列。阻障層340之多層結構之每一層可分別藉由上文
提及的沉積製程中之至少一個製程形成。在一些實施例中,第一層3402可為金屬層(例如,鉭層),第二層3404可為金屬氮化物層(例如,氮化鉭層),且第三層3406可為金屬氮化物層(例如,氮化鉭層)。
另外地,第一層3402的厚度可標記為T1,第二層3404的厚度可標記為T2,且第三層3406的厚度可標記為T3。在一些實施例中,厚度T3大於厚度T2。在一些實施例中,厚度T2大於厚度T1。應注意,多層結構中每一層的厚度可基於各種設計而藉由調整沉積製程的沉積參數來控制。例如,第二層3404可藉由範圍在約400瓦與約600瓦(例如,500瓦)之間的沉積功率而形成,以使得第二層之厚度T2的範圍可介於約50Å與約70Å之間(例如,60Å)。又例如,第三層3406可藉由範圍在約5000瓦與約7000瓦(例如,6000瓦)之間的沉積功率而形成,以使得第三層之厚度T3的範圍可介於約500Å與約700Å之間(例如,600Å)。因此,第二層3404可充當緩衝層以保護下層元件及/或結構在其他元件(例如,第三層3406)形成於其上期間免受腐蝕、刮劃,及/或損害。
在一些實施例中,當第二層3404及第三層3406皆由氮化鉭製成時,第二層及第三層之至少一者可進一步包括其他類似於金屬之材料,此等材料將配備不同特性以用於應對一些特定條件。在一些實施例中,阻障層340可包括金屬氮化物及/或金屬,而不含氧化物。因此,由於多層結構的配置,阻障層340之保護效果可進一步增強。
另外地,氧化層350可藉由氧化阻障層340之第三層3406而形成。因此,氧化層350及第三層3406可包括相同金屬。氧化層350的厚度可標記為T4,且具有厚度T1、T2、T3及T4之中的最小值。
參看第14圖,其繪示依據本揭示案之一些實施例的晶圓處理設備10的示意圖。在一些實施例中,可在晶圓處理設備10中實施第2圖之操作S40、S50,及/或S60。更特定而言,晶圓處理設備10可包括複數個前開式晶圓傳送盒(front opening unified pod;FOUP)12、裝載埠14、負載鎖定腔室16、複數個處理腔室20、22、28、30、32、通過腔室24、34、移送腔室18、26、移送機器人19、27,以及其他元件,如電源及真空泵。晶圓處理設備10之特徵細節將描述於下。
在一些實施例中,每一前開式晶圓傳送盒(front opening unified pod;FOUP)12中可包含複數個晶圓。FOUP 12可在半導體製造設備(fabrication plant;FAB)中傳送。當FOUP被傳送至FAB中之晶圓處理設備10中時,FOUP可被裝載及連接至裝載埠14。裝載埠14連接至負載鎖定腔室16。負載鎖定腔室16連接至移送腔室18。通過腔室24、34分別連接在移送腔室18、26之間。處理腔室20、22可連接至移送腔室18。處理腔室28、30、32可連接至移送腔室26。移送腔室18、26分別配備移送機器人19、27以在前述的晶圓處理設備10的元件之間傳送晶圓。
在一些實施例中,處理腔室20、22、28、30、32用以分別實施各種半導體製造程序。例如,處理腔室20可為脫氣腔室,處理腔室22可為預清潔腔室,處理腔室28、32可為沉積腔室,且處理腔室30可為氧化腔室。此外,如第14圖所示的無符號的處理腔室可為前述腔室的備用腔室,或基於各種設計而被分配以實施額外的半導體製造程序,例如快速熱製程(rapid thermal process;RTP)、化學氣相沉積(chemical vapor deposition;CVD)、物理氣相沉積(physical vapor deposition;PVD),及離子化金屬電漿(ionized metal plasma;IMP)製程。在一些實施例中,通過腔室24、34亦可用以在半導體製造程序之間冷卻晶圓。
參看第15圖,其繪示依據本揭示案之一些實施例之用於形成半導體裝置100之結合襯墊結構120的方法M2的流程圖。由於如第2圖中所示的方法M1之一些操作類似於如第14圖中所示之方法M2的對應操作,下文將不再重複彼等類似操作的描述。出於說明的目的,參考如第14圖中所示的晶圓處理設備10來共同描述方法M2的細節,如下所述。
在一些實施例中,對半導體基板依序執行操作S10-S30,以使得可提供具有如第7圖中所示的結構的未完工半導體裝置。未完工的半導體裝置可依序包含在FOUP 12中,運送至晶圓處理設備10,在裝載埠14卸載,並移送至負載鎖定腔室16內以準備執行以下製造程序。例如,真
空泵可將負載鎖定腔室16抽真空以防止外界污染進入晶圓處理設備10。
在一些實施例中,操作S32包括使未完工的半導體裝置脫氣。更特定而言,移送機器人19可將未完工的半導體裝置(在此情況下是第7圖中之晶圓)從負載鎖定腔室16移至處理腔室20以用於實施脫氣製程。在脫氣製程期間,晶圓可經加熱以活化晶圓上的剩餘雜質。隨後,可應用真空泵以將活化雜質排出至外界。在一些實施例中,如氫氣(H2)等反應性氣體可進一步被提供至晶圓,以移除及/或防止非所欲氧化層在晶圓上之形成。在一些實施例中,脫氣製程係針對具有或沒有第一鈍化層130的導電部分112N。
在一些實施例中,操作S34包括預清潔未完工的半導體裝置。更特定而言,在脫氣製程之後,移送機器人19可將晶圓從處理腔室20移至處理腔室22,以用於實施預清潔製程。執行預清潔製程以移除晶圓上非所欲的層、材料,及物件。在一些實施例中,預清潔製程可包括濺射蝕刻製程、遠端電漿清潔(remote plasma cleaning;RPC)製程、上述各者之組合等。在一些實施例中,預清潔製程係針對具有或沒有第一鈍化層130的導電部分112N。
在一些實施例中,在預清潔製程之後,晶圓可從處理腔室22逐一移至通過腔室24、移送腔室26,及處理腔室28。隨後,如上文所論述的多種阻障層可形成於處理腔室28中,經由操作S40。
在一些實施例中,可在處理腔室28中原位執行操作S50,亦即氧化製程,以在阻障層上形成氧化層。在形成阻障層之後,向處理腔室28提供氧源。在一些其他實施例中,在處理腔室28、30中分別實施操作S40、S50。詳細而言,晶圓可在真空條件下從處理腔室28中移至處理腔室30。隨後,可在處理腔室30中執行操作S50。
在一些實施例中,在氧化製程之後,操作S60可在處理腔室32中執行以在氧化層上形成襯墊金屬層。此外,晶圓可逐一移動至移送腔室26、通過腔室34、移送腔室18、負載鎖定腔室16、裝載埠14,及FOUP 12。因此,操作S60、S70及其他適合製程可經執行以形成多種結合襯墊結構,如上文所論述。
基於上文提及之描述,本揭示案之一些實施例可提供各種優勢。詳細而言,結合襯墊結構之阻障層可經歷氧化製程以從阻障層之頂表面形成氧化層。此外,氧化製程可經操縱以提供基於各種設計而具有可控厚度之氧化層。氧化層可捕獲由阻障層產生的濕氣及/或污染,亦防止內應力在結合襯墊結構中局部化。因此,結合襯墊結構之可能的晶鬚缺陷問題可得以減緩。
在一些實施例中,半導體裝置的形成方法包括在半導體裝置上形成互連結構,在互連結構上形成鈍化層,經由鈍化層形成至少一個開口,至少在開口中形成氧化層,及在氧化層上形成襯墊金屬層。互連結構之一部分由至少一開口曝露。在一些實施例中,半導體裝置的形成方法進一步
包括經由沉積製程,至少在開口中沉積阻障層,及氧化層經由氧化製程形成於阻障層上方。在一些實施例中,沉積阻障層包括在鈍化層的一部分上沉積阻障層,同時經由至少一個開口在互連結構上沉積阻障層。在一些實施例中,形成氧化層包括:曝露阻障層的頂表面至氧化劑氣體達一時段;及氧化阻障層,其中阻障層的一部分轉化為氧化層。在一些實施例中,時段範圍在約10秒與約600秒之間。在一些實施例中,氧化劑氣體包括氮及氧,且氮對氧的流量比範圍在約1/1000與約1000/1之間。在一些實施例中,沉積製程及氧化製程在同一腔室中實施。在一些實施例中,沉積製程及氧化製程係在不同腔室中分別實施。在一些實施例中,形成氧化層,以使得阻障層的厚度減小。在一些實施例中,形成氧化層是在範圍約25℃與約100℃之間的溫度下實施的。在一些實施例中,半導體裝置的形成方法進一步包括在形成氧化層之前,先使半導體裝置脫氣。在一些實施例中,形成半導體裝置的方法進一步包括在使半導體裝置脫氣後,預清潔半導體裝置。
在一些實施例中,半導體裝置包括具有導電部分之互連結構、位於導電部分上且其內具有開口的第一鈍化層、位於導電部分之一部分上方且至少位於第一鈍化層之開口中的氧化層,及直接位於氧化層上且電連接至導電部分的襯墊金屬層。在一些實施例中,氧化層的氧濃度向下降低。在一些實施例中,氧化層夾在襯墊金屬層與導電部分之間。在一些實施例中,半導體裝置進一步包括位於第一鈍化層上
方且接觸氧化層及襯墊金屬層的第二鈍化層。在一些實施例中,氧化層的一部分夾在第二鈍化層與第一鈍化層之間。
在一些實施例中,半導體裝置包括具有導電部分之互連結構、電連接至導電部分之阻障層、位於阻障層上之氧化層,及氧化層上之襯墊金屬層。在一些實施例中,氧化層的厚度範圍在約1Å與約500Å之間。在一些實施例中,氧化層及阻障層包括同一金屬。
前述內容介紹數個實施例之特徵,以使得熟習此項技術者可理解本揭示案之態樣。彼等熟習此項技術者應理解,其可將本揭示案之一些實施例用作設計或修飾其他製程與結構之基礎,以實現與本案介紹之實施例相同的目的及/或獲得相同之優勢。彼等熟習此項技術者亦應認識到,此種同等構成不脫離本揭示案之一些實施例之精神與範疇,且可在本案中進行各種變更、替換,及改動,而不脫離本揭示案之一些實施例之精神及範疇。
100:半導體裝置
102:基板
103:電晶體
1040:介電層
1040-104N:介電層
1041:介電層
1042:介電層
104N:介電層
105:導電插頭
1061:蝕刻停止層
1061-106N:蝕刻停止層
1062:蝕刻停止層
106N:蝕刻停止層
108:淺溝槽隔離
110:互連結構
1121:導電部分
1121-112N:導電部分
1122:導電部分
112N:導電部分
1141:導線
1141-114N:導線
1142:導線
114N:導線
1161:導電通孔
1161-116N:導電通孔
1162:導電通孔
116N:導電通孔
120:結合襯墊結構
130:第一鈍化層
140:阻障層
150:氧化層
160:襯墊金屬層
170:第二鈍化層
1032:閘極結構
1034:源極/汲極區域
1036:通道區域
1302:第一層
1304:第二層
1702:第一層
1704:第二層
Claims (10)
- 一種半導體裝置的形成方法,包括:在一半導體裝置上形成一互連結構;在該互連結構上形成一鈍化層;形成穿過該鈍化層的至少一個開口,其中該互連結構的一部分被該至少一個開口曝露;至少在該開口中形成一阻障層,其中該阻障層包括一金屬層、在該金屬層上方的一第一金屬氮化物層、及在該第一金屬氮化物層上方的一第二金屬氮化物層;至少在該開口中形成一氧化層,其中該氧化層的厚度小於該阻障層的該金屬層的厚度;及在該氧化層上形成一襯墊金屬層。
- 如請求項1所述之半導體裝置的形成方法,其中該阻障層經由一沉積製程形成,及該氧化層經由一氧化製程形成於該阻障層上方。
- 如請求項2所述之半導體裝置的形成方法,其中沉積該阻障層包括:在該鈍化層的一部分上沉積該阻障層,同時經由該至少一個開口在該互連結構上沉積該阻障層。
- 如請求項2所述之半導體裝置的形成方法,其中形成該氧化層包括: 曝露該阻障層的一頂表面至一氧化劑氣體達一時段;及氧化該阻障層,其中該阻障層的一部分轉化為該氧化層。
- 如請求項2所述之半導體裝置的形成方法,其中形成該氧化層,以使得該阻障層的一厚度減小。
- 如請求項1所述之半導體裝置的形成方法,進一步包括:在形成該氧化層之前,先使該半導體裝置脫氣。
- 一種半導體裝置,包括:一互連結構,具有一導電部分;一第一鈍化層,位於該導電部分上,且其內具有相對的複數個內側壁;一阻障層,電性連接該導電部分,該阻障層包括一金屬層、在該金屬層上方的一第一金屬氮化物層、及在該第一金屬氮化物層上方的一第二金屬氮化物層;一氧化層,位於該導電部分的一部分上方,且至少位於該第一鈍化層的相對的該些內側壁之間,其中該氧化層的厚度小於該阻障層的該金屬層的厚度;及一襯墊金屬層,直接位於該氧化層上,且電連接至該導電部分。
- 如請求項7所述之半導體裝置,其中該氧化層的氧濃度向下降低。
- 一種半導體裝置,包括:一互連結構,具有一導電部分;一阻障層,電連接至該導電部分,其中該阻障層包括一金屬層、在該金屬層上方的一第一金屬氮化物層、及在該第一金屬氮化物層上方的一第二金屬氮化物層;一氧化層,在該阻障層上,其中該氧化層的厚度小於該阻障層的該金屬層的厚度;及一襯墊金屬層,在該氧化層上。
- 如請求項9所述之半導體裝置,其中該氧化層及該阻障層包括同一金屬。
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201862725200P | 2018-08-30 | 2018-08-30 | |
US62/725,200 | 2018-08-30 | ||
US16/430,075 | 2019-06-03 | ||
US16/430,075 US11075179B2 (en) | 2018-08-30 | 2019-06-03 | Semiconductor device and method of forming the same |
Publications (2)
Publication Number | Publication Date |
---|---|
TW202013472A TW202013472A (zh) | 2020-04-01 |
TWI734164B true TWI734164B (zh) | 2021-07-21 |
Family
ID=69640586
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW108128362A TWI734164B (zh) | 2018-08-30 | 2019-08-08 | 半導體裝置及其形成方法 |
Country Status (3)
Country | Link |
---|---|
US (3) | US11075179B2 (zh) |
CN (1) | CN110875242B (zh) |
TW (1) | TWI734164B (zh) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20230063726A1 (en) * | 2021-08-30 | 2023-03-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit structure and manufacturing method thereof |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW388107B (en) * | 1998-09-23 | 2000-04-21 | Taiwan Semiconductor Mfg | Diffusion barrier Cu metal layer process and diffusion barrier layer thereof |
US20110057317A1 (en) * | 2009-09-07 | 2011-03-10 | Tohoku University | Contact plug structure, semiconductor device, and method for forming contact plug |
TW201338109A (zh) * | 2012-03-14 | 2013-09-16 | Taiwan Semiconductor Mfg | 半導體結構與其形成方法 |
Family Cites Families (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3528665B2 (ja) * | 1998-10-20 | 2004-05-17 | セイコーエプソン株式会社 | 半導体装置の製造方法 |
US6495449B1 (en) * | 2000-03-07 | 2002-12-17 | Simplus Systems Corporation | Multilayered diffusion barrier structure for improving adhesion property |
TW469590B (en) * | 2000-10-30 | 2001-12-21 | United Microelectronics Corp | Barrier layer formation method and the structure formed by the same |
KR100386034B1 (ko) * | 2000-12-06 | 2003-06-02 | 에이에스엠 마이크로케미스트리 리미티드 | 확산 방지막의 결정립계를 금속산화물로 충진한 구리 배선구조의 반도체 소자 제조 방법 |
KR100389037B1 (ko) * | 2001-04-11 | 2003-06-25 | 삼성전자주식회사 | 플립 칩형 반도체소자 및 그 제조방법 |
US6429524B1 (en) | 2001-05-11 | 2002-08-06 | International Business Machines Corporation | Ultra-thin tantalum nitride copper interconnect barrier |
KR20030002863A (ko) * | 2001-06-30 | 2003-01-09 | 주식회사 하이닉스반도체 | 코어를 가진 플러그 구조 상의 강유전체 메모리소자 및 그제조방법 |
US6489229B1 (en) * | 2001-09-07 | 2002-12-03 | Motorola, Inc. | Method of forming a semiconductor device having conductive bumps without using gold |
US6605874B2 (en) * | 2001-12-19 | 2003-08-12 | Intel Corporation | Method of making semiconductor device using an interconnect |
US6787831B2 (en) | 2002-01-15 | 2004-09-07 | Infineon Technologies Aktiengesellschaft | Barrier stack with improved barrier properties |
TW541659B (en) * | 2002-04-16 | 2003-07-11 | Macronix Int Co Ltd | Method of fabricating contact plug |
US6583507B1 (en) * | 2002-04-26 | 2003-06-24 | Bum Ki Moon | Barrier for capacitor over plug structures |
US7414315B2 (en) | 2005-10-31 | 2008-08-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Damascene structure with high moisture-resistant oxide and method for making the same |
JP5353109B2 (ja) * | 2008-08-15 | 2013-11-27 | 富士通セミコンダクター株式会社 | 半導体装置の製造方法 |
JP4415100B1 (ja) | 2008-12-19 | 2010-02-17 | 国立大学法人東北大学 | 銅配線、半導体装置および銅配線形成方法 |
US20120273949A1 (en) * | 2011-04-27 | 2012-11-01 | Globalfoundries Singapore Pte. Ltd. | Method of forming oxide encapsulated conductive features |
US8722531B1 (en) * | 2012-11-01 | 2014-05-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Barrier layer for copper interconnect |
JP2014141739A (ja) * | 2012-12-27 | 2014-08-07 | Tokyo Electron Ltd | 金属マンガン膜の成膜方法、処理システム、電子デバイスの製造方法および電子デバイス |
CN104051323B (zh) * | 2013-03-13 | 2017-12-29 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体封装结构及其制备方法 |
US9478510B2 (en) * | 2013-12-19 | 2016-10-25 | Texas Instruments Incorporated | Self-aligned under bump metal |
US9275952B2 (en) * | 2014-01-24 | 2016-03-01 | International Business Machines Corporation | Ultrathin superlattice of MnO/Mn/MnN and other metal oxide/metal/metal nitride liners and caps for copper low dielectric constant interconnects |
US10825724B2 (en) | 2014-04-25 | 2020-11-03 | Taiwan Semiconductor Manufacturing Company | Metal contact structure and method of forming the same in a semiconductor device |
US9455182B2 (en) * | 2014-08-22 | 2016-09-27 | International Business Machines Corporation | Interconnect structure with capping layer and barrier layer |
US9478626B2 (en) * | 2014-12-19 | 2016-10-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device with an interconnect structure and method for forming the same |
-
2019
- 2019-06-03 US US16/430,075 patent/US11075179B2/en active Active
- 2019-08-08 TW TW108128362A patent/TWI734164B/zh active
- 2019-08-13 CN CN201910742708.7A patent/CN110875242B/zh active Active
-
2021
- 2021-07-22 US US17/383,215 patent/US11682639B2/en active Active
-
2023
- 2023-05-04 US US18/312,325 patent/US20230275048A1/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW388107B (en) * | 1998-09-23 | 2000-04-21 | Taiwan Semiconductor Mfg | Diffusion barrier Cu metal layer process and diffusion barrier layer thereof |
US20110057317A1 (en) * | 2009-09-07 | 2011-03-10 | Tohoku University | Contact plug structure, semiconductor device, and method for forming contact plug |
TW201338109A (zh) * | 2012-03-14 | 2013-09-16 | Taiwan Semiconductor Mfg | 半導體結構與其形成方法 |
Also Published As
Publication number | Publication date |
---|---|
US11682639B2 (en) | 2023-06-20 |
US20200075518A1 (en) | 2020-03-05 |
TW202013472A (zh) | 2020-04-01 |
US20210351143A1 (en) | 2021-11-11 |
CN110875242B (zh) | 2022-04-29 |
US20230275048A1 (en) | 2023-08-31 |
US11075179B2 (en) | 2021-07-27 |
CN110875242A (zh) | 2020-03-10 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10867921B2 (en) | Semiconductor structure with tapered conductor | |
US20220059403A1 (en) | Removing Polymer Through Treatment | |
US7514354B2 (en) | Methods for forming damascene wiring structures having line and plug conductors formed from different materials | |
CN111261584B (zh) | 形成半导体器件的方法及半导体器件 | |
US11482493B2 (en) | Methods for reducing dual damascene distortion | |
TWI707440B (zh) | 積體電路結構及其製造方法 | |
US11456256B2 (en) | Semiconductor device, stacked semiconductor device and manufacturing method of semiconductor device | |
TW201436101A (zh) | 形成無凹陷連線結構的方法 | |
US20230275048A1 (en) | Semiconductor device and method of forming the same | |
US10157819B2 (en) | Semiconductor device and manufacturing method thereof | |
US20230215802A1 (en) | Conductive structures and methods of fabrication thereof | |
TW202410150A (zh) | 半導體裝置及其製造方法 | |
CN116153854A (zh) | 半导体结构及其形成方法 | |
JP2004288763A (ja) | 半導体装置の製造方法及び半導体装置 |