TWI611536B - 半導體裝置及半導體裝置的製造方法 - Google Patents

半導體裝置及半導體裝置的製造方法 Download PDF

Info

Publication number
TWI611536B
TWI611536B TW104135422A TW104135422A TWI611536B TW I611536 B TWI611536 B TW I611536B TW 104135422 A TW104135422 A TW 104135422A TW 104135422 A TW104135422 A TW 104135422A TW I611536 B TWI611536 B TW I611536B
Authority
TW
Taiwan
Prior art keywords
flux
semiconductor element
base metal
semiconductor device
bonding
Prior art date
Application number
TW104135422A
Other languages
English (en)
Other versions
TW201622089A (zh
Inventor
門口卓矢
Original Assignee
豐田自動車股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 豐田自動車股份有限公司 filed Critical 豐田自動車股份有限公司
Publication of TW201622089A publication Critical patent/TW201622089A/zh
Application granted granted Critical
Publication of TWI611536B publication Critical patent/TWI611536B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/492—Bases or plates or solder therefor
    • H01L23/4924—Bases or plates or solder therefor characterised by the materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04026—Bonding areas specifically adapted for layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/292—Material of the matrix with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/292—Material of the matrix with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29201—Material of the matrix with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29211—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29347—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/325—Material
    • H01L2224/32501—Material at the bonding interface
    • H01L2224/32503—Material at the bonding interface comprising an intermetallic compound
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/325—Material
    • H01L2224/32505—Material outside the bonding interface, e.g. in the bulk of the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/331—Disposition
    • H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/33181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/83455—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H01L2224/8381—Soldering or alloying involving forming an intermetallic compound at the bonding interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H01L2224/83815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
    • H01L23/4334—Auxiliary members in encapsulations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49537—Plurality of lead frames mounted in one device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582—Metallic layers on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Die Bonding (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

一種半導體裝置(100)，包括：半導體元件(6)；接合至該半導體元件並包括鎳膜(2a)的接合構件(2)；及接合至該接合構件並包含2.0重量百分比或更高之銅的接合層(4)，其中該接合層包括焊劑部分(4a)及Cu6Sn5部分，該焊劑部分的基底金屬包含至少錫作為構成元素並包含元素銅，且該Cu6Sn5部分與該鎳膜接觸。

Description

半導體裝置及半導體裝置的製造方法
本發明相關於半導體裝置及半導體裝置的製造方法。本發明特別相關於在其中將半導體元件的電極接合至接合構件的半導體裝置。
日本專利申請案公告案號第2007-67158號(JP 2007-67158 A)揭示在其中將半導體元件接合至接合構件的半導體裝置。在JP 2007-67158 A中，半導體元件經由Sn-Cu焊劑(錫及銅的混合合金焊劑)接合至接合構件。將構成該焊劑之Cu的比例調整為3.0重量百分比至7.0重量百分比(重量百分率)。亦即，半導體元件經由Sn-3.0至7.0Cu焊劑接合至接合構件。JP 2007-67158 A描述當熔化焊劑凝固時，Cu6Sn5化合物形成在該接合構件的表面上。由於Cu6Sn5化合物的形成，防止焊劑及接合構件之間的擴散。
如JP 2007-67158 A所述，當使用包含低於 0.9重量百分比之Cu的Sn-Cu焊劑時，理論上，Cu6Sn5化合物不會形成在接合構件的表面上。因此，JP 2007-67158 A描述半導體元件經由包含0.9重量百分比或更高之Cu的Sn-Cu焊劑接合至接合構件。在該描述中，如上文所述，將Sn-Cu焊劑中之Cu的比例調整成3.0重量百分比至7.0重量百分比更佳。
然而，當構成Sn-Cu焊劑之Cu的比例增加時，焊劑的熔點(或液相溫度)增加。例如，在Sn-3.0Cu焊劑的情形中，液相溫度高於310℃。當使用具有高熔點(液相溫度)的焊劑時，改善半導體元件的耐熱性以防止該半導體元件受損係必要的。因此，需要將Cu6Sn5化合物形成在接合構件之表面上而無需改善半導體元件之耐熱性的半導體裝置。
根據本發明的樣態，提供一種半導體裝置，包括：半導體元件；接合至該半導體元件並包括鎳膜的接合構件；及接合至該接合構件並包含2.0重量百分比或更高之銅的接合層，其中該接合層包括焊劑部分及Cu6Sn5部分，該焊劑部分的基底金屬包含至少錫作為構成元素並包含元素銅，且該Cu6Sn5部分與該鎳膜接觸。
「焊劑部分」係指在該處半導體元件接合至接合構件之接合層的部分。另一方面，用於形成接合層的材料(亦即，受熔化以形成接合層之前的材料)稱為「焊 劑材料」並與「焊劑部分」區分。另外，「Cu6Sn5部分(或Cu6Sn5)」包括以Ni取代一部分之Cu的化合物。亦即，「Cu6Sn5部分(或Cu6Sn5)」包括(Cu,Ni)6Sn5。例如，當使用將Ni加至其的Sn-Cu焊劑時，Ni固態溶解在Cu6Sn5中以形成(Cu,Ni)6Sn5。Cu6Sn5及(Cu,Ni)6Sn5呈現實質相同的功能。該接合構件並未受限於直接接合至半導體元件的構件，並包括接合至接合至半導體元件之構件的構件。亦即，描述在此說明書中的接合構件係指直接或間接接合至半導體元件的構件。
在該半導體裝置中，焊劑部分包含元素Cu，其包含在基底金屬中。此暗示用於將半導體元件接合至接合構件之焊劑材料的基底金屬包含元素Cu。元素Cu不構成該基底金屬。包含在焊劑材料之基底金屬中的元素Cu可係當將焊劑材料熔化然後凝固以將半導體元件接合至接合構件時用於形成Cu6Sn5部分的Cu成分。因此，在使用此焊劑材料接合期間，即使焊劑材料的基底金屬中之Cu的比例(在基底金屬中作為合金存在之Cu的比例)甚低，能形成Cu6Sn5部分。例如，當半導體元件經由在其中將元素Cu引入基底金屬中的焊劑材料接合至接合構件時，即使作為合金包含在焊劑材料的基底金屬中之Cu的比例低於0.9重量百分比，Cu6Sn5部分能形成在一部分的接合層中。特別在此半導體裝置中，包含在接合層中之銅的比例係2.0重量百分比或更高。以此方式，當接合層包含2.0重量百分比或更高的銅時，能可靠地得到Cu6Sn5部 分。另外，藉由將元素Cu引入焊劑材料的基底金屬中，能將作為合金包含在焊劑材料的基底金屬中之Cu的比例降低。因此，能降低焊劑材料的熔點(或液相溫度)。因此，高耐熱性對該半導體元件係不必要的。
根據本發明的另一樣態，提供一種半導體裝置的製造方法，包括：經由焊料接合半導體元件至包括鎳膜的接合構件，該焊料之基底金屬包含至少錫作為構成元素並包含元素銅，其中銅的百分比為2.0重量百分比或更高。
2、10‧‧‧金屬板
2a‧‧‧Ni膜
2b‧‧‧Cu部分
4、12、16‧‧‧接合層
4a‧‧‧焊劑部分
4b‧‧‧Cu6Sn5部分
6‧‧‧半導體元件
6a、6b‧‧‧電極
8‧‧‧樹脂
14‧‧‧金屬間隔器
20‧‧‧Cu粒子
100‧‧‧半導體裝置
本發明之範例實施例的特性、優點、及技術及產業重要性將參考隨附圖式於下文描述，其中相似數字指示相似元件，且其中：圖1係顯示半導體裝置的概要圖；圖2係顯示由虛線圍繞之圖1的部分的放大圖；圖3係Cu-Sn的二元相圖；圖4係顯示圖3之一部分(Sn：80至100)的放大圖；圖5係顯示範例1中的半導體元件及接合構件之間的接合介面的SEM影像；且圖6係顯示比較範例1中的半導體元件及接合構件之間的接合介面的SEM影像。
將參考圖1描述半導體裝置100。在半導體裝置100中，半導體元件6配置在二金屬板2、10之間，且該等組件以樹脂8壓模。金屬板2、10對應於半導體裝置100的電極板。另外，金屬板2、10對應於將半導體元件6的熱消散至半導體裝置100外側的散熱片。各金屬板2、10的一表面自樹脂8的表面暴露。在圖1中，未顯示連接至半導體元件6的終端、及焊線等。
接合層4設置在半導體元件6及金屬板2之間。更具體地說，將設置在半導體元件6之金屬板2側(在下文中，稱為「背表面」)上的電極6a焊接至金屬板2。另外，將設置在半導體元件6之金屬板10側(在下文中，稱為「前表面」)上的電極6b焊接至金屬間隔器14的背表面。將間隔器14的前表面焊接至金屬板10的背表面。亦即，半導體元件6經由接合層4接合至金屬板2、半導體元件6經由接合層16接合至間隔器14、且間隔器14經由接合層12接合至金屬板10。可以說金屬板10間接接合至半導體元件6。金屬板2、10及間隔器14係接合構件的範例。
半導體元件6、金屬板2、10、間隔器14、及接合層4、12、16的表面塗佈有底漆(未圖示)。藉由使用該底漆，改善樹脂8；及半導體元件6、金屬板2、10、間隔器14、及接合層4、12、及16之間的接合性 質。將熱固性聚醯亞胺使用為該底漆，並將環氧樹脂使用為樹脂8。
圖2概要地顯示金屬板2及接合層4之間的介面。如圖2所示，金屬板2包括Cu部分2b及Ni膜2a。Cu部分2b具有板形。Ni膜2a覆蓋Cu部分2b的表面。將Ni膜2a的厚度調整成2μm至20μm。接合層4包括焊劑部分4a及Cu6Sn5部分4b。在焊劑部分4a中，將Cu粒子20(元素Cu)分散在其係基底金屬的Sn-0.7Cu中。在以下描述中，Cu粒子20將也稱為Cu球20。也將Cu部分及覆蓋Cu部分之表面的Ni膜設置在電極6a的表面上。因此，電極6a及接合層4之間的介面也具有與金屬板2及接合層4之間的介面相同的組態。
焊劑部分4a包含1.3重量百分比的Cu球20。另外，如上文所述，因為焊劑部分4a的基底金屬係Sn-0.7Cu，基底金屬包含作為合金的Cu。Cu對焊劑部分4a之總重的比例為2.0重量百分比。Cu6Sn5部分4b與Ni膜2a接觸。將Cu6Sn5部分4b的厚度調整成3μm至20μm。Cu6Sn5部分4b沈積自金屬板2及半導體元件6經由其彼此接合的焊劑材料(包含1.3重量百分比之Cu球20的Sn-0.7Cu焊劑)。Cu6Sn5部分4b的厚度遠小於焊劑部分4a的厚度。因此，金屬板2及半導體元件6彼此接合前之焊劑材料的組態與金屬板2及半導體元件6彼此接合後之焊劑部分4a的組態實質相同。
將描述將半導體元件6接合至金屬板2的步 驟。製備在其中將Ni膜形成在電極6a之表面上的半導體元件6及在其中將Ni電鍍在Cu板之表面上的金屬板2。其次，半導體元件6的電極6a與金屬板2經由焊劑材料彼此接合。如上文所述，焊劑材料具有與焊劑部分4a實質相同的組態。亦即，焊劑材料的基底金屬係Sn-0.7Cu。Cu球20係以分散於其中的狀態包含在焊劑材料的基底金屬中。Cu對焊劑材料之總重的比例為2.0重量百分比。在該接合步驟中，首先，將焊劑材料配置成與金屬板2的Ni膜2a及半導體元件6的電極6a接觸。其次，焊劑材料藉由加熱熔化，然後凝固。接合層4藉由焊劑材料的凝固而形成。金屬板2的Ni膜2a及半導體元件6的電極6a經由接合層4彼此接合。
當焊劑材料凝固時，Cu6Sn5沈積在Ni膜2a的表面上。結果，如圖2所示，Cu6Sn5部分4b形成。在相關技術中，當構成焊劑材料之Cu的比例減少時，Cu6Sn5不沈積在Ni膜的表面上。另一方面，在本實施例中，Cu球20分散在焊劑材料的基底金屬中。Cu球20可係Cu6Sn5的材料。因此，雖然構成焊劑材料之Cu的比例甚低(0.7重量百分比)，Cu6Sn5部分4b能在焊劑材料的凝固期間形成。如上文所述，包含基底金屬及Cu球的焊劑材料中之Cu的比例係2.0重量百分比。當焊劑材料中之Cu的比例係2.0重量百分比時，Cu6Sn5部分4b能可靠地形成。
藉由包含Cu球20的焊劑材料，將作為合金 包含在焊劑材料的基底金屬中之Cu的比例抑制成低達0.7重量百分比。以此方式，藉由抑制包含在焊劑材料的基底金屬中之Cu的比例，能降低焊劑材料的熔點(或液相溫度)。如圖3所示，Sn-0.7Cu的熔點係227℃，其低於Sn-2.0Cu的液相溫度(270℃至280℃)。當半導體元件6及金屬板2彼此接合時，施加至半導體元件6的溫度能降低至比將不含Cu球之Sn-2.0Cu的焊劑材料用於該接合的情形更低。因此，使用根據本實施例的方法，能降低在焊接步驟中施加至半導體元件6的溫度。
如同在金屬板2中，在金屬板10中，將Ni電鍍在Cu板的表面上。在間隔器14中，將Ni電鍍在Cu板的二表面(前表面及背表面)上。另外，將Ni膜形成在電極6b的表面上。電極6b及間隔器14之間的接合部分及間隔器14及金屬板10之間的接合部分具有與半導體元件6及金屬板2之間的接合部分實質相同的結構。因此，半導體元件6及接合層16之間的介面、間隔器14及接合層16之間的介面、間隔器14及接合層12之間的介面、及金屬板10及接合層12之間的介面的描述將以金屬板2及接合層4之間的介面的描述取代。
將描述半導體裝置100的有利效應。如上文所述，將Cu6Sn5部分4b設置在焊劑部分4a及Ni膜2a之間。因此，Cu6Sn5部分4b的功能如同障壁層。因此，即使當熱從半導體元件6產生時，能抑制焊劑部分4a及Ni膜2a之間的反應。當焊劑部分4a及Ni膜2a之間的反 應到達Cu部分2b時，金屬板2可從半導體元件6剝除。由於Cu6Sn5部分4b，能防止此種剝除。
另外，焊劑材料包含Cu球20。結果，當焊劑材料熔化時，能抑制焊劑材料之形狀上的明顯改變。具體地說，當焊劑材料熔化時，焊劑材料不從金屬板2及半導體元件6之間的間隙流動，使得能防止金屬板2及半導體元件6之間的接觸。換言之，包含Cu球20的焊劑材料的功能如同防止金屬板2及半導體元件6之間的接觸的間隔器。
圖5係顯示當半導體元件及金屬板經由在其中將1.3重量百分比的Cu球引入至以Sn-0.7Cu形成之基底金屬中的焊劑材料彼此接合時在焊劑部分及金屬板(Ni膜形成於其上的Cu板)之間的接合介面的SEM影像(範例1)。另外，圖6係顯示當半導體元件及金屬板經由以不含Cu球之Sn-0.7Cu形成的焊劑材料彼此接合時在焊劑部分及金屬板之間的接合介面的SEM影像(比較範例1)。
在範例1及比較範例1中，因為焊劑材料的基底金屬均相同(Sn-0.7Cu焊劑)，焊劑材料的熔點相同。如圖6所示，在比較範例1中，不係Cu6Sn5層而係Ni3Sn4層形成在Ni膜2a及焊劑部分4a之間。此結果顯示當包含在基底金屬中之Cu的比例甚低時(0.7重量百分比)，不形成Cu6Sn5層。在比較範例1中，當接合層的溫度為半導體裝置的驅動所增加時，焊劑部分中的Sn擴 散，且Ni3Sn4層生長。
另一方面，在範例1中，Cu6Sn5部分4b形成在Ni膜2a及焊劑部分4a之間。藉由將1.3重量百分比的Cu球分散在Sn-0.7Cu的基底金屬中，Cu6Sn5部分能在半導體元件及金屬板之間的接合期間形成在金屬板的表面上而不沒溫度上的增加。
在上述實施例之範例的描述中，半導體元件及金屬板經由在其中將1.3重量百分比的Cu球分散在Sn-0.7Cu之基底金屬中的焊劑材料彼此接合。然而，該相同效應甚至能在半導體元件及金屬板經由在其中將2.0重量百分比的Cu球分散在Sn(100%的錫)之基底金屬中的焊劑材料彼此接合時得到。在此情形中，Sn之基底金屬的熔點係232℃，其低於Sn-2.0Cu之焊劑材料的液相溫度(270℃至280℃)。
在上述實施例的描述中，在該半導體裝置中，半導體元件6的各電極6a、6b、金屬板2、10、及間隔器14包括Cu部分(Cu板)及覆蓋該Cu部分的Ni膜。然而，該半導體裝置可具有電極6a、6b的至少一者、金屬板2、10、及間隔器14包括Cu部分及覆蓋該Cu部分之Ni膜的結構。在半導體裝置中，由於熱而在接合部分中導致缺陷的風險依據製造步驟期間的加熱情況及環境溫度、及從半導體元件產生的熱等而變化。在半導體裝置100中，缺陷可能由於在與半導體元件6直接接觸之部分中的熱而發生。亦即，在半導體裝置100中，缺陷可 能發生在金屬板2及半導體元件6之間的接合部分中及半導體元件6及間隔器14之間的接合部分中。特別係缺陷可能發生在半導體元件6及間隔器14之間的接合部分中。於此說明書中揭示之相關於接合層的技術(將元素銅包含在基底金屬中的焊劑部分，及與鎳膜接觸的Cu6Sn5部分)可僅施用至可能發生缺陷的上述部分。
將總結在此說明書中揭示之使用在半導體裝置中的焊劑材料的特徵。該焊劑材料包含：包含至少錫作為構成元素的基底金屬(在下文中，也稱為「焊劑基底金屬」)；及引入焊劑基底金屬中的元素銅。焊劑基底金屬中之錫的比例可係100%(含Cu率：0重量百分比)。另外，當焊劑基底金屬係Sn-Cu焊劑時，焊劑基底金屬中的含Cu率可係0.3重量百分比或更高且係0.5重量百分比或更高為佳。焊劑基底金屬係Sn-0.7Cu(含Cu率：0.7%)更佳。另外，焊劑基底金屬中的含Cu率可係7.6重量百分比或更低、且係5.0重量百分比或更低為佳、且係4.0重量百分比或更低更佳。
將描述於此說明書中揭示之半導體裝置的部分技術特徵。以下特性具有獨立技術重要性。
該半導體裝置包括：半導體元件、接合至該半導體元件並包括鎳膜的接合構件；及接合至該接合構件的接合層。該接合層可包括：焊劑部分；與該鎳膜接觸的Cu6Sn5部分。該焊劑部分的基底金屬可包含至少錫作為構成元素。另外，該焊劑部分可包含元素銅(Cu)在該基底 金屬中。包含在接合層中之Cu的比例可係2.0重量百分比或更高。
焊劑部分的基底金屬中之錫(Sn)的比例可係100%。另外，焊劑部分的基底金屬可係Cu及Sn的化合物(Sn-Cu焊劑)。元素Cu可不構成焊劑部分的基底金屬。元素Cu可係微粒。在半導體元件及接合構件彼此接合之前，元素Cu可預先分散在焊劑材料的基底金屬中。當半導體元件及接合構件彼此接合時，Cu6Sn5部分可沈積在接合構件的表面(鎳膜的表面)上。
當焊劑部分的基底金屬係Sn-Cu焊劑時，基底金屬中的含Cu率可係0.3重量百分比或更高且係0.5重量百分比或更高為佳。如可從圖3清楚地看到的，在Sn-0.3Cu焊劑及Sn-0.5Cu焊劑中，η(eta)相化合物(Cu6Sn5)在從液相至固相的相轉變期間形成。藉由將包含在Sn-Cu焊劑中的含Cu率調整為0.3重量百分比或更高，即使元素Cu未充分地分散在焊劑材料的基底金屬中，Cu6Sn5部分能形成在鎳膜的表面上。藉由調整含Cu率至0.5重量百分比或更高，Cu6Sn5部分能更可靠地形成。另外，「Sn-Cu焊劑」係用於將錫及銅包含為主成分之合金的通用術語，除了錫及銅外，可更包含，例如，Ni、P(磷)、Bi(鉍)、Sb(銻)、或Ag(銀)。
焊劑部分之基底金屬中的含Cu率可係7.6重量百分比或更低，且係5.0重量百分比或更低為佳，且係4.0重量百分比或更低更佳。如圖3及4所示，當Sn-Cu 焊劑中的含Cu率高於7.6重量百分比時，ε(upsilon)相化合物(Cu3Sn)在基底金屬從液相至固相的相轉變期間形成。另一方面，當含Cu率係7.6重量百分比或更低時，η(eta)相化合物(Cu6Sn5)在基底金屬從液相至固相的相轉變期間形成。藉由將焊劑部分之基底金屬中的含Cu率調整成7.6重量百分比或更低，Cu6Sn5部分能可靠地形成。
如圖4所示，含Cu率係5.0重量百分比的Sn-Cu焊劑(Sn-5.0Cu焊劑)具有350℃的熔點。用於半導體元件的元件保護膜可在高於350℃的溫度退化。因此，當含Cu率高於5.0重量百分比時，必需採取對策以抑制元件保護膜的退化。藉由將焊劑部分(焊劑材料)之基底金屬中的含Cu率調整至5.0重量百分比或更低，元件保護膜的退化能受抑制而不需採取任何特殊對策。
如圖4所示，含Cu率係4.0重量百分比的Sn-Cu焊劑(Sn-4.0Cu焊劑)具有330℃的熔點。使用在半導體元件中的電極可依據其材料在高於330℃的溫度破裂。因此，當含Cu率高於4.0重量百分比時，必需採取對策以防止電極破裂。例如，必需限制電極的材料。藉由調整含Cu率至4.0重量百分比或更低，能不需採取任何特殊對策而得到電極破裂受抑制的半導體裝置。焊劑部分的基底金屬(及焊劑材料的基底金屬)係Sn-0.7Cu(含Cu率：0.7%)更佳，而非將在Sn-0.1至7.6Cu中的焊劑材料之基底金屬的熔點儘可能地降低。
包含在接合層(焊劑部分的基底金屬、元素Cu、及Cu6Sn5部分)中之Cu的比例可係2.0重量百分比或更高，且係3.0重量百分比或更高為佳。如可從圖3及4清楚地看到的，在Sn-2.0Cu焊劑中，η(eta)相化合物(Cu6Sn5)在從液相至固相的相轉變期間形成。亦即，藉由將包含在接合層中之Cu的比例調整成2.0重量百分比或更高，Cu6Sn5部分能可靠地形成在鎳膜的表面上。另外，藉由將包含在接合層中之Cu的比例調整成3.0重量百分比或更高，Cu6Sn5部分能更穩定地形成在鎳膜的表面上。元素Cu的比例可依據構成焊劑部分的基底金屬之Cu的比例調整。如上文所述，從可靠地形成Cu6Sn5部分的觀點，包含在接合層中之Cu的比例係7.6重量百分比或更低為佳。
在上文中，已詳細地描述本發明的具體範例。然而，此等範例僅係例示的且不限制申請專利範圍。於申請專利範圍中描述的技術包括上述具體範例的各種修改及變化。描述於此說明書及圖式中的技術特性在單獨或結合使用時呈現技術重要性，且未受限於在本申請案提出申請時描述於申請專利範圍中的該等組合。例示於此說明書或圖式中的技術同時實現數個目的，且技術重要性係藉由實現該等目的的一者而得到。
2‧‧‧金屬板
2a‧‧‧Ni膜
2b‧‧‧Cu部分
4‧‧‧接合層
4a‧‧‧焊劑部分
4b‧‧‧Cu6Sn5部分
20‧‧‧Cu粒子

Claims (6)

  1. 一種半導體裝置(100)，其特徵為包含：半導體元件(6)；接合構件(2)，其接合至該半導體元件並包括鎳膜(2a)；及接合層(4)，其接合至該接合構件並包含2.0重量百分比或更高的銅，其中該接合層包括焊劑部分(4a)及Cu6Sn5部分，該焊劑部分的基底金屬包含至少錫作為構成元素並且更包含元素銅，其中該元素銅為(a)不與該錫結合，(b)非熔態而是固態，(c)純金屬，及(d)分散在該基底金屬中，且該Cu6Sn5部分與該鎳膜接觸。
  2. 如申請專利範圍第1項的半導體裝置，其中包含在該接合層中之銅的比例為7.6重量百分比或更低。
  3. 如申請專利範圍第1或2項的半導體裝置，其中該基底金屬係包含錫及銅作為主要成分的合金。
  4. 如申請專利範圍第3項的半導體裝置，其中該基底金屬係包含Sn-0.7Cu作為主要成分的合金。
  5. 一種半導體裝置的製造方法，其特徵為包含：經由焊料接合半導體元件至接合構件，其包括鎳膜，該焊料之基底金屬包含至少錫作為構成元素並包含元素 銅，其中銅的百分比為2.0重量百分比或更高。
  6. 如申請專利範圍第5項的方法，其中該半導體元件經由該焊料接合至其在該接合構件上的該鎳膜。
TW104135422A 2014-10-30 2015-10-28 半導體裝置及半導體裝置的製造方法 TWI611536B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2014-221341 2014-10-30
JP2014221341A JP6287759B2 (ja) 2014-10-30 2014-10-30 半導体装置とその製造方法

Publications (2)

Publication Number Publication Date
TW201622089A TW201622089A (zh) 2016-06-16
TWI611536B true TWI611536B (zh) 2018-01-11

Family

ID=54364126

Family Applications (1)

Application Number Title Priority Date Filing Date
TW104135422A TWI611536B (zh) 2014-10-30 2015-10-28 半導體裝置及半導體裝置的製造方法

Country Status (7)

Country Link
US (1) US9824994B2 (zh)
EP (1) EP3021355A1 (zh)
JP (1) JP6287759B2 (zh)
KR (1) KR102004577B1 (zh)
CN (1) CN105575928B (zh)
BR (1) BR102015027628B1 (zh)
TW (1) TWI611536B (zh)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6287759B2 (ja) 2014-10-30 2018-03-07 トヨタ自動車株式会社 半導体装置とその製造方法
JP6281468B2 (ja) 2014-10-30 2018-02-21 トヨタ自動車株式会社 半導体装置とその製造方法
JP6330786B2 (ja) 2015-11-16 2018-05-30 トヨタ自動車株式会社 半導体装置の製造方法
JP6638626B2 (ja) * 2016-11-21 2020-01-29 トヨタ自動車株式会社 半導体装置の製造方法
JP7180392B2 (ja) * 2019-01-11 2022-11-30 株式会社デンソー 半導体装置及びその製造方法
JP7428595B2 (ja) * 2020-06-08 2024-02-06 日立Astemo株式会社 半導体装置、および半導体装置の製造方法
US11610861B2 (en) * 2020-09-14 2023-03-21 Infineon Technologies Austria Ag Diffusion soldering with contaminant protection
CN116438636A (zh) * 2021-05-18 2023-07-14 富士电机株式会社 半导体装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040007384A1 (en) * 2002-03-08 2004-01-15 Hitachi, Ltd. Electronic device
US20040102023A1 (en) * 2002-08-13 2004-05-27 Fuji Electric Co., Ltd. Semiconductor device and method of relaxing thermal stress
US20070057021A1 (en) * 2005-08-31 2007-03-15 Osamu Ikeda Semiconductor device and automotive AC generator
US20090134501A1 (en) * 2007-11-26 2009-05-28 Infineon Technologies Ag Device and method including a soldering process
US20090243089A1 (en) * 2008-03-31 2009-10-01 Infineon Technologies Ag Module including a rough solder joint

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005340275A (ja) 2004-05-24 2005-12-08 Denso Corp 電子部品接合体、その製造方法、およびそれを含む電子装置
JP5369682B2 (ja) 2006-04-28 2013-12-18 千住金属工業株式会社 フォームはんだおよび電子部品
JP5045673B2 (ja) 2006-09-01 2012-10-10 千住金属工業株式会社 機能部品用リッドとその製造方法
JP2010179336A (ja) * 2009-02-05 2010-08-19 Toyota Central R&D Labs Inc 接合体、半導体モジュール、及び接合体の製造方法
US8378485B2 (en) * 2009-07-13 2013-02-19 Lsi Corporation Solder interconnect by addition of copper
JP2011044624A (ja) 2009-08-24 2011-03-03 Hitachi Ltd 半導体装置および車載用交流発電機
JP5517694B2 (ja) 2010-03-29 2014-06-11 株式会社 日立パワーデバイス 半導体装置
US8802553B2 (en) 2011-02-10 2014-08-12 Infineon Technologies Ag Method for mounting a semiconductor chip on a carrier
JP5557788B2 (ja) 2011-04-07 2014-07-23 株式会社 日立パワーデバイス 電子装置の製造方法
EP2824696B1 (en) * 2012-03-07 2021-05-05 Toyota Jidosha Kabushiki Kaisha Semiconductor device and method of manufacture thereof
JP5677346B2 (ja) 2012-03-22 2015-02-25 株式会社日立製作所 半導体素子、半導体装置、半導体装置の製造方法及び接続材料
US8814030B2 (en) * 2012-04-17 2014-08-26 Toyota Motor Engineering & Manufacturing North America, Inc. Improvements of long term bondline reliability of power electronics operating at high temperatures
JP6061248B2 (ja) * 2013-03-29 2017-01-18 国立研究開発法人産業技術総合研究所 接合方法及び半導体モジュールの製造方法
JP6281468B2 (ja) * 2014-10-30 2018-02-21 トヨタ自動車株式会社 半導体装置とその製造方法
JP6287759B2 (ja) 2014-10-30 2018-03-07 トヨタ自動車株式会社 半導体装置とその製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040007384A1 (en) * 2002-03-08 2004-01-15 Hitachi, Ltd. Electronic device
US20040102023A1 (en) * 2002-08-13 2004-05-27 Fuji Electric Co., Ltd. Semiconductor device and method of relaxing thermal stress
US20070057021A1 (en) * 2005-08-31 2007-03-15 Osamu Ikeda Semiconductor device and automotive AC generator
US20090134501A1 (en) * 2007-11-26 2009-05-28 Infineon Technologies Ag Device and method including a soldering process
US20090243089A1 (en) * 2008-03-31 2009-10-01 Infineon Technologies Ag Module including a rough solder joint

Also Published As

Publication number Publication date
KR20160052342A (ko) 2016-05-12
US20160126207A1 (en) 2016-05-05
CN105575928B (zh) 2018-12-11
CN105575928A (zh) 2016-05-11
JP6287759B2 (ja) 2018-03-07
BR102015027628A2 (pt) 2016-09-27
JP2016092063A (ja) 2016-05-23
KR102004577B1 (ko) 2019-07-26
TW201622089A (zh) 2016-06-16
BR102015027628B1 (pt) 2021-11-03
US9824994B2 (en) 2017-11-21
EP3021355A1 (en) 2016-05-18

Similar Documents

Publication Publication Date Title
TWI611536B (zh) 半導體裝置及半導體裝置的製造方法
US9659892B2 (en) Semiconductor device and method of manufacturing semiconductor device
TWI505899B (zh) A bonding method, a bonding structure, and a method for manufacturing the same
TWI464031B (zh) 抑制柯肯達爾孔洞形成於銲料與銅銲墊之間的方法
US20160271738A1 (en) Lead-Free, Silver-Free Solder Alloys
US20150029670A1 (en) Sn-cu-based lead-free solder alloy
WO2017134974A1 (ja) 接合材、それを用いた接合方法及び接合構造
US9669493B2 (en) Layered solder material for bonding different species of electrodes and method of bonding the different species of electrodes in an electronic component
JP4959539B2 (ja) 積層はんだ材およびそれを用いたはんだ付方法ならびにはんだ接合部
JP5758242B2 (ja) 鉛フリー接合材料
WO2011036829A1 (ja) 半導体装置及びその製造方法
JP6477517B2 (ja) 半導体装置の製造方法
JP2008034514A (ja) 半導体装置
JP2014146635A (ja) はんだ接合方法およびはんだボールと電極との接合構造体
JP4745878B2 (ja) はんだ皮膜及びそれを用いたはんだ付方法