TWI609996B - 電化學電鍍方法 - Google Patents

電化學電鍍方法 Download PDF

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TWI609996B
TWI609996B TW104107417A TW104107417A TWI609996B TW I609996 B TWI609996 B TW I609996B TW 104107417 A TW104107417 A TW 104107417A TW 104107417 A TW104107417 A TW 104107417A TW I609996 B TWI609996 B TW I609996B
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cobalt
substrate
bath
seed layer
nickel
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林約翰Ｗ
艾密許伊斯梅爾
夏維羅伊
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應用材料股份有限公司
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Abstract

用於施用導電膜至具晶種層的基板上的電化學製程包括把基板放入接觸含鈷或鎳鹽的電化學電鍍浴，且電鍍浴的pH為4.0至9.0。電流經引導通過浴而至基板。浴中的鈷或鎳離子沉積至晶種層上。電鍍浴可含氯化鈷和甘氨酸。電流可為1-50毫安/平方公分。完成電化學製程後，將基板移出電鍍浴、潤洗及乾燥，接著以200℃至400℃的溫度退火，以改善材料性質及減少接縫線缺陷。可多次循環進行電鍍及退火製程。

Description

電化學電鍍方法
本發明的領域為電化學處理微型工件、晶圓或基板的方法。
諸如微米級電子、電機或光學裝置等微電子裝置通常係製造在工件或基板上及/或內，例如矽晶圓。在典型製造製程中，例如在半導體材料晶圓上，會先利用化學氣相沉積(CVD)、物理氣相沉積(PVD)、無電電鍍製程或其他適合方法於基板表面施用導電晶種層。形成晶種層後，在存有含金屬離子的電處理液中，於晶種層與一或更多電極間施加適當電位，將金屬毯覆層或圖案化層電鍍至基板上。接著在後續程序中清洗、蝕刻及/或退火處理基板，及形成裝置、觸點或導線。一些基板可具有阻障層，晶種層形成於阻障層上。
目前，微電子裝置大多製作在鍍銅基板上。雖然銅具有高導電率，但銅通常需要阻障層，例如氮化鉭(TaN)，以防止銅擴散到基板或基板上的介電材料內。此類阻障層的導電率相當低。利用已知技術，以使用酸銅化學品或電鍍液電鍍的銅填充基板上的特徵結構。該等化學品通常使用添加 劑來促進超共形填充製程(特徵結構填充主要係從下往上、而非從側邊往內)及形成無孔隙填充。隨著特徵結構尺寸微縮，以傳統銅電鍍製程達成無孔隙填充益發困難。又隨著特徵結構變小，銅所需阻障層仍佔很大體積，此係因為無論特徵結構尺寸為何，防止銅擴散需維持最小阻障層厚度。
例如，若防止銅擴散所需的最小阻障層厚度為3nm，則就關鍵尺寸60nm、深寬比4：1的特徵結構而言，阻障層約佔橫斷面積的11%。然對關鍵尺寸20nm、深寬比2：1的特徵結構來說，阻障層厚度仍需為3nm，但如此便佔橫斷面積的33%。在此情況下，具低導電率的阻障層體積按比例很大，是以內連線、通孔或其他特徵結構的電阻按比例也很高。當特徵結構日益縮小，銅與阻障層的比例將增加到電阻變得無法接受的程度。
克服此技術挑戰的一方式係用不需阻障層的金屬取代銅，例如鈷。雖然鈷的電阻比銅高(鈷為6微歐姆-公分；銅為2微歐姆-公分)，但鈷不需阻障層，因為鈷不會擴散到矽或介電質內。美國專利申請公開案第20130260555號描述利用化學氣相沉積(CVD)施用鈷，以填充大與小特徵結構。儘管此方法可成功用於如7-10nm的較小特徵結構，但CVD不適於填充大於約10nm的特徵結構。故仍需改良技術。
用於施用導電膜至具晶種層的基板上的電化學製程包含：把基板放入接觸含鈷或鎳鹽的電化學電鍍浴，且電鍍浴的pH為4.0至9.5；及引導電流通過浴，以減少電鍍浴中 的鈷或鎳離子，及沉積鈷或鎳膜至晶種層上。
10‧‧‧基板
12、20‧‧‧特徵結構
14‧‧‧晶種層
16‧‧‧膜
18‧‧‧金屬層/覆蓋層
第1A圖係具TaN阻障層和Cu晶種層的基板上的未填充或未電鍍結構的掃描式電子顯微鏡(SEM)圖。在一些應用中，阻障層可為其他材料，例如TiN，或者可無阻障層。晶種層亦可為CVD鈷。
第1B圖圖示第1A圖現已填充由鹼性電鍍浴電化學沉積鈷的結構。
第2A圖係使用pH 6.5的鈷-甘氨酸電鍍浴電鍍鈷至TaN/Co晶種層上的類似結構的SEM圖，並且顯示接縫線缺陷。
第2B圖圖示第2A圖經退火後的結構，並且顯示接縫線缺陷減少或消除。
第3圖係使用pH 8.5的鈷-EDA電鍍浴電鍍鈷至CVD Co晶種層上的另一結構的SEM圖。
第4A圖至第4E圖係本發明的方法實施例示意圖。
第5圖係退火後的線路電阻測試資料曲線圖。
第6A圖至第6C圖係超共形填充的示意圖。
第7A圖至第7C圖係共形填充的示意圖。
第8A圖至第8C圖係共形填充、然後退火處理的示意圖。
目前已提出各種使用酸性與鹼性鈷浴的已知鈷電鍍方法。然電鍍鈷至具很小特徵結構(例如60奈米(nm)、40 nm、30nm或以下的特徵結構)的基板上將面臨不同的挑戰。具很小特徵結構的基板必然具有很薄的晶種層。對該等基板使用已知鈷電鍍方法通常會使很薄的晶種層溶解，以致妨礙適當電鍍。本發明的方法使用具特定pH範圍的鈷浴，以減少晶種層腐蝕。
鎳的電鍍特性類似鈷。所述鈷的用法亦可應用到以鎳取代鈷。在此提及的內連線包括基板上或內的其他特徵結構，例如溝槽、孔洞和通孔。
利用電化學沉積至導電基板上可達成沉積金屬至次微米內連線內。電鍍金屬可選自包括銅、鈷、鎳、金、銀或鉑。共形及超共形電化學沉積金屬後可選擇性熱處理。
中性至鹼性水溶液可用於沉積電化學電鍍金屬。例如，鈷或鎳錯合電鍍液可用於電化學沉積鈷或鎳至次微米內連線或基板上的其他特徵結構內。基板可提供具有晶種層，晶種層可由無電沉積、物理氣相沉積或化學氣相沉積形成。用於晶種層的材料可包括銅、錳摻雜銅、釕(Ru)等。矽化鈷或矽化鎳亦可用於晶種層。若有，則基板上的阻障層可由化學氣相沉積(CVD)或其他已知技術施用。
電鍍或電化學沉積製程後可為退火步驟，用以改善電化學電鍍鈷或鎳的材料性質，及減少共形電鍍相關的接縫線孔隙。在本發明的方法中，電鍍後退火可以比傳統銅製程低的溫度進行。退火步驟能穩定電鍍膜。此亦有助於移除共形電鍍製程的接縫線和微孔隙。退火步驟亦可驅除因電鍍條件而陷入的雜質，進而改善膜性質。在一些應用中，可視特 定電鍍條件與化學品而省略退火步驟。例如，促進超共形成長及併入少量雜質的鈷電鍍液可不需退火步驟。
A. 使用鈷的電化學沉積 i. 綜述
本發明的方法圖示於第4A圖至第4E圖。在第4A圖中，基板10(例如矽晶圓)具有特徵結構12和導電晶種層14。在一些應用中，可在晶種層14下面提供阻障層(未圖示)。在第4B圖中，鈷或鎳共形或超共形膜16置於晶種層14上。膜16可部分或完全填充特徵結構，如第4B圖所示，膜16部分填充特徵結構12。膜16的厚度足以提供至少10%、20%、30%、40%或50%填充特徵結構(對照幾乎無顯著填充的晶種層14)。阻障層可選擇性為PVD TaN、ALD TaN、PVD TiN、ALD TiN、ALD MnN、CVD MnN、CVD NiSi或CoSi，其中PVD係物理氣相沉積，CVD係化學氣相沉積，ALD係原子層沉積。
第4C圖圖示退火使膜16再流以進一步填充特徵結構12。第4D圖圖示沉積覆蓋層或金屬層18，該層可為相同金屬(如同用於膜16的鈷或鎳)或不同金屬。第4E圖圖示化學機械研磨後的基板，且覆蓋層18選擇性移除而留下填充特徵結構12。
可使用pH 4至pH 9的中性至鹼性鈷電鍍液，將膜16電鍍至晶種層14上。電鍍液可含螯合劑，例如檸檬酸、甘氨酸、酒石酸、乙二胺等。
第6A圖至第6C圖圖示超共形填充基板上的特徵結 構，例如溝槽或通孔。如圖所示，特徵結構主要從下往上填充、而非從側邊往內，藉以提供無縫電鍍特徵結構。填充的進行亦可為電鍍共形膜、然後為退火步驟或另一層超共形膜。第7A圖至第7C圖圖示共形填充，其中特徵結構主要從側邊往內填充，而於填充特徵結構中形成縫隙。第8A圖至第8C圖圖示和第7A圖至第7C圖一樣的製程，但係在退火後無縫填充特徵結構。共形或超共形電鍍可用於進行所述方法。
ii.製程詳述
1.基板提供具有導電晶種層，例如CVD或無電沉積鈷，但其他如銅、鎳、金、銀、鈀及/或釕也可使用。第1A圖圖示未填充特徵結構的實例，未填充特徵結構具有施用於基板上的阻障層(例如TaN)和阻障層上的銅晶種層。第2A圖圖示共形電化學沉積(ECD)鈷至具CVD鈷層於TaN阻障層上的基板上，並且顯示接縫線缺陷。第3圖圖示共形ECD鈷至CVD鈷晶種層上的實例。
2.使用預鍍處理，即在電鍍前，將還原劑(例如He/H2、形成氣體等)施用於基板。可在弱酸性、中性或鹼性電鍍浴中，使結構電鍍上鈷。在第1B圖、第2A圖及第2B圖中，氯化鈷與甘氨酸浴在pH 6.5下用於鈷沉積。在第3圖中，氯化鈷與EDA浴在pH 8.5下用於鈷沉積。用於電化學沉積製程的電流密度可為1-50毫安/平方公分。
3.若晶種層較易腐蝕，例如CVD鈷晶種層，則可使用中性至鹼性電鍍浴。當pH從6.5提高到8.3時，電化學沉積鈷一般會完全覆蓋在由化學氣相沉積施用的鈷晶種層 上。電鍍浴的pH或可為下列範圍之一：7.5至8.5、7.8至8.5、8.0至8.5或7.8至9.0。
4.完成共形或超共形電化學沉積鈷後，以200℃至450℃的溫度熱處理基板，以改善材料性質及/或減少接縫線缺陷。第2B圖圖示以350℃在H2/He環境中退火後的基板。掃描式電子顯微鏡圖看不到接縫線。或者可使用其他氣體，例如N2/He或淨化H2。如第2B圖所示，退火處理後，亦可改善表面粗糙度。
利用緩慢電鍍製程填充特徵結構，接著退火處理來改善材料性質，然後沉積覆蓋層18供化學機械研磨，以進行多重電鍍多重退火製程。電鍍鈷可用於覆蓋層18。在多重電鍍製程中，第一和第二電鍍步驟提供第一和第二膜於基板上，如以200℃至450℃的溫度退火處理基板後，進行第三電鍍步驟，以提供金屬層於第二膜上。接著化學機械研磨金屬層。
iii.測試結果
利用所述方法填充60nm-25nm的特徵結構。測試結果顯示成功電鍍至具高表面電阻的薄晶種層，即300毫米(mm)晶圓的200歐姆/sq的晶種層上。此類晶種層通常會在習知酸銅電鍍液中快速腐蝕，但使用上述鈷或鎳電鍍液時不會明顯蝕刻或腐蝕。測試結果亦證實使用弱酸性至鹼性鈷電鍍液，可成功電鍍鈷膜至6nm CVD鈷晶種層上。
測試資料亦顯示電鍍後熱處理可降低線路電阻和毯覆膜電阻，此如第5圖所示。亦可對具CVD鈷晶種層的基板 進行多重電鍍多重退火製程。多重電鍍製程一例為利用緩慢電鍍液填充特徵結構，接著把基板移到另一腔室，以於化學機械研磨前，快速電鍍覆蓋或金屬層18。
B. 使用鎳的電化學沉積
上述方法和參數亦可配合鎳使用。
相較於僅有CVD的製程，上述方法提供的產量高得多並可降低成本，故適於大量製造。
C. 附加方法
把基板放入接觸包含金屬的電化學電鍍浴，且金屬選自鈷或鎳，電鍍浴的pH為4.0至9.0，以進行電化學製程而沉積導電膜至基板的次微米內連線內，基板具有晶種層於上。按1-50毫安/平方公分的額定引導電流通過浴而至基板，以沉積金屬膜至基板的特徵結構上。將基板移出電鍍浴、潤洗及乾燥，接著以如200℃至450℃的溫度選擇性退火，促使金屬膜再流而進一步填充基板的特徵結構。電鍍浴可包括氯化鈷及/或甘氨酸。該等步驟可反覆進行，且其間可有或無退火步驟。例如，晶圓可經歷電鍍、乾燥及退火處理的至少兩次循環。
另一製程可用於把基板放入接觸含鈷或鎳鹽的電化學電鍍浴，且電鍍浴的pH為4.0至9.5，以施用導電膜至基板上，基板具有晶種層、具第一尺寸的第一特徵結構和具第二尺寸的第二特徵結構，第二尺寸大於第一尺寸。引導電流通過浴來進行第一電鍍步驟，以減少電鍍浴中的鈷或鎳離子，及沉積共形或超共形的第一鈷或鎳膜至晶種層上，第一 膜完全填充第一特徵結構，但不完全填充第二特徵結構。接著引導電流通過浴來進行第二電鍍步驟，以減少電鍍浴中的鈷或鎳離子，及沉積共形或超共形的第二鈷或鎳膜至第一膜上，第二膜完全填充第二特徵結構。
10‧‧‧基板
12、20‧‧‧特徵結構
14‧‧‧晶種層
16‧‧‧膜
18‧‧‧金屬層/覆蓋層

Claims (30)

  1. 一種電化學製程，用於施用一導電膜至具有一晶種層的一基板上，該製程包含以下步驟：把該基板放入接觸含鈷鹽或鎳鹽的一電化學電鍍浴，且該電鍍浴的pH為6.5至8.3；以及引導一電流通過該浴，以減少該電鍍浴中的鈷離子或鎳離子，並沉積一鈷或鎳的超共形膜至該晶種層上。
  2. 如請求項1所述之製程，其中該晶種層包含銅、鈷、金、銀、鈀及/或釕於該基板上。
  3. 如請求項1所述之製程，其中該電鍍浴包含氯化鈷或其他鈷鹽。
  4. 如請求項1所述之製程，其中該電鍍浴包含甘氨酸或另一螯合劑。
  5. 如請求項1所述之製程，其中該電流為1至50毫安/平方公分。
  6. 如請求項1所述之製程，進一步包含以200℃至450℃的一溫度退火處理該基板。
  7. 如請求項6所述之製程，其中該退火步驟將造成該膜再 流。
  8. 如請求項6所述之製程，其中該退火步驟係在H2/He、N2/H2、一還原氣體、純化H2、或氨的一環境中進行。
  9. 如請求項1所述之製程，其中該電鍍浴進一步包括一螯合劑，該螯合劑與鈷金屬離子錯合。
  10. 如請求項1所述之製程，其中該鈷或鎳沉積至該基板上的次微米內連線中。
  11. 如請求項1所述之製程，其中該電鍍浴包括一螯合劑，該螯合劑選自由檸檬酸、甘氨酸、酒石酸和乙二胺所組成的群組。
  12. 如請求項1所述之製程，其中該晶種層位於該基板的一阻障層上。
  13. 如請求項1所述之製程，其中該基板無阻障層。
  14. 一種電化學製程，用於沉積一導電膜至一基板上的次微米內連線中，其中該基板上具有一晶種層，該製程包含以下步驟：把該基板放入接觸含有選自鈷或鎳的一金屬的一電化學 電鍍浴，且該電鍍浴的pH為6.5至8.3；引導1至50毫安/平方公分的一電流通過該浴至該基板，以沉積一金屬的超共形膜至該基板的特徵結構上；以及將該基板移出該電鍍浴，潤洗並乾燥該基板。
  15. 如請求項14所述之製程，其中該電鍍浴包含氯化鈷。
  16. 如請求項14所述之製程，其中該電鍍浴包含甘氨酸。
  17. 如請求項14所述之製程，進一步包含以200℃至450℃的一溫度退火處理該基板，以使該金屬的超共形膜再流且進一步填充該基板的特徵結構。
  18. 如請求項17所述之製程，進一步包含重複該些步驟至少一次，以提供一多重步驟多次循環的電化學沉積與退火製程。
  19. 一種電化學製程，用於施用一導電膜至一基板上，該基板上包含一晶種層、具一第一尺寸的一第一特徵結構以及具一第二尺寸的一第二特徵結構，該第二尺寸大於該第一尺寸，該製程包含以下步驟：把該基板放入接觸含有鈷鹽或鎳鹽的一電化學電鍍浴，且該電鍍浴的pH為4.0至9.0；執行一電鍍步驟，藉由引導一電流通過該浴，以減少該電鍍浴中的鈷離子或鎳離子，並沉積超共形的一第一鈷或鎳 膜至該晶種層上，其中該第一鈷或鎳膜完全填充該第一特徵結構，但不完全填充該第二特徵結構；以及執行一第二電鍍步驟，藉由引導一電流通過該浴，以減少該電鍍浴中的鈷離子或鎳離子，並沉積超共形的一第二鈷或鎳膜至該第一膜上，其中該第二鈷或鎳膜完全填充該第二特徵結構。
  20. 如請求項19所述之製程，該電鍍浴進一步包括一螯合劑，該螯合劑與鈷金屬離子錯合，並進一步包含以200℃至450℃的一溫度退火處理該基板。
  21. 一種電化學製程，該製程包含以下步驟：把具有一鈷晶種層的一基板放入接觸含有鈷鹽的一電化學電鍍浴，其中該電鍍浴的pH為6.5至8.3；引導一電流通過該浴，以減少該電鍍浴中的鈷離子，並沉積一共形鈷膜至該鈷晶種層上；以及以200℃至450℃的一溫度退火處理該基板。
  22. 如請求項21所述之製程，其中該浴包含甘氨酸。
  23. 如請求項21所述之製程，其中該電流為1至50毫安/平方公分。
  24. 如請求項21所述之製程，其中該退火步驟係在H2/He、 N2/H2、一還原氣體、純化H2、或氨的一環境中進行。
  25. 如請求項21所述之製程，其中該鈷沉積至該鈷晶種層上的次微米特徵結構中，且該退火步驟將造成該共形鈷膜填充該特徵結構，而沒有接縫線缺陷。
  26. 如請求項21所述之製程，其中該鈷晶種層位於該基板的一阻障層上。
  27. 如請求項21所述之製程，其中該基板無阻障層。
  28. 如請求項21所述之製程，其中該電鍍浴不會腐蝕或蝕刻該鈷晶種層。
  29. 如請求項21所述之製程，進一步包含重複該些步驟至少一次，以提供一多重步驟多次循環的電化學沉積與退火製程。
  30. 如請求項29所述之製程，進一步包含電鍍、乾燥及退火該基板至少兩次循環。
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Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106463358B (zh) * 2014-06-16 2020-04-24 英特尔公司 金属互连件的接缝愈合
US9601430B2 (en) * 2014-10-02 2017-03-21 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device structure and method for forming the same
US9777386B2 (en) * 2015-03-19 2017-10-03 Lam Research Corporation Chemistry additives and process for cobalt film electrodeposition
US20160309596A1 (en) * 2015-04-15 2016-10-20 Applied Materials, Inc. Methods for forming cobalt interconnects
US9805976B2 (en) 2016-01-08 2017-10-31 Applied Materials, Inc. Co or Ni and Cu integration for small and large features in integrated circuits
US10438847B2 (en) * 2016-05-13 2019-10-08 Lam Research Corporation Manganese barrier and adhesion layers for cobalt
US10049927B2 (en) * 2016-06-10 2018-08-14 Applied Materials, Inc. Seam-healing method upon supra-atmospheric process in diffusion promoting ambient
US9859215B1 (en) 2016-08-17 2018-01-02 International Business Machines Corporation Formation of advanced interconnects
US9941212B2 (en) 2016-08-17 2018-04-10 International Business Machines Corporation Nitridized ruthenium layer for formation of cobalt interconnects
US9852990B1 (en) 2016-08-17 2017-12-26 International Business Machines Corporation Cobalt first layer advanced metallization for interconnects
US10115670B2 (en) 2016-08-17 2018-10-30 International Business Machines Corporation Formation of advanced interconnects including set of metal conductor structures in patterned dielectric layer
US9716063B1 (en) 2016-08-17 2017-07-25 International Business Machines Corporation Cobalt top layer advanced metallization for interconnects
US10622214B2 (en) 2017-05-25 2020-04-14 Applied Materials, Inc. Tungsten defluorination by high pressure treatment
KR102405723B1 (ko) 2017-08-18 2022-06-07 어플라이드 머티어리얼스, 인코포레이티드 고압 및 고온 어닐링 챔버
US10276411B2 (en) 2017-08-18 2019-04-30 Applied Materials, Inc. High pressure and high temperature anneal chamber
US20210167019A1 (en) * 2017-09-01 2021-06-03 Intel Corporation Metal interconnects, devices, and methods
CN117936417A (zh) 2017-11-11 2024-04-26 微材料有限责任公司 用于高压处理腔室的气体输送系统
WO2019099255A2 (en) 2017-11-17 2019-05-23 Applied Materials, Inc. Condenser system for high pressure processing system
KR20230079236A (ko) 2018-03-09 2023-06-05 어플라이드 머티어리얼스, 인코포레이티드 금속 함유 재료들을 위한 고압 어닐링 프로세스
WO2019179897A1 (en) * 2018-03-20 2019-09-26 Aveni Process for electrodeposition of cobalt
US10950429B2 (en) 2018-05-08 2021-03-16 Applied Materials, Inc. Methods of forming amorphous carbon hard mask layers and hard mask layers formed therefrom
US10748783B2 (en) 2018-07-25 2020-08-18 Applied Materials, Inc. Gas delivery module
WO2020117462A1 (en) 2018-12-07 2020-06-11 Applied Materials, Inc. Semiconductor processing system
KR102605619B1 (ko) 2019-07-17 2023-11-23 삼성전자주식회사 기판 관통 비아들을 포함하는 반도체 소자 및 그 제조 방법
US11901222B2 (en) 2020-02-17 2024-02-13 Applied Materials, Inc. Multi-step process for flowable gap-fill film
KR20230008822A (ko) * 2020-05-08 2023-01-16 램 리써치 코포레이션 코발트, 니켈 및 이의 합금들의 전기 도금

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070105377A1 (en) * 2003-10-20 2007-05-10 Novellus Systems, Inc. Fabrication of semiconductor interconnect structure
CN102260891A (zh) * 2011-07-04 2011-11-30 中国地质大学（武汉） 双脉冲电沉积纳米晶镍钴合金的方法
TW201142986A (en) * 2010-01-07 2011-12-01 Ibm Superfilled metal contact vias for semiconductor devices

Family Cites Families (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2546150A (en) * 1946-11-08 1951-03-27 Brenner Abner Method for securing adhesion of electroplated coatings to a metal base
US6194315B1 (en) * 1999-04-16 2001-02-27 Micron Technology, Inc. Electrochemical cobalt silicide liner for metal contact fills and damascene processes
US7135404B2 (en) * 2002-01-10 2006-11-14 Semitool, Inc. Method for applying metal features onto barrier layers using electrochemical deposition
US6913680B1 (en) 2000-05-02 2005-07-05 Applied Materials, Inc. Method of application of electrical biasing to enhance metal deposition
WO2001090446A2 (en) 2000-05-23 2001-11-29 Applied Materials, Inc. Method and apparatus to overcome anomalies in copper seed layers and to tune for feature size and aspect ratio
US20050006245A1 (en) * 2003-07-08 2005-01-13 Applied Materials, Inc. Multiple-step electrodeposition process for direct copper plating on barrier metals
US20020127847A1 (en) 2000-11-03 2002-09-12 Shipley Company, L.L.C. Electrochemical co-deposition of metals for electronic device manufacture
US6977224B2 (en) 2000-12-28 2005-12-20 Intel Corporation Method of electroless introduction of interconnect structures
JP2003049280A (ja) 2001-06-01 2003-02-21 Ebara Corp 無電解めっき液及び半導体装置
US6717189B2 (en) 2001-06-01 2004-04-06 Ebara Corporation Electroless plating liquid and semiconductor device
US9051641B2 (en) * 2001-07-25 2015-06-09 Applied Materials, Inc. Cobalt deposition on barrier surfaces
US20090004850A1 (en) 2001-07-25 2009-01-01 Seshadri Ganguli Process for forming cobalt and cobalt silicide materials in tungsten contact applications
WO2003017359A1 (en) 2001-08-13 2003-02-27 Ebara Corporation Semiconductor device and production method therefor, and plating solution
US6720263B2 (en) 2001-10-16 2004-04-13 Applied Materials Inc. Planarization of metal layers on a semiconductor wafer through non-contact de-plating and control with endpoint detection
US20030116439A1 (en) * 2001-12-21 2003-06-26 International Business Machines Corporation Method for forming encapsulated metal interconnect structures in semiconductor integrated circuit devices
JP2003328184A (ja) 2002-05-16 2003-11-19 Ebara Corp 微細回路配線形成方法およびこれに用いる装置
US7074721B2 (en) * 2003-04-03 2006-07-11 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming thick copper self-aligned dual damascene
US20050274621A1 (en) * 2004-06-10 2005-12-15 Zhi-Wen Sun Method of barrier layer surface treatment to enable direct copper plating on barrier metal
US20060283716A1 (en) * 2003-07-08 2006-12-21 Hooman Hafezi Method of direct plating of copper on a ruthenium alloy
US7192495B1 (en) * 2003-08-29 2007-03-20 Micron Technology, Inc. Intermediate anneal for metal deposition
US20050067297A1 (en) * 2003-09-26 2005-03-31 Innovative Technology Licensing, Llc Copper bath for electroplating fine circuitry on semiconductor chips
CN1906333A (zh) * 2004-01-29 2007-01-31 应用材料公司 用于抛光衬底的方法和组合物
US20050230262A1 (en) * 2004-04-20 2005-10-20 Semitool, Inc. Electrochemical methods for the formation of protective features on metallized features
CN1965110A (zh) * 2004-06-10 2007-05-16 应用材料公司 能够在阻挡金属上直接镀铜的阻挡层表面处理的方法
US20060035016A1 (en) * 2004-08-11 2006-02-16 Chandra Tiwari Electroless metal deposition methods
US7189650B2 (en) * 2004-11-12 2007-03-13 Taiwan Semiconductor Manufacturing Co., Ltd. Method and apparatus for copper film quality enhancement with two-step deposition
SG124309A1 (en) * 2005-01-25 2006-08-30 Sony Corp A material and uses thereof
TW200641189A (en) 2005-02-25 2006-12-01 Applied Materials Inc Counter electrode encased in cation exchange membrane tube for electroplating cell
WO2006102318A2 (en) 2005-03-18 2006-09-28 Applied Materials, Inc. Electroless deposition process on a contact containing silicon or silicide
US7456102B1 (en) * 2005-10-11 2008-11-25 Novellus Systems, Inc. Electroless copper fill process
TW200746268A (en) * 2006-04-11 2007-12-16 Applied Materials Inc Process for forming cobalt-containing materials
US7794530B2 (en) 2006-12-22 2010-09-14 Lam Research Corporation Electroless deposition of cobalt alloys
US8513124B1 (en) * 2008-03-06 2013-08-20 Novellus Systems, Inc. Copper electroplating process for uniform across wafer deposition and void free filling on semi-noble metal coated wafers
US7928577B2 (en) * 2008-07-16 2011-04-19 Micron Technology, Inc. Interconnect structures for integration of multi-layered integrated circuit devices and methods for forming the same
CN101840883B (zh) * 2009-03-16 2012-01-25 中芯国际集成电路制造(上海)有限公司 铜薄膜形成方法
US20120153483A1 (en) 2010-12-20 2012-06-21 Akolkar Rohan N Barrierless single-phase interconnect
KR101182155B1 (ko) 2011-05-20 2012-09-12 인천대학교 산학협력단 반도체 장치 및 금속박막 형성방법
CN102230200A (zh) * 2011-06-10 2011-11-02 湘潭大学 一种用作锂电池外壳材料的含钴镀镍钢带及其制备方法
US9153449B2 (en) * 2012-03-19 2015-10-06 Lam Research Corporation Electroless gap fill
US10665503B2 (en) 2012-04-26 2020-05-26 Applied Materials, Inc. Semiconductor reflow processing for feature fill
TWI506727B (zh) 2012-05-03 2015-11-01 Nat Univ Chung Hsing Semiconductor components High aspect ratio (HAR) hole or trough of the nickel-tungsten alloy filling plating solution and filling process

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070105377A1 (en) * 2003-10-20 2007-05-10 Novellus Systems, Inc. Fabrication of semiconductor interconnect structure
TW201142986A (en) * 2010-01-07 2011-12-01 Ibm Superfilled metal contact vias for semiconductor devices
CN102260891A (zh) * 2011-07-04 2011-11-30 中国地质大学（武汉） 双脉冲电沉积纳米晶镍钴合金的方法

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