TWI587486B - 半導體裝置與其製造方法以及靜態隨機存取記憶體 - Google Patents

半導體裝置與其製造方法以及靜態隨機存取記憶體 Download PDF

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TWI587486B
TWI587486B TW105103805A TW105103805A TWI587486B TW I587486 B TWI587486 B TW I587486B TW 105103805 A TW105103805 A TW 105103805A TW 105103805 A TW105103805 A TW 105103805A TW I587486 B TWI587486 B TW I587486B
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semiconductor
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李宜靜
郭紫微
游明華
李昆穆
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台灣積體電路製造股份有限公司
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Description

半導體裝置與其製造方法以及靜態隨機存取記憶體
本揭露係關於一種半導體裝置。
靜態隨機存取記憶體(Static Random Access Memory；Static RAM或SRAM)為半導體記憶體，此記憶體只要通電即可以靜態形式保存資料。靜態隨機存取記憶體與較常見的動態隨機存取記憶體(dynamic RAM；DRAM)相比更快且更可靠。術語靜態係衍生自其無需如動態隨機存取記憶體一般刷新之事實。靜態隨機存取記憶體用於電腦之快取記憶體且用作視訊卡上之隨機存取記憶體數位類比轉換器的一部分。
根據一些實施方式，半導體裝置包含基板、第一半導體鰭、第二半導體鰭、n型磊晶結構、p型磊晶結構 及複數個介電鰭側壁結構。第一半導體鰭置於基板上。第二半導體鰭置於基板上且毗鄰第一半導體鰭。n型磊晶結構置於第一半導體鰭上。p型磊晶結構置於第二半導體鰭上且與n型磊晶結構分離。介電鰭側壁結構置於至少一個n型磊晶結構及p型磊晶結構之相對側面上。
根據一些實施方式，靜態隨機存取記憶體單元包含兩個上拉電晶體、兩個通閘電晶體及兩個下拉電晶體。上拉電晶體及下拉電晶體形成兩個交叉耦接的轉換器。通閘電晶體電性連接至交叉耦接轉換器。至少一之上拉電晶體、通閘電晶體及下拉電晶體包含半導體鰭、磊晶結構及複數個介電鰭側壁結構。半導體鰭包含至少一凹陷部分及至少一通道部分。磊晶結構置於半導體鰭之凹陷部分上。介電鰭側壁結構置於磊晶結構之相對側面上。
根據一些實施方式，用於製造半導體裝置之方法包含形成第一半導體鰭及第二半導體鰭在基板上。第一半導體鰭毗鄰第二半導體鰭。至少在第一半導體鰭之相對側面上形成複數個介電鰭側壁結構。降低第一半導體鰭。形成第一磊晶結構在降低之第一半導體鰭上。降低第二半導體鰭。形成第二磊晶結構在降低之第二半導體鰭上。第一磊晶結構及第二磊晶結構具有不同類型。
根據上述實施方式，由於介電鰭側壁結構置於至少一個半導體鰭之相對側面上，因此磊晶結構之形成可藉由介電鰭側壁結構來調整。更詳細地說，磊晶結構之磊晶生長縱向及橫向延伸。橫向磊晶生長將擴大磊晶結構之尺寸且 使其間的間隔變窄。然而，介電鰭側壁結構可抑制磊晶結構之橫向磊晶生長，以使得其間的空間可減小以預防磊晶結構合併在一起。因此，可改良靜態隨機存取記憶體裝置之效能。
100、200a、200b、200c、200d‧‧‧靜態隨機存取記憶體單元
102‧‧‧第一轉換器
103、105‧‧‧儲存結點
104‧‧‧第二轉換器
210‧‧‧基板
212‧‧‧p阱區域
216‧‧‧n阱區域
222、224、226、228‧‧‧半導體鰭
222c、224c‧‧‧通道部分
222r、224r‧‧‧凹陷部分
230‧‧‧隔離結構
240a‧‧‧閘極絕緣體層
240b‧‧‧閘電極層
242、244、246、248‧‧‧閘極堆疊
250‧‧‧閘極間隔層
260‧‧‧介電鰭側壁結構
272、276‧‧‧磊晶結構
272a、276a‧‧‧頂部分
272b、276b‧‧‧主體部分
B‧‧‧區域
BL‧‧‧第一位元線
BLB‧‧‧第二位元線
PG-1‧‧‧第一通閘電晶體
PG-2‧‧‧第二通閘電晶體
PU-1、PU-2‧‧‧上拉電晶體
PD-1、PD-2‧‧‧下拉電晶體
R‧‧‧凹陷
Vdd‧‧‧電壓匯流排
Vss‧‧‧接地電位
W1、W2、W3、W4、W5、W6‧‧‧寬度
WL‧‧‧字線
當結合隨附圖式閱讀時，自以下詳細描述將很好地理解本揭露之態樣。應注意，根據工業中之標準實務，各特徵結構並非按比例繪製。事實上，出於論述清晰之目的，可任意增加或減小各特徵結構之尺寸。
第1圖為六電晶體靜態隨機存取記憶體單元之電路圖。
第2A圖至第6A圖為根據本揭露之一些實施方式在各階段之用於製造靜態隨機存取記憶體裝置的方法之俯視圖。
第2B圖至第6B圖為第2A圖至第6A圖之區域B之透視圖。
以下揭示內容提供許多不同實施方式或範例，以用於實施所提供目標之不同特徵結構。下文描述組件及排列之特定範例以簡化本揭露。當然，此等範例僅為示例且並不意欲為限制性。舉例而言，以下描述中在第二特徵結構上方或第二特徵結構上形成第一特徵結構可包含以直接接觸形成第一特徵結構及第二特徵結構的實施方式，且亦可包含可在第一特徵結構與第二特徵結構之間形成額外特徵結構以使得第一特徵結構及第二特徵結構可不直接接觸的實施 方式。另外，本揭露可在各種範例中重複組件符號及/或字母。此重複係出於簡明性及清晰之目的，且本身並不指示所論述之各實施方式及/或配置之間的關係。
進一步地，為了便於描述，本文可使用空間相對性術語(諸如「之下」、「下方」、「下部」、「上方」、「上部」及類似者)來描述圖式中所說明之一個部件或特徵結構與另一部件(或多個部件)或特徵結構(或多個特徵結構)之關係。除了諸圖所描繪之定向外，空間相對性術語意欲包含在使用或操作中的裝置之不同定向。設備可經其他方式定向(旋轉90度或處於其他定向)且因此可同樣地解讀本文所使用之空間相對性描述詞。
將結合特定上下文中之實施方式描述本揭露，即由鰭式場效電晶體(fin field effect transistor；FinFET)形成之靜態隨機存取記憶體(SRAM)。然而，本揭露之實施方式亦可應用至多種半導體裝置。各實施方式將結合隨附圖式詳細地說明。
靜態隨機存取記憶體(SRAM)為一種揮發性半導體記憶體，其使用雙穩定鎖存電路(bistable latching circuitry)以儲存各位元。靜態隨機存取記憶體中之各位元均儲存在形成兩個交叉耦接轉換器之四個電晶體(PU-1、PU-2、PD-1及PD-2)上。此記憶體單元具有兩個穩態，其用於指示0及1。兩個額外的存取電晶體(PG-1及PG-2)電性連接至兩個交叉耦接轉換器且用以在讀取及寫入操作期間控制對儲存單元之存取。
第1圖為六電晶體(six transistors；6T)靜態隨機存取記憶體單元之電路圖。靜態隨機存取記憶體單元100包含由上拉電晶體PU-1及下拉電晶體PD-1形成之第一轉換器102。靜態隨機存取記憶體單元100更包含由上拉電晶體PU-2及下拉電晶體PD-2形成之第二轉換器104。此外，在電壓匯流排Vdd與接地電位Vss之間耦接第一轉換器102與第二轉換器104兩者。在一些實施方式中，上拉電晶體PU-1及PU-2可為p型電晶體，而下拉電晶體PD-1及PD-2可為n型電晶體，且本揭露之所主張範圍不限於此方面。
在第1圖中，第一轉換器102與第二轉換器104交叉耦接。亦即，第一轉換器102之輸入端連接至第二轉換器104之輸出端。同樣地，第二轉換器104之輸入端連接至第一轉換器102之輸出端。第一轉換器102之輸出端稱為儲存結點103。同樣地，第二轉換器104之輸出端稱為儲存結點105。在正常操作模式中，儲存結點103與儲存結點105處於相反邏輯態。藉由使用兩個交叉耦接轉換器，靜態隨機存取記憶體單元100可使用鎖存結構保留資料，以使得只要經由電壓匯流排Vdd供應電力即可使儲存的資料在不應用刷新循環的情況下不丟失。
在使用6T靜態隨機存取記憶體單元的靜態隨機存取記憶體裝置中，單元以列及行排列。靜態隨機存取記憶體陣列之行係藉由位元線對形成，即第一位元線BL與第二位元線BLB。靜態隨機存取記憶體裝置之單元置於各別 位元線對之間。如第1圖中所示，靜態隨機存取記憶體單元100置放在位元線BL與位元線BLB之間。
在第1圖中，靜態隨機存取記憶體單元100更包含連接在位元線BL與第一轉換器102之輸出端103之間的第一通閘電晶體PG-1。靜態隨機存取記憶體單元100更包含連接在位元線BLB與第二轉換器104之輸出端105之間的第二通閘電晶體PG-2。第一通閘電晶體PG-1及第二通閘電晶體PG-2之閘極連接至字線WL，字線WL將靜態隨機存取記憶體單元連接在靜態隨機存取記憶體陣列之列中。
在操作中，若通閘電晶體PG-1及PG-2為非主動，則只要經由電壓匯流排Vdd提供電力，靜態隨機存取記憶體單元100即將無限期地維持儲存結點103及105處之互補值。此係由於交叉耦接轉換器對之各轉換器驅動另一者之輸入，從而維持儲存結點處之電壓。此情形將維持穩定，直至自靜態隨機存取記憶體移除電力，或執行寫入循環，改變儲存結點處之儲存的資料。
在第1圖之電路圖中，上拉電晶體PU-1、PU-2為p型電晶體。下拉電晶體PD-1、PD-2及通閘電晶體PG-1、PG-2為n型電晶體。根據各實施方式，上拉電晶體PU-1、PU-2、下拉電晶體PD-1、PD-2及通閘電晶體PG-1、PG-2係由FinFET實施。
第1圖中之靜態隨機存取記憶體單元100之結構在6T-SRAM之上下文中描述。然而，一般技術者應理解本文所描述之各實施方式之特徵結構可用於形成其他類型 之裝置，諸如8T-SRAM記憶體裝置，或不同於靜態隨機存取記憶體之記憶體裝置，諸如標準單元、閘極二極體或ESD(靜電放電(Electrostatic Discharge))裝置。此外，本揭露之實施方式可用作獨立的記憶體裝置、與其他整合電路整合之記憶體裝置或其類似者。
第2A圖至第6A圖為根據本揭露之一些實施方式在各階段之用於製造靜態隨機存取記憶體裝置的方法之俯視圖，且第2B圖至第6B圖為第2A圖至第6A圖之區域B之透視圖。在第2A圖至第6A圖中，說明包含四個靜態隨機存取記憶體單元200a、200b、200c及200d之靜態隨機存取記憶體裝置。然而，在一些其他實施方式中，靜態隨機存取記憶體裝置中之靜態隨機存取記憶體單元200a、200b、200c及200d之數目不限制於此方面。參考第2A圖及第2B圖。提供基板210。在一些實施方式中，例如，基板210可為半導體材料，且可包含已知結構，包含分級層或內埋式氧化物。在一些實施方式中，基板210包含可為未摻雜或摻雜之塊體矽(例如，p型、n型或其組合)。可使用其他適合於半導體裝置形成之材料。其他材料，諸如鍺、石英、藍寶石及玻璃可替代地用於基板210。或者，矽基板210可為絕緣體上半導體(semiconductor-on-insulator；SOI)基板之活性層，或多層結構，諸如形成於塊體矽層上之矽-鍺層。
複數個p阱區域212及複數個n阱區域216形成在基板210中。一個n阱區域216形成在兩個p阱區域212之間。p阱區域212用P摻雜材料(諸如硼離子)植入，且n阱區 域216用N摻雜材料(諸如砷離子)植入。在植入p阱區域212期間，n阱區域216由遮罩(諸如光阻劑)覆蓋，且在植入n阱區域216期間，p阱區域212由遮罩(諸如光阻劑)覆蓋。
複數個半導體鰭222、224、226及228形成於基板210上。更詳細地說，半導體鰭222及226形成於p阱區域212上，且半導體鰭224及228形成於n阱區域216上。半導體鰭222毗鄰半導體鰭224，且半導體鰭226毗鄰半導體鰭228。在一些實施方式中，半導體鰭222、224、226及228包含矽。應注意，第2A圖中之半導體鰭222、224、226及228之數目為說明性，且不應限制本揭露之所主張的範圍。一般技術者可根據實際情形選擇半導體鰭222、224、226及228之適宜的數目。
半導體鰭222、224、226及228可例如藉由使用微影技術圖案化及蝕刻基板210來形成。在一些實施方式中，光阻劑材料層(未圖示)沉積在基板210之上。根據所要圖案(在此情況下，半導體鰭222、224、226及228)照射光阻劑材料層且使其顯影以移除光阻劑材料部分。剩餘光阻劑材料保護底層材料免受後續處理步驟(諸如蝕刻)影響。應注意，其他遮罩(諸如氧化物或氮化矽遮罩)亦可用於蝕刻製程。
參考第3A圖及第3B圖。移除部分之半導體鰭224及228。舉例而言，含有用於半導體鰭224與228兩者之圖案的光罩(未圖示)用於保護半導體鰭224及228待保留的部分。隨後同時蝕刻半導體鰭224與228兩者之曝露部分。
隨後，複數個隔離結構230形成於基板210上。充當圍繞半導體鰭222、224、226及228之淺溝槽隔離(shallow trench isolation；STI)之隔離結構230可藉由化學氣相沉積(chemical vapor deposition；CVD)技術使用正矽酸四乙酯(tetra-ethyl-ortho-silicate；TEOS)及氧作為前驅物來形成。在一些其他實施方式中，隔離結構230可藉由將離子(諸如氧、氮、碳或其類似者)植入至基板210中來形成。在又一些其他實施方式中，隔離結構230為SOI晶圓之絕緣體層。
參考第4A圖及第4B圖。複數個閘極堆疊242、244、246及248形成於半導體鰭222、224、226及228之部分上，且曝露半導體鰭222、224、226及228之另一部分。更詳細地說，閘極堆疊242形成於半導體鰭222、224之部分上，且在一些實施方式中更形成於半導體鰭228之部分上；閘極堆疊244形成於半導體鰭226及228之部分上，且在一些實施方式中更形成於半導體鰭224之部分上；閘極堆疊246形成於半導體鰭222之部分上，且閘極堆疊248形成於半導體鰭226之部分上。
如第4B圖中所示，閘極堆疊242、244、246及248中之至少一者包含閘極絕緣體層240a及閘電極層240b。閘極絕緣體層240a置於閘電極層240b與基板210之間，且形成於半導體鰭222、224、226及228上。防止電子空乏之閘極絕緣體層240a可包含例如高k介電材料，諸如金屬氧化物、金屬氮化物、金屬矽酸鹽、過渡金屬氧化物、過 渡金屬氮化物、過渡金屬矽酸鹽、金屬之氮氧化物、金屬鋁酸鹽、矽酸鋯、鋁酸鋯或其組合。一些實施方式可包含氧化鉿(HfO2)、氧化鉿矽(HfSiO)、氮氧化鉿矽(HfSiON)、氧化鉿鉭(HfTaO)、氧化鉿鈦(HfTiO)、氧化鉿鋯(HfZrO)、氧化鑭(LaO)、氧化鋯(ZrO)、氧化鈦(TiO)、氧化鉭(Ta2O5)、氧化釔(Y2O3)、氧化鍶鈦(SrTiO3、STO)、氧化鋇鈦(BaTiO3、BTO)、氧化鋯鋇(BaZrO)、氧化鉿鑭(HfLaO)、氧化鑭矽(LaSiO)、氧化鋁矽(AlSiO)、氧化鋁(Al2O3)、氮化矽(Si3N4)、氮氧化物(SiON)及其組合。閘極絕緣體層240a可具有多層結構，諸如一個氧化矽層(例如，界面層)及另一個高k材料層。
閘極絕緣體層240b可使用化學氣相沉積(chemical vapor deposition；CVD)、物理氣相沉積(physical vapor deposition；PVD)、原子層沉積(atomic layer deposition；ALD)、熱氧化、臭氧氧化、其他適宜的製程或其組合來形成。閘電極層240b形成於基板210之上以覆蓋閘極絕緣體層240a及部分之半導體鰭222、224、226及228。在一些實施方式中，閘電極層240b包含半導體材料，諸如多晶矽、非晶矽或其類似者。閘電極層240b可在經摻雜或未經摻雜的情況下沉積。舉例而言，在一些實施方式中，閘電極層240b包含藉由低壓化學氣相沉積(low-pressure chemical vapor deposition；LPCVD)在未經摻雜的情況下沉積的多晶矽。多晶矽亦可例如藉由原位摻雜多晶矽之爐沉積來沉積。或者，閘電極層240b可包含 多晶矽金屬合金或包含諸如鎢(W)、鎳(Ni)、鋁(Al)、鉭(Ta)、鈦(Ti)或其任何組合之金屬的任何金屬閘極。
在第4B圖中，複數個閘極間隔層250在基板210之上且沿著閘極堆疊242、244、246及248之側面形成。出於清晰之目的，閘極間隔層250繪示於第4B圖中且在第4A圖中省略。在一些實施方式中，閘極間隔層250可包含氧化矽、氮化矽、氮氧化矽或其他適宜的材料。閘極間隔層250可包含單層或多層結構。閘極間隔層250之毯覆層可藉由CVD、PVD、ALD或其他適宜的技術形成。隨後，對毯覆層執行非等向性蝕刻以在閘極堆疊242、244、246及248之兩個側面上形成一對閘極間隔層250。在一些實施方式中，閘極間隔層250用於抵消隨後形成之摻雜區域，諸如源極/汲極區域。閘極間隔層250可進一步用於設計或改變源極/汲極區域(接合面)輪廓。
複數個介電鰭側壁結構260形成於半導體鰭222、224、226及228之相對側面上。介電鰭側壁結構260係沿著半導體鰭222、224、226及228形成。介電鰭側壁結構260可包含介電材料，諸如氧化矽。或者，介電鰭側壁結構260可包含氮化矽、碳化矽(SiC)、氮氧化矽(SiON)或其組合。用於介電鰭側壁結構260之形成方法可包含在半導體鰭222、224、226及228之上沉積介電材料，且隨後非等向性地反向蝕刻介電材料。反向蝕刻製程可包含多步驟蝕刻以獲得蝕刻選擇性、靈活性及所要過度蝕刻控制。
在一些實施方式中，閘極間隔層250及介電鰭側壁結構260可在相同製造製程中形成。舉例而言，可藉由CVD、PVD、ALD或其他適宜的技術形成介電質層之毯覆層以覆蓋閘極堆疊242、244、246及248以及半導體鰭222、224、226及228。隨後，對毯覆層執行蝕刻製程以在閘極堆疊242、244、246及248之相對側面上形成閘極間隔層250，且在半導體鰭222、224、226及228之相對側面上形成介電鰭側壁結構260。然而，在一些其他實施方式中，閘極間隔層250及介電鰭側壁結構260可在不同製造製程中形成。
在第4A圖中，半導體鰭222及閘極堆疊242形成下拉電晶體PD-1，且半導體鰭224及閘極堆疊242形成上拉電晶體PU-1。換言之，下拉電晶體PD-1及上拉電晶體PU-1共享閘極堆疊242。半導體鰭226及閘極堆疊244形成另一下拉電晶體PD-2，且半導體鰭228及閘極堆疊244形成另一上拉電晶體PU-2。換言之，下拉電晶體PD-2及上拉電晶體PU-2共享閘極堆疊244。此外，半導體鰭222及閘極堆疊246形成通閘電晶體PG-1。換言之，通閘電晶體PG-1及下拉電晶體PD-1共享半導體鰭222。半導體鰭226及閘極堆疊248形成另一通閘電晶體PG-2。換言之，通閘電晶體PG-2及下拉電晶體PD-2共享半導體鰭226。因此，靜態隨機存取記憶體單元200a為六電晶體(6T)靜態隨機存取記憶體。然而，一般技術者應理解本文所描述之各實施方式之特徵結 構可用於形成其他類型之裝置，諸如8T靜態隨機存取記憶體裝置。
在一些實施方式中，半導體鰭222之數目可為複數個，且/或半導體鰭226之數目可為複數個。因此，下拉電晶體PD-1、PD-2及通閘電晶體PG-1、PG-2每個電晶體具有複數個半導體鰭，且上拉電晶體PU-1及PU-2每個電晶體具有一個半導體鰭，然而所主張的範圍不限於此。
在第4A圖中，當靜態隨機存取記憶體單元200a至200d排列在一起以形成陣列(係本文中之靜態隨機存取記憶體裝置)時，單元佈局可經翻轉或旋轉以允許較高的封裝密度。通常，藉由沿著單元邊界或軸線將單元翻轉及將經翻轉之單元鄰近原始單元置放，可將常見結點及連接組合以增加封裝密度。舉例而言，靜態隨機存取記憶體單元200a至200d彼此為鏡像且為旋轉影像。特定言之，靜態隨機存取記憶體單元200a及200b沿著Y軸呈鏡像，靜態隨機存取記憶體單元200c及200d亦為如此。靜態隨機存取記憶體單元200a及200c沿著X軸呈鏡像，靜態隨機存取記憶體單元200b及200d亦為如此。此外，對角線靜態隨機存取記憶體單元(靜態隨機存取記憶體單元200a及200d；靜態隨機存取記憶體單元200b及200c)為彼此之180度旋轉影像。
參考第5A圖及第5B圖。被閘極堆疊242、244、246及248與閘極間隔層250曝露之部分半導體鰭222、224、226及228被移除(或被部分降低)以在半導體鰭222、224、226及228中形成凹陷R。在第5A圖及第5B圖中，凹 陷R形成為以介電鰭側壁結構260作為其上部。在一些實施方式中，凹陷R之側壁彼此實質且垂直平行。在一些其他實施方式中，凹陷R以非垂直平行輪廓形成。
在第5B圖中，半導體鰭222包含至少一個凹陷部分222r及至少一個通道部分222c。凹陷R形成於凹陷部分222r上，且閘極堆疊242覆蓋通道部分222c。半導體鰭224包含至少一個凹陷部分224r及至少一個通道部分224c。凹陷R形成於凹陷部分224r上，且閘極堆疊242覆蓋通道部分224c。此外，半導體鰭226及228(參看第4A圖)個別地包含至少一個凹陷部分及至少一個通道部分(未圖示)。由於半導體鰭226及228之凹陷部分及通道部分與凹陷部分222r及224r及通道部分222c及224c具有類似配置，因此，下文將不再重複關於此點之描述。
至少一介電鰭側壁結構260具有高度H1，且至少一半導體鰭222、224、226及228具有自隔離結構230(亦即，通道部分222c、224c)突出之高度H2。高度H1低於高度H2。在一些實施方式中，高度H1及高度H2滿足以下條件：0.1≦(H1/H2)≦0.5，然而所主張之範圍不限於此。介電鰭側壁結構260之高度H1可例如藉由蝕刻調整以調節形成於其上之磊晶結構272及276(參看第6A圖及第6B圖)之輪廓。
移除製程可包含乾式蝕刻製程、濕式蝕刻製程及/或其組合。移除製程亦可包含選擇性濕式蝕刻或選擇性乾式蝕刻。濕式蝕刻溶液包含氫氧化四甲銨 (tetramethylammonium hydroxide；TMAH)、氫氟酸/硝酸/醋酸(HF/HNO3/CH3COOH)溶液或其他適宜的溶液。乾式及濕式蝕刻製程具有可調整之蝕刻參數，諸如所用之蝕刻劑、蝕刻溫度、蝕刻溶液濃度、蝕刻壓力、電源、RF偏壓電壓、RF偏壓功率、蝕刻劑流動速率及其他適宜的參數。舉例而言，濕式蝕刻溶液可包含氫氧化銨(NH4OH)、氫氧化鉀(KOH)、氫氟酸(HF)、氫氧化四甲銨(TMAH)、其他適宜的濕式蝕刻溶液或其組合。乾式蝕刻製程包含使用基於氯之化學物質的偏壓電漿蝕刻製程。其他乾式蝕刻劑氣體包含四氟化碳(CF4)、三氟化氮(NF3)、六氟化硫(SF6)及氦氣(He)。乾式蝕刻亦可使用諸如深度反應性離子蝕刻(DRIE)之機制來非等向性地執行。
參考第6A圖及第6B圖。複數個磊晶結構272分別形成於半導體鰭222及226之凹陷R中(參看第4A圖)，且複數個磊晶結構276分別形成於半導體鰭224及228之凹陷R中(參看第4A圖)。磊晶結構272與鄰近的磊晶結構276分離。磊晶結構272及276自凹陷R突出。磊晶結構272可為n型磊晶結構，且磊晶結構276可為p型磊晶結構。磊晶結構272及276可使用一個或更多個磊晶或磊晶(epi)製程形成，以使得Si特徵結構、SiGe特徵結構及/或其他適宜的特徵結構可以結晶態形成於半導體鰭222、224、226及228上。在一些實施方式中，磊晶結構272及276之晶格常數不同於半導體鰭222、224、226及228之晶格常數，且磊晶結構272及276經拉伸或加壓以允許靜態隨機存取記憶體裝置 之載流子遷移率且增強裝置效能。磊晶結構272及276可包含半導體材料，諸如鍺(Ge)或矽(Si)；或化合物半導體材料，諸如砷化鎵(GaAs)、砷化鋁鎵(AlGaAs)、矽鍺(SiGe)、碳化矽(SiC)或砷化鎵磷化物(GaAsP)。
在一些實施方式中，磊晶結構272及276在不同磊晶製程中形成。磊晶結構272可包含磷化矽(SiP)、碳化矽(SiC)、磷碳矽化合物(SiPC)、矽(Si)、III-V族化合物半導體材料或其組合，且磊晶結構276可包含鍺化矽(SiGe)、碳鍺矽化合物(SiGeC)、鍺(Ge)、矽(Si)、III-V族化合物半導體材料或其組合。在磊晶結構272形成期間，可隨著磊晶之進行摻雜n型雜質(諸如磷或砷)。舉例而言，當磊晶結構272包含碳化矽或矽時，摻雜n型雜質。此外，在磊晶結構276形成期間，可隨著磊晶之進行摻雜p型雜質(諸如硼或氟化硼(BF2))。舉例而言，當磊晶結構276包含鍺化矽時，摻雜p型雜質。磊晶製程包含CVD沉積技術(例如，氣相磊晶(vapor-phase epitaxy；VPE)及/或超高真空CVD(ultra-high vacuumCVD；UHV-CVD))、分子束磊晶及/或其他適宜的製程。磊晶製程可使用氣體及/或液體前驅物，其與半導體鰭222、224、226及228之組成物(例如，矽)相互作用。因此，可實現拉伸通道以增加載流子遷移率且增強裝置效能。磊晶結構272及276可原位摻雜。若磊晶結構272及276未原位摻雜，則執行第二植入製程(亦即，接合面植入製程)以摻雜磊晶結構272及276。可執行一個或更多個退火製程以激活磊晶結構272及276。退火製程包含快 速熱退火(rapid thermal annealing；IRTA)及/或雷射退火製程。
在一些實施方式中，磊晶結構272具有頂部分272a及置於頂部分272a與基板210之間的主體部分272b。頂部分272a具有寬度W1，且主體部分270b具有比寬度W1小之寬度W2。至少一個半導體鰭222及226具有實質與寬度W2相同的寬度W3。介電鰭側壁結構260置於磊晶結構272之主體部分272b之相對側面上，且磊晶結構272之頂部分272a置於介電鰭側壁結構260上。
此外，磊晶結構276具有頂部分276a及置於頂部分276a與基板210之間的主體部分276b。頂部分276a具有寬度W4，且主體部分276b具有比寬度W4小之寬度W5。至少一個半導體鰭222及226具有實質與寬度W5相同的寬度W6。介電鰭側壁結構260置於磊晶結構276之主體部分276b之相對側面上，且磊晶結構276之頂部分276a置於介電鰭側壁結構260上。
在一些實施方式中，磊晶結構272及276具有不同形狀。磊晶結構272之頂部分272a可具有至少一個存在於介電鰭側壁結構260上方之實質為刻面(facet)的表面，且磊晶結構276之頂部分276a可具有至少一個存在於介電鰭側壁結構260上方之非刻面的(或圓形)表面，然而所主張之範圍不限於此。
在第6A圖中，半導體鰭222(參看第4A圖)、形成於其上之磊晶結構272、形成於磊晶結構272之相對側面 上的介電鰭側壁結構260與閘極堆疊242一起形成下拉電晶體PD-1，其中半導體鰭222及磊晶結構272作為下拉電晶體PD-1之源極/汲極。半導體鰭224(參看第4A圖)、形成於其上之磊晶結構276、形成於磊晶結構276之相對側面上的介電鰭側壁結構260與閘極堆疊242一起形成上拉電晶體PU-1，其中半導體鰭224及磊晶結構276作為上拉電晶體PU-1之源極/汲極。半導體鰭226(參看第4A圖)、形成於其上之磊晶結構272、形成於磊晶結構272之相對側面上的介電鰭側壁結構260與閘極堆疊244一起形成下拉電晶體PD-2，其中半導體鰭226及磊晶結構272作為下拉電晶體PD-2之源極/汲極。半導體鰭228(參看第4A圖)、形成於其上之磊晶結構276、形成於磊晶結構276之相對側面上的介電鰭側壁結構260與閘極堆疊244一起形成上拉電晶體PU-2，其中半導體鰭228及磊晶結構276作為上拉電晶體PU-2之源極/汲極。半導體鰭222、形成於其上之磊晶結構272、形成於磊晶結構272之相對側面上的介電鰭側壁結構260與閘極堆疊246一起形成通閘電晶體PG-1，其中半導體鰭222及磊晶結構272作為通閘電晶體PG-1之源極/汲極。半導體鰭226、形成於其上之磊晶結構272、形成於磊晶結構272之相對側面上的介電鰭側壁結構260與閘極堆疊248一起形成通閘電晶體PG-2，其中半導體鰭226及磊晶結構272作為通閘電晶體PG-2之源極/汲極。因此，靜態隨機存取記憶體單元200a為六電晶體(6T)靜態隨機存取記憶體。然而，一般技術者應理解本文所描述之各實施方式之特徵結 構可用於形成其他類型之裝置，諸如8T靜態隨機存取記憶體裝置。
根據前述實施方式，由於介電鰭側壁結構置於至少一個半導體鰭之相對側面上，因此磊晶結構之形成可藉由介電鰭側壁結構來調整。更詳細地說，磊晶結構之磊晶生長縱向及橫向延伸。橫向磊晶生長將擴大磊晶結構之尺寸且使其間的間隔變窄。然而，介電鰭側壁結構可抑制磊晶結構之橫向磊晶生長，以使得其間的空間可減小以預防磊晶結構合併在一起。因此，可改良靜態隨機存取記憶體裝置之效能。
根據一些實施方式，半導體裝置包含基板、第一半導體鰭、第二半導體鰭、n型磊晶結構、p型磊晶結構及複數個介電鰭側壁結構。第一半導體鰭置於基板上。第二半導體鰭置於基板上且毗鄰第一半導體鰭。n型磊晶結構置於第一半導體鰭上。p型磊晶結構置於第二半導體鰭上且與n型磊晶結構分離。介電鰭側壁結構置於至少一個n型磊晶結構及p型磊晶結構之相對側面上。
根據一些實施方式，靜態隨機存取記憶體單元包含兩個上拉電晶體、兩個通閘電晶體及兩個下拉電晶體。上拉電晶體及下拉電晶體形成兩個交叉耦接的轉換器。通閘電晶體電性連接至交叉耦接轉換器。至少一之上拉電晶體、通閘電晶體及下拉電晶體包含半導體鰭、磊晶結構及複數個介電鰭側壁結構。半導體鰭包含至少一凹陷部分及至少一通道部分。磊晶結構置於半導體鰭之凹陷部分上。介電鰭側壁結構置於磊晶結構之相對側面上。
根據一些實施方式，用於製造半導體裝置之方法包含形成第一半導體鰭及第二半導體鰭在基板上。第一半導體鰭毗鄰第二半導體鰭。至少在第一半導體鰭之相對側面上形成複數個介電鰭側壁結構。降低第一半導體鰭。形成第一磊晶結構在降低之第一半導體鰭上。降低第二半導體鰭。形成第二磊晶結構在降低之第二半導體鰭上。第一磊晶結構及第二磊晶結構具有不同類型。
上文概述若干實施方式之特徵結構，使得熟習此項技術者可更好地理解本揭露之態樣。熟習此項技術者應瞭解，可輕易使用本揭露作為設計或修改其他製程及結構的基礎，以便實施本文所介紹之實施方式的相同目的及/或實現相同優勢。熟習此項技術者亦應認識到，此類等效結構並未脫離本揭露之精神及範疇，且可在不脫離本揭露之精神及範疇的情況下做出對本揭露的各種變化、替代及更改。
210‧‧‧基板
212‧‧‧p阱區域
216‧‧‧n阱區域
222、224‧‧‧半導體鰭
230‧‧‧隔離結構
240a‧‧‧閘極絕緣體層
240b‧‧‧閘電極層
242‧‧‧閘極堆疊
250‧‧‧閘極間隔層
260‧‧‧介電鰭側壁結構
272、276‧‧‧磊晶結構
272a、276a‧‧‧頂部分
272b、276b‧‧‧主體部分
R‧‧‧凹陷
W1、W2、W3、W4、W5、W6‧‧‧寬度

Claims (8)

  1. 一種半導體裝置，包含：一基板；一第一半導體鰭，置於該基板上，其中該第一半導體鰭具有一第三寬度；一第二半導體鰭，置於該基板上且毗鄰該第一半導體鰭；一n型磊晶結構，置在該第一半導體鰭上，且該n型磊晶結構包含：一頂部分，具有一第一寬度；以及一主體部分，置於該頂部分與該第一半導體鰭之間且具有比該第一寬度小之一第二寬度，且該第二寬度與該第三寬度實質相同；一p型磊晶結構，置於該第二半導體鰭上且與該n型磊晶結構分離；以及複數個介電鰭側壁結構，置於至少一之該n型磊晶結構與該p型磊晶結構之相對側面上。
  2. 如請求項1所述之半導體裝置，其中該些介電鰭側壁結構置於該n型磊晶結構之該主體部分之相對側面上，且該n型磊晶結構之該頂部分置於該些介電鰭側壁結構上。
  3. 如請求項1所述之半導體裝置，其中該些介電鰭側壁結構置於該p型磊晶結構之該些相對側面上，且該p型磊晶結構包含：一頂部分，具有一第四寬度；以及一主體部分，置於該頂部分與該第二半導體鰭之間且具有比該第四寬度小之一第五寬度，其中該些介電鰭側壁結構置於該p型磊晶結構之該主體部分之相對側面上，且該p型磊晶結構之該頂部分置於該些介電鰭側壁結構上。
  4. 如請求項3所述之半導體裝置，其中該第二半導體鰭具有一第六寬度，該第六寬度與該p型磊晶結構之該主體部分之該第五寬度實質相同。
  5. 一種靜態隨機存取記憶體單元，包含：兩個上拉電晶體、兩個通閘電晶體及兩個下拉電晶體，其中該些上拉電晶體及該些下拉電晶體形成兩個交叉耦接轉換器，該些通閘電晶體電性連接至該些交叉耦接轉換器，且該些上拉電晶體、該些通閘電晶體及該些下拉電晶體中至少一者包含：一半導體鰭，包含至少一凹陷部分及至少一通道部分，其中該半導體鰭具有一第三寬度；一磊晶結構，置於該半導體鰭之該凹陷部分上，且該磊晶結構包含：一頂部分，具有一第一寬度；以及 一主體部分，置於該頂部分與該半導體鰭之間且具有比該第一寬度小之一第二寬度，其中該第二寬度與該第三寬度實質相同；以及複數個介電鰭側壁結構，置於該磊晶結構之相對側面上。
  6. 如請求項5所述之靜態隨機存取記憶體單元，其中該些介電鰭側壁結構置於該磊晶結構之該主體部分之相對側面上，且該磊晶結構之該頂部分置於該些介電鰭側壁結構上。
  7. 一種用於製造一半導體裝置之方法，包含：形成一第一半導體鰭及一第二半導體鰭在一基板上，其中該第一半導體鰭毗鄰該第二半導體鰭，且該第一半導體鰭具有一第三寬度；至少在該第一半導體鰭之相對側面上形成複數個介電鰭側壁結構；降低該第一半導體鰭；形成一第一磊晶結構在該降低之第一半導體鰭上，且該第一磊晶結構包含：一頂部分，具有一第一寬度；以及一主體部分，置於該頂部分與該半導體鰭之間且具有比該第一寬度小之一第二寬度，且該第三寬度與該第二寬度實質相同；降低該第二半導體鰭；以及 形成一第二磊晶結構在該降低之第二半導體鰭上，其中該第一磊晶結構及該第二磊晶結構具有不同類型。
  8. 如請求項7所述之方法，更包含：調整該些介電鰭側壁結構之高度。
TW105103805A 2015-11-11 2016-02-04 半導體裝置與其製造方法以及靜態隨機存取記憶體 TWI587486B (zh)

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Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10115807B2 (en) * 2015-11-18 2018-10-30 Globalfoundries Inc. Method, apparatus and system for improved performance using tall fins in finFET devices
WO2017111888A1 (en) * 2015-12-21 2017-06-29 Intel Corporation Envelope-tracking control techniques for highly-efficient rf power amplifiers
CN107346762A (zh) * 2016-05-05 2017-11-14 中芯国际集成电路制造(上海)有限公司 鳍式场效应管的形成方法
US10515969B2 (en) 2016-11-17 2019-12-24 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
CN108122976B (zh) * 2016-11-29 2020-11-03 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法、以及sram
US10147787B1 (en) * 2017-05-31 2018-12-04 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure and manufacturing method thereof
CN109273407B (zh) * 2017-07-18 2021-05-04 中芯国际集成电路制造(上海)有限公司 半导体器件及其形成方法
CN109390342A (zh) 2017-08-02 2019-02-26 中芯国际集成电路制造(上海)有限公司 Sram存储器及其形成方法
US11011545B2 (en) * 2017-11-14 2021-05-18 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device including standard cells
US10510894B2 (en) * 2017-11-30 2019-12-17 Taiwan Semiconductor Manufacturing Co., Ltd. Isolation structure having different distances to adjacent FinFET devices
CN110571195B (zh) * 2018-06-05 2021-12-21 中芯国际集成电路制造(上海)有限公司 一种sram及其制造方法和电子装置
KR102612196B1 (ko) 2018-06-20 2023-12-12 삼성전자주식회사 반도체 장치
KR102456669B1 (ko) 2018-07-16 2022-10-20 삼성전자주식회사 반도체 소자
US11282751B2 (en) * 2018-10-26 2022-03-22 Taiwan Semiconductor Manufacturing Co., Ltd. Dielectric fins with different dielectric constants and sizes in different regions of a semiconductor device
US11088150B2 (en) 2019-01-28 2021-08-10 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
CN112018112A (zh) * 2019-05-29 2020-12-01 中芯国际集成电路制造(上海)有限公司 半导体单元结构及其形成方法
US11049774B2 (en) * 2019-07-18 2021-06-29 Taiwan Semiconductor Manufacturing Company, Ltd. Hybrid source drain regions formed based on same Fin and methods forming same
US11600728B2 (en) * 2020-06-15 2023-03-07 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing a facet-free source/drain epitaxial structure having an amorphous or polycrystalline layer

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201419451A (zh) * 2012-11-14 2014-05-16 Taiwan Semiconductor Mfg 靜態隨機存取記憶單元陣列與其形成方法
US20150214366A1 (en) * 2014-01-24 2015-07-30 Taiwan Semiconductor Manufacturing Company Ltd. Embedded source or drain region of transistor with downward tapered region under facet region

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100470841C (zh) * 2005-03-30 2009-03-18 台湾积体电路制造股份有限公司 类平面及类鳍式场效晶体管的晶体管元件及其制造方法
US7968394B2 (en) * 2005-12-16 2011-06-28 Freescale Semiconductor, Inc. Transistor with immersed contacts and methods of forming thereof
JP4310399B2 (ja) * 2006-12-08 2009-08-05 株式会社東芝 半導体装置及びその製造方法
US7939889B2 (en) * 2007-10-16 2011-05-10 Taiwan Semiconductor Manufacturing Company, Ltd. Reducing resistance in source and drain regions of FinFETs
US8264021B2 (en) * 2009-10-01 2012-09-11 Taiwan Semiconductor Manufacturing Company, Ltd. Finfets and methods for forming the same
US8310013B2 (en) * 2010-02-11 2012-11-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating a FinFET device
US9281378B2 (en) * 2012-01-24 2016-03-08 Taiwan Semiconductor Manufacturing Company, Ltd. Fin recess last process for FinFET fabrication
US8865560B2 (en) * 2012-03-02 2014-10-21 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET design with LDD extensions
KR20130106093A (ko) * 2012-03-19 2013-09-27 삼성전자주식회사 전계 효과 트랜지스터 및 그 형성 방법
US8703556B2 (en) 2012-08-30 2014-04-22 Taiwan Semiconductor Manufacturing Company, Ltd. Method of making a FinFET device
US9196613B2 (en) * 2013-11-19 2015-11-24 International Business Machines Corporation Stress inducing contact metal in FinFET CMOS
US9431537B2 (en) * 2014-03-26 2016-08-30 Samsung Electronics Co., Ltd. Semiconductor devices and methods of fabricating the same
KR102158961B1 (ko) * 2014-05-13 2020-09-24 삼성전자 주식회사 반도체 장치 및 그 제조 방법
KR102227128B1 (ko) * 2014-09-03 2021-03-12 삼성전자주식회사 반도체 장치 및 이의 제조 방법
US10032910B2 (en) * 2015-04-24 2018-07-24 GlobalFoundries, Inc. FinFET devices having asymmetrical epitaxially-grown source and drain regions and methods of forming the same
KR102402763B1 (ko) * 2018-03-27 2022-05-26 삼성전자주식회사 반도체 장치

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201419451A (zh) * 2012-11-14 2014-05-16 Taiwan Semiconductor Mfg 靜態隨機存取記憶單元陣列與其形成方法
US20150214366A1 (en) * 2014-01-24 2015-07-30 Taiwan Semiconductor Manufacturing Company Ltd. Embedded source or drain region of transistor with downward tapered region under facet region

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