TWI584472B - 半導體元件結構及其形成方法 - Google Patents

半導體元件結構及其形成方法 Download PDF

Info

Publication number
TWI584472B
TWI584472B TW104138902A TW104138902A TWI584472B TW I584472 B TWI584472 B TW I584472B TW 104138902 A TW104138902 A TW 104138902A TW 104138902 A TW104138902 A TW 104138902A TW I584472 B TWI584472 B TW I584472B
Authority
TW
Taiwan
Prior art keywords
work function
layer
gate
dielectric layer
fin structure
Prior art date
Application number
TW104138902A
Other languages
English (en)
Other versions
TW201642465A (zh
Inventor
張哲誠
莊瑞萍
呂禎祥
陳威廷
劉又誠
Original Assignee
台灣積體電路製造股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Publication of TW201642465A publication Critical patent/TW201642465A/zh
Application granted granted Critical
Publication of TWI584472B publication Critical patent/TWI584472B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/26—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys
    • H01L29/267—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66553—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using inside spacers, permanent or not
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Materials Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)

Description

半導體元件結構及其形成方法
本揭露係關於半導體元件結構及其形成方法。
半導體積體電路(IC)工業已歷經快速發展的階段。積體電路材料及設計在技術上的進步已生產出許多代的積體電路。每一代的積體電路比前代的積體電路具有更小且更複雜的電路。
在積體電路發展的進程中，功能性密度(亦即每一個晶片區域中內連接元件的數目)已經普遍增加，而幾何尺寸(亦即製程中所能創造出最小的元件或線路)則是下降。這種微縮化的過程通常可藉由增加生產效率及降低相關支出提供許多利益。
然而，這些進步也增加了積體電路在加工和製造上的複雜度。因為特徵尺寸持續縮小，製程也持續變得更加難以實施。因此，形成具有越來越小的尺寸之可靠的半導體元件將是一個挑戰。
本揭露提供一種半導體元件結構，包括：一鰭狀結構，位於一半導體基板之上；一閘極堆疊，覆蓋鰭狀結構的一部分，其中閘極堆疊包括一功函數層和一閘極介電層；以及 一隔離元件，位於半導體基板之上且相鄰閘極堆疊，其中隔離元件與功函數層和閘極介電層直接接觸，且隔離元件的一較低的寬度大於隔離元件的一較高的寬度。
本揭露另提供一種半導體元件結構，包括：一第一鰭狀結構和一第二鰭狀結構，位於一半導體基板之上；一第一閘極堆疊，覆蓋第一鰭狀結構的一部分；一第二閘極堆疊，覆蓋第二鰭狀結構的一部分；以及一隔離元件，相鄰第一閘極堆疊和第二閘極堆疊，其中隔離元件的一較低的寬度大於隔離元件的一較高的寬度。
本揭露更提供一種半導體元件結構的形成方法，包括：形成一第一鰭狀結構和一第二鰭狀結構於一半導體基板之上；形成一虛設閘極堆疊於半導體基板之上以部分地覆蓋第一鰭狀結構和第二鰭狀結構；移除虛設閘極堆疊以形成一溝槽於半導體基板之上；形成一閘極介電層於溝槽中；形成一凹槽於閘極介電層中；形成一隔離元件於溝槽中以填充凹槽；以及形成一功函數金屬層於閘極介電層之上和隔離元件的一側壁之上。
為讓本揭露之上述和其他目的、特徵、和優點能更明顯易懂，下文特舉出較佳實施例，並配合所附圖式，作詳細說明如下：
100‧‧‧半導體基板
101A、101B‧‧‧鰭狀結構
102‧‧‧隔離特徵
104‧‧‧閘極介電層
106‧‧‧虛設閘極電極層
107‧‧‧虛設閘極堆疊
108a、108b‧‧‧硬罩幕層
110A、110B‧‧‧部分
112‧‧‧間隔元件
113‧‧‧介電層
114A、114B‧‧‧源極/汲極結構
116‧‧‧溝槽
118‧‧‧閘極介電層
120‧‧‧阻障層
120A、120B‧‧‧阻障元件
122A、122B‧‧‧功函數層
124‧‧‧阻擋層
126‧‧‧金屬填充層
126A、126B‧‧‧金屬填充
132‧‧‧凹槽
133A、133B‧‧‧閘極堆疊
134、134’‧‧‧隔離元件
134s‧‧‧側壁
134b‧‧‧底部
L‧‧‧假想線
W1、W2‧‧‧寬度
H‧‧‧高度
P‧‧‧假想面
θ‧‧‧角度
I-I、J-J、K-K‧‧‧線
本揭示最好配合圖式及詳細說明閱讀以便了解。要強調的是，依照工業上的標準實施，各個特徵並未按照比例繪製。事實上，為了清楚之討論，可能任意的放大或縮小各個 特徵的尺寸。
第1A~1I圖為根據一些實施例顯示形成半導體元件結構製程中各階段剖面圖。
第2A~2G圖為根據一些實施例顯示形成半導體元件結構製程中各階段俯視圖。
第3A~3D圖為根據一些實施例顯示形成半導體元件結構製程中各階段剖面圖。
以下揭示提供許多不同的實施方法或是例子來實行本揭露之不同特徵。以下描述具體的元件及其排列的例子以簡化本揭露。當然這些僅是例子且不該以此限定本揭露的範圍。例如，在描述中提及第一個元件形成於第二個元件之上時，其可能包括第一個元件與第二個元件直接接觸的實施例，也可能包括兩者之間有其他元件形成而沒有直接接觸的實施例。此外，在不同實施例中可能使用重複的標號及/或符號，這些重複僅為了簡單清楚地敘述本揭露，不代表所討論的不同實施例及/或結構之間有特定的關係。
此外，其中可能用到與空間相關的用詞，像是“在...下方”、“下方”、“較低的”、“上方”、“較高的”及類似的用詞，這些關係詞係為了便於描述圖式中一個(些)元件或特徵與另一個(些)元件或特徵之間的關係。這些空間關係詞包括使用中或操作中的裝置之不同方位，以及圖式中所描述的方位。裝置可能被轉向不同方位(旋轉90度或其他方位)，則其中使用的空間相關形容詞也可相同地照著解釋。
以下描述本揭露的一些實施例。第1A~1I圖為根據一些實施例顯示形成半導體元件結構製程中各階段剖面圖。可在第1A~1I圖所述的階段之前、期間、及/或之後提供額外的操作。在不同的實施例中，可置換或刪除前述的一些階段。可加入額外的特徵到半導體元件結構。在不同的實施例中，可置換或刪除以下所述的一些特徵。
如第1A圖所示，提供半導體基板100。在一些實施例中，半導體基板100可為塊狀半導體基板，像是一半導體晶圓。例如，半導體基板100為一矽晶圓。半導體基板100可包括矽或其他元素半導體材料，像是鍺。在一些其他的實施例中，半導體基板100包括一化合物半導體。化合物半導體可包括砷化鍺、碳化矽、砷化銦、磷化銦、其他合適的化合物半導體、或前述之組合。
在一些實施例中，半導體基板100包括一絕緣物上半導體(semiconductor-on-insulator；SOI)基板。可利用氧植入隔離(SIMOX)製程、晶圓接合製程、其他可應用的方式、或前述之組合形成SOI基板。
如第1A圖所示，以假想線L將半導體基板100分為部分110A和110B。在一些實施例中，兩個或更多個電晶體形成於半導體基板100的部分110A和110B中及/或之上。在一些實施例中，p-型金氧半場效電晶體(PMOSFET)和n-型金氧半場效電晶體(NMOSFET)將分別形成於部分110A和110B中及/或之上。在一些其他實施例中，NMOSFET和PMOSFET將分別形成於部分110A和110B中及/或之上。在一些其他實施例中， NMOSFETs將形成於部分110A和110B中及/或之上。在一些其他實施例中，PMOSFETs將形成於部分110A和110B中及/或之上。
如第1A圖所示，根據一些實施例，形成複數個凹槽(或溝槽)於半導體基板100中。因此，形成包括鰭狀結構101A和101B的複數個鰭狀結構於凹槽之間。在一些實施例中，凹槽式利用一個或多個微影和蝕刻製程所形成。
如第1A圖所示，根據一些實施例，形成隔離特徵102於凹槽中以圍繞鰭狀結構101A和101B的較低部分。利用隔離特徵102以定義和電性隔離形成於半導體基板100中及/或之上的各種裝置元件。在一些實施例中，隔離特徵102包括淺溝槽隔離(shallow trench isolation；STI)特徵、半導體局部氧化(local oxidation of semiconductor；LOCOS)特徵、其他合適的隔離特徵、或前述之組合。
在一些實施例中，每一個隔離特徵102具有多層結構。在一些實施例中，隔離特徵102由介電材料形成。介電材料可包括氧化矽、氮化矽、氮氧化矽、氯摻雜矽酸鹽玻璃(fluoride-doped silicate glass；FSG)、低介電常數(low-k)介電材料、其他合適的材料、或前述之組合。在一些實施例中，形成STI襯層(未顯示)以降低半導體基板100和隔離特徵102之間於界面上的晶體缺陷(crystalline defects)。類似地，也可形成STI襯層以降低鰭狀結構和隔離特徵102之間於界面上的晶體缺陷。
在一些實施例中，將介電材料層沉積於半導體基 板100之上。介電材料層覆蓋包括鰭狀結構101A和101B的鰭狀結構且填充鰭狀結構之間的凹槽。在一些實施例中，利用化學氣相沉積(CVD)製程、旋塗式(spin-on)製程、其他可應用的製程、或前述之組合沉積介電材料層。在一些實施例中，實施平坦化製程以薄化介電材料層，直到曝露出鰭狀結構101A和101B。平坦化製程可包括化學機械平坦化(CMP)製程、研磨製程、蝕刻製程、其他可應用的製程、或前述之組合。之後，將介電材料層回蝕刻以形成隔離特徵102。根據一些實施例，鰭狀結構包括從隔離特徵102突出的鰭狀結構101A和101B，如第1A圖所示。
如第1B圖所示，根據一些實施例，將閘極介電層104和虛設閘極電極層106沉積於隔離特徵102和鰭狀結構101A和101B之上。在一些實施例中，閘極介電層104是由氧化矽、氮化矽、氮氧化矽、高介電常數(high-k)介電材料、其他合適的介電材料、或前述之組合所形成。高介電常數(high-k)介電材料的例子包括氧化鉿、氧化鋯、氧化鋁、二氧化鋁鉿合金、二氧化矽鉿、氮氧化矽鉿、氧化鉭鉿、氧化鈦鉿、氧化鋯鉿、其它合適的高介電常數(high-k)介電材料、或前述之組合。在一些實施例中，閘極介電層104為後續將被移除的虛設閘極介電層。虛設閘極介電層例如為一氧化矽層。
在一些實施例中，利用化學氣相沉積(CVD)製程、原子層沉積(ALD)製程、熱氧化製程、物理氣相沉積(PVD)製程、其他可應用的製程、或前述之組合沈積閘極介電層104。在一些實施例中，虛設閘極電極層106由多晶矽形成。例如， 利用CVD製程、或其他可應用的製程沉積虛設閘極電極層106。可對本揭露的實施例進行許多改變及/或修飾。在一些實施例中，未形成閘極介電層104。
之後，根據一些實施例，形成圖案化硬罩幕於虛設閘極電極層106之上，如第1B圖所示。圖案化硬罩幕係用以將虛設閘極電極層106和閘極介電層104圖案化為一個或更多個虛設閘極堆疊(或虛設閘極線)。在一些實施例中，圖案化硬罩幕包括第一硬罩幕層108a和第二硬罩幕層108b。在一些實施例中，第一硬罩幕層108a是由氮化矽形成。在一些實施例中，第二硬罩幕層108b是由氧化矽形成。在一些實施例中，第二硬罩幕層108b比第一硬罩幕層108a厚。
在一些實施例中，虛設閘極堆疊是形成於隔離特徵102和鰭狀結構101A和101B之上的複數個虛設閘極線。在一些實施例中，虛設閘極線實質上與彼此平行。在一些實施例中，每一個虛設閘極堆疊(或虛設閘極線)在後續製程中被形成為不同電晶體的兩個或更多個閘極堆疊。
在一些實施例中，圖案化光阻層(未顯示)係用以幫助圖案化硬罩幕層的形成。圖案化光阻層是透過微影製程形成。微影製程可包括光阻塗佈(例如：旋塗式塗佈)、軟烤(soft baking)、光罩對準、曝光、曝光後烘烤、光阻顯影、沖洗、乾燥(例如：硬烤)、其他合適的製程、或前述之組合。
之後，根據一些實施例，圖案化虛設閘極電極層106和閘極介電層104以形成一個或更多個虛設閘極堆疊107，如第1C圖所示。在一些實施例中，硬罩幕層108a和108b此後被 移除。
第2A~2G圖為根據一些實施例顯示形成半導體元件結構製程中各階段俯視圖。在一些實施例中，第2A圖為第1C圖所示結構的俯視圖。如第1C圖和第2A圖所示，根據一些實施例，形成複數個虛設閘極堆疊107。為達簡短的目的，第2A圖僅顯示虛設閘極堆疊107(或虛設閘極線)。每一個虛設閘極堆疊107包括虛設閘極電極層106和閘極介電層104。在第1C圖和第2B~2G圖中，為達簡短的目的，僅顯示虛設閘極堆疊107之一。
之後，根據一些實施例，形成源極/汲極結構於鰭狀結構101A和101B之上且相鄰虛設閘極堆疊107。第3A~3D圖為根據一些實施例顯示形成半導體元件結構製程中各階段剖面圖。在一些實施例中，第1C~1I圖為沿著第2C~2G圖的I-I線繪製的剖面圖。在一些實施例中，第3A~3C圖為沿著第2C~2G圖的J-J線繪製的剖面圖，且第3D圖為沿著第2G圖的K-K線繪製的剖面圖。
參照第2C圖和第3A圖，根據一些實施例，源極/汲極結構114A和114B形成於半導體基板100之上且位於虛設閘極堆疊107之間。如上所述，在一些實施例中，兩個電晶體形成於半導體基板100的部分110A和110B中及/或之上。源極/汲極結構114A是形成於部分110A中及/或之上的一部分電晶體，且源極/汲極結構114B是形成於部分110B中及/或之上的另一部分電晶體。
在一些實施例中，根據一些實施例，使鰭狀結構 101A和101B凹陷以使其低於隔離特徵102的頂表面。在一些實施例中，實施蝕刻製程以移除鰭狀結構101A和101B的較高部分。因此，凹槽形成於鰭狀結構101A(和101B)上方，如第3A圖所示。在一些其他實施例中，使用複數個蝕刻操作，因而凹槽進一步橫向地朝著虛設閘極堆疊107下方的通道區域延伸。
在一些實施例中，半導體材料(或兩個或更多個半導體材料)磊晶生長於凹陷的鰭狀結構之上，持續生長至凹槽上方以形成源極/汲極結構114A和114B。在一些實施例中，同時實施源極/汲極結構114A和114B的生長。在一些實施例中，分別在不同的製程中實施源極/汲極結構114A和114B的生長。
在一些實施例中，源極/汲極結構114A為p-型半導體材料。例如，源極/汲極結構114A可包括磊晶生長鍺化矽。源極/汲極結構114A並不限於p-型半導體材料。在一些實施例中，源極/汲極結構114A為n-型半導體材料。源極/汲極結構114A可包括磊晶生長矽、磊晶生長碳化矽(SiC)、磊晶生長磷化矽(SiP)、或其他合適的磊晶生長半導體材料。
在一些實施例中，源極/汲極結構114A和114B都是p-型。在一些實施例中，源極/汲極結構114A和114B都是n-型。在一些實施例中，源極/汲極結構114A和114B之一為p-型，且源極/汲極結構114A和114B的另一個為n-型。
在一些實施例中，利用選擇性磊晶生長(SEG)製程、CVD製程(例如：氣相磊晶(VPE)製程)、低壓化學氣相沉積(LPCVD)製程、及/或超高真空CVD(UHV-CVD)製程、分子束磊晶製程、其他可應用的製程、或前述之組合形成源極/汲極結 構114A和114B。可利用氣體及/或液體製程作為源極/汲極結構114A和114B的形成製程。在一些實施例中，源極/汲極結構114A和114B都在相同的製程腔室中原位(in-situ)生長。換句話說，源極/汲極結構114A和114B是透過原位(in-situ)磊晶生長製程而形成。在一些其他實施例中，源極/汲極結構114A和114B分別生長。
源極/汲極結構114A和114B包括摻質。在一些實施例中，實施複數個植入(implantation)製程以摻雜源極/汲極結構114A和114B。在一些實施例中，形成間隔元件112於虛設堆疊閘極107的側壁之上以幫助源極/汲極結構114A和114B的形成，如第2C圖和第3A圖所示。在一些實施例中，在形成間隔元件112之前，利用離子植入製程形成輕摻雜源極/汲極區域(未顯示)。
在一些實施例中，在源極/汲極結構114A和114B生長期間對源極/汲極結構114A和114B進行原位(in-situ)摻雜。在一些其他實施例中，在源極/汲極結構114A和114B生長期間未對源極/汲極結構114A和114B進行摻雜。在磊晶生長之後，在後續製程中對源極/汲極結構114A和114B進行摻雜。在一些實施例中，利用離子植入製程、電漿浸入離子植入製程、氣體及/或固體源擴散製程(gas and/or solid source diffusion process)、其他可應用的製程、或前述之組合達成摻雜。在一些實施例中，更進一步將源極/汲極結構114A和114B曝露於退火製程以活化摻質。例如，實施一快速熱退火製程。
如第1D、2D、3B圖所示，根據一些實施例，移除 虛設閘極堆疊107。在一些實施例中，在移除虛設閘極堆疊107之前，將介電層113沈積於源極/汲極結構114A和114B以及虛設閘極堆疊107之上，如第2D圖和第3B圖所示。在一些實施例中，介電層113是由氧化矽、氮氧化矽、硼矽酸鹽玻璃(borosilicate glass；BSG)、磷矽酸鹽玻璃(phosphoric silicate glass；PSG)、硼磷矽玻璃(borophosphosilicate glass；BPSG)、氟摻雜矽酸鹽玻璃(fluoride-doped silicate glass；FSG)、低介電常數(low-k)材料、多孔介電材料、其他合適的介電材料、或前述之組合所形成。在一些實施例中，介電層113是透過CVD製程、旋塗式製程、ALD製程、PVD製程、其他可應用的製程、或前述之組合沈積。
之後，薄化介電層113直到曝露出虛設閘極電極層106。經薄化的介電層113圍繞虛設閘極堆疊107。在一些實施例中，利用平坦化製程薄化介電層113。平坦化製程可包括化學機械平坦化(CMP)製程、研磨製程、蝕刻製程、其他可應用的製程、或前述之組合。可對本揭露的實施例進行許多改變及/或修飾。在一些實施例中，未形成介電層113。
之後，根據一些實施例，移除虛設閘極堆疊107以形成溝槽116於鰭狀結構101A和101B以及隔離特徵102之上，如第1D、2D、3B圖所示。在一些實施例中，形成介電層113，且溝槽116形成於介電層113中。換句話說，介電層113圍繞溝槽116。在一些實施例中，溝槽116位於間隔元件112之間。在一些實施例中，溝槽116曝露原本被虛設閘極堆疊107覆蓋的鰭狀結構101A和101B的一部分，如第1D、2D、3B圖所示。鰭狀 結構101A和101B曝露的部分可作為通道區域。在一些實施例中，虛設閘極堆疊107是透過乾蝕刻製程、濕蝕刻製程、其他可應用的製程、或前述之組合而移除。在一些實施例中，閘極介電層104是由高介電常數(high-K)材料所形成且未被移除。在這些情況中，溝槽116曝露出閘極介電層104。
根據一些實施例，在移除虛設閘極堆疊107之後，將一些金屬閘極堆疊層沈積於溝槽116的側壁和底部之上，如第1E、2E、3C、3D圖所示。如上所述，在一些實施例中，每一個虛設閘極堆疊107(或虛設閘極線)將被形成為不同電晶體的兩個或更多個閘極堆疊。因此，在移除虛設閘極堆疊107後所形成的溝槽116足夠長到可包含電晶體的兩個或更多個金屬閘極堆疊。這些金屬閘極堆疊層的沈積或填充，比起在設計成只包含電晶體的一個金屬閘極堆疊的溝槽中實施金屬閘極堆疊層的沈積或填充的情況簡單。因此，可顯著地擴大製程窗口。
在一些實施例中，形成兩個電晶體於半導體基板100的部分110A和110B中及/或之上。在一些實施例中，電晶體之一為p-型電晶體，且另一個電晶體為n-型電晶體。在一些實施例中，兩個電晶體都是p-型電晶體。在一些實施例中，兩個電晶體都是n-型電晶體。在一些實施例中，一個或更多個p-型功函數層形成於部分110A之上，且一個或更多個n-型功函數層形成於部分110B之上。在一些實施例中，一個或更多個n-型功函數層形成於部分110A之上，且一個或更多個p-型功函數層形成於部分110B之上。
如第1E、3C、3D圖所示，根據一些實施例，將閘極介電層118沈積於溝槽116的側壁和底部之上。在一些實施例中，閘極介電層118延伸於部分110A和110B之上。在一些實施例中，閘極介電層118共形地延伸於鰭狀結構101A和101B之上。在一些實施例中，閘極介電層118為高介電常數(high-k)層。高介電常數(high-k)層可由氧化鉿、氧化鋯、氧化鋁、二氧化鋁鉿合金、二氧化矽鉿、氮氧化矽鉿、氧化鉭鉿、氧化鈦鉿、氧化鋯鉿、其它合適的高介電常數(high-k)介電材料、或前述之組合組成。
在一些實施例中，利用ALD製程、CVD製程、旋塗式製程、其他可應用的製程、或前述之組合沈積閘極介電層118。在一些實施例中，實施高溫退火操作以降低或消除閘極介電層118中的缺陷。可對本揭露的實施例進行許多改變及/或修飾。在一些實施例中，兩個不同的閘極介電層分別形成於部分110A和110B之上以作為不同電晶體的閘極介電層。
在一些實施例中，在形成閘極介電層118之前，在溝槽116中形成一界面層(interfacial layer)(未顯示)。界面層可用以減少閘極介電層118與鰭狀結構101A和101B之間的壓力。在一些實施例中，界面層是由氧化矽組成。在一些實施例中，界面層是透過ALD製程、熱氧化製程、其他可應用的製程、或前述之組合形成。
如第1E、3C、3D圖所示，根據一些實施例，將阻障層120沈積於閘極介電層118之上。可利用阻障層120作為閘極介電層118和後續形成的功函數層之間的界面。阻障層120也 可用以避免閘極介電層118和後續形成的功函數層之間的擴散。在一些實施例中，阻障層120共形地延伸於鰭狀結構101A和101B之上。
在一些實施例中，阻障層120是由包含金屬的材料組成。包含金屬的材料可包括氮化鈦、氮化鉭、其他合適的材料、或前述之組合。在一些實施例中，阻障層120包括多層。在一些實施例中，阻障層120是透過ALD製程、PVD製程、電鍍製程、無電解電鍍製程、CVD製程、其他可應用的製程、或前述之組合形成。在一些其他實施例中，未形成阻障層120。在一些實施例中，兩個不同的阻障層分別形成於部分110A和110B之上作為不同電晶體的阻障層。
如第1F圖和第2F圖所示，根據一些實施例，移除部分的閘極介電層118和阻障層120以形成一個或更多個凹槽132。根據一些實施例，凹槽132將閘極介電層118和阻障層120分隔為兩部分，如第1F圖和第2F圖所示。如第1F圖和第2F圖所示，凹槽132具有寬度W1。在一些實施例中，寬度W1的範圍為從約15nm至約1000nm。阻障層120被劃分以形成阻障元件120A和120B，如第1F圖和第2F圖所示。在一些實施例中，阻障元件120A和120B沒有與彼此直接接觸。如第1F圖和第2F圖所示，根據一些實施例，凹槽132曝露出隔離特徵102。
可對本揭露的實施例進行許多改變及/或修飾。在一些實施例中，部分地移除阻障層120以形成阻障元件120A和120B，且閘極介電層118未被移除。這些情況中，凹槽132曝露出閘極介電層118。
如第1G圖所示，根據一些實施例，形成隔離元件134於溝槽116中以填充凹槽132。在一些實施例中，將介電層沈積於溝槽116的側壁和底部之上。之後，根據一些實施例，圖案化介電層以形成隔離元件134，如第1G圖所示。在一些實施例中，隔離元件134的寬度實質上與凹槽132的寬度W1相等。在一些實施例中，隔離元件134具有實質上垂直的側壁。
在一些實施例中，用以形成隔離元件134的介電層是由氧化矽、氮化矽、氮氧化矽、含碳氧化矽、其他合適的介電材料、或前述之組合所組成。在一些實施例中，介電層包括聚合物材料。在一些實施例中，介電層的材料與介電層113的材料不同。然而，本揭露的實施例不限於此。在一些實施例中，介電層的材料與介電層113的材料實質上相同。
在一些實施例中，利用CVD製程、ALD製程、流動式化學氣相沈積(FCVD)製程、旋塗式製程、其他可應用的製程、或前述之組合沈積介電層。在一些其他實施例中，利用旋塗式製程形成介電層。之後，利用微影製程和蝕刻製程部分地移除介電層以形成隔離元件134。
可對本揭露的實施例進行許多改變及/或修飾。在一些實施例中，隔離元件134包括多層結構。例如，將多層介電層沈積至溝槽116中以填充凹槽132。類似地，實施圖案化製程以部分地移除介電層。因此，形成具有多層結構的隔離元件134。
如第1H圖所示，根據一些實施例，部分地移除隔離元件134以形成經修飾的隔離元件134’。如第1H圖所示，經 修飾的隔離元件134’具有較高的寬度W2、較低的寬度W1、和高度H。在一些實施例中，寬度W1大於寬度W2。在一些實施例中，經修飾的隔離元件134’的寬度沿著隔離元件134’的頂部朝半導體基板100的方向逐漸增加。在一些實施例中，隔離元件134’具有一個傾斜的側壁。
在一些實施例中，因為寬度W2小於寬度W1，後續在鰭狀結構之上形成其他金屬閘極堆疊層將因為開口較大而變得簡單。其他金屬閘極堆疊層可包括功函數層、阻擋層(blocking 1ayer)、及金屬填充層。如上所述，在一些實施例中，寬度W1的範圍為從約15nm至約1000nm。在一些實施例中，寬度W2的範圍為從約10nm至約500nm。在一些實施例中，高度H的範圍為從約50nm至約2000nm。然而，本揭露的實施例不限於此。每一個寬度W1、寬度W2、和高度H可具有不同的範圍。
在一些實施例中，部分地蝕刻隔離元件134以形成經修飾的隔離元件134’。藉由改變蝕刻條件，可微調經修飾的隔離元件134’的輪廓。如第1H圖所示，經修飾的隔離元件134’具有側壁134s和底部134b。側壁134s和平行於隔離元件134’底部134b的假想面P之間的角度θ可藉由改變蝕刻條件而調整。在一些實施例中，角度θ的範圍為從約10度至約85度。在一些其他實施例中，角度θ的範圍為從約20度至約75度。在一些情況中，角度θ應大於約10度以確保寬度W2足夠寬到可電性隔離將形成的相鄰的金屬閘極堆疊。在一些情況中，角度θ應小於約85度以確保後續在鰭狀結構之上形成其他金屬閘極堆疊層是容易實施的。
在一些實施例中，利用一個或多個蝕刻操作以形成經修飾的隔離元件134’。在一些實施例中，蝕刻操作中所使用的蝕刻劑包括氣體混合物。氣體混合物可包括Cl2、HBr、BCl3、NF3、N2、CF4、CH2F2、N2、O2、Ar、N2H2、SF6、SiCl4、CH4、其他合適的氣體、或前述之組合。在蝕刻操作期間，氣體混合物的組成可根據需要而變化。在一些實施例中，用以實施蝕刻操作的壓力範圍為從約1托(torr)至約80托(torr)。在一些實施例中，用以實施蝕刻操作的操作功率範圍為從約100W至約1500W。在一些實施例中，用以實施蝕刻操作的操作溫度範圍為從約10℃至約80℃。在一些實施例中，用以實施蝕刻操作的操作時間範圍為從約5秒至約600秒。
如第1I、3C、3D圖所示，根據一些實施例，形成功函數層122A和122B於阻障層120和隔離元件134’的側壁之上。功函數層是用以提供電晶體所需的功函數以提昇元件性能，包括改良的閾值電壓。在一些實施例中，功函數層122A共形地延伸於鰭狀結構101A和隔離元件134’的側壁134s之上。類似地，功函數層122B共形地延伸於鰭狀結構101B和隔離元件134’相對於側壁134s的側壁之上。
在形成NMOS電晶體的實施例中，功函數層可為一n-型金屬層。n-型金屬層能夠提供適合元件的功函數值，像是等於或小於約4.5eV。n-型金屬層可包括金屬、金屬碳化物、金屬氮化物、或前述之組合。例如，n-型金屬層包括氮化鈦、鉭、氮化鉭、其他合適的材料、或前述之組合。
另一方面，在形成PMOS電晶體的實施例中，功函 數層可為一p-型金屬層。p-型金屬層能夠提供適合元件的功函數值，像是等於或小於約4.8eV。p-型金屬層可包括金屬、金屬碳化物、金屬氮化物、其他合適的材料、或前述之組合。例如，p-型金屬包括氮化鉭、氮化鎢、鈦、氮化鈦、其他合適的材料、或前述之組合。
功函數層也可由鉿(hafnium)、鋯(zirconium)、鈦(titanium)、鉭(tantalum)、鋁(aluminum)、金屬碳化物(例如：碳化鉿、碳化鋯、碳化鈦、碳化鋁)、鋁化物(aluminides)、釕(ruthenium)、鈀(palladium)、鉑(platinum)、鈷(cobalt)、鎳(nickel)、導電金屬氧化物、或前述之組合組成。可微調功函數層的厚度及/或組成以調整功函數的水平(level)。例如，取決於氮化鈦層的厚度及/或組成，氮化鈦層可用來當作p-型金屬層或n-型金屬層。
在一些實施例中，功函數層122A為p-型金屬層，且功函數層122B為n-型金屬層。在一些實施例中，功函數層122A在功函數層122B之前形成。功函數層122A沈積於阻障層120之上。之後，圖案化功函數層122A。例如，將功函數層122A定位於半導體基板100的部份110A之上。移除功函數層122A原本位於部分110B之上的部份。例如，利用微影製程和蝕刻製程圖案化功函數層122A。類似地，在半導體基板100的部份110B之上沈積並圖案化功函數層122B。
可對本揭露的實施例進行許多改變及/或修飾。在一些其他實施例中，功函數層122B在功函數層122A之前形成。存一些其他實施例中，功函數層122A和122B具有相同的導電 類型，像是n-型或p-型。
之後，根據一些實施例，將阻擋層(blocking layer)124沈積於功函數層122A和122B之上，如第1E、3C、3D圖所示。阻擋層124可用以避免後續形成的一金屬填充層擴散至或滲入(penetrating)功函數層。在一些實施例中，阻擋層124共形地形成於功函數層122A和122B之上。
在一些實施例中，阻擋層124是由氮化鉭、氮化碳鈦、其他合適的材料、或前述之組合所組成。在一些實施例中，利用ALD製程、PVD製程、電鍍製程、無電解電鍍製程、其他可應用的製程、或前述之組合沈積阻擋層124。
本揭露的實施例並不限於此。在一些其他實施例中，未形成阻擋層124。在一些其他實施例中，兩層不同的阻擋層用於後續形成的金屬填充層及不同的功函數層122A和122B之間。
之後，根據一些實施例，將金屬填充層126沈積於阻擋層124之上以填充溝槽116，如第1I、3C、3D圖所示。在一些實施例中，金屬填充層126是由鎢(tungsten)、鋁(aluminum)、銅(copper)、鈷(cobalt)、其他合適的材料、或前述之組合所組成。在一些實施例中，利用PVD製程、CVD製程、電鍍製程、無電解電鍍製程、其他可應用的製程、或前述之組合沈積金屬填充層126。在一些其他實施例中，未形成金屬填充層126。在一些其他實施例中，兩層不同的金屬填充層形成於部分110A和110B之上以作為不同電晶體的金屬填充層。
在一些實施例中，形成第一組金屬閘極堆疊層於 部分110A之上，且部分110B被例如一圖案化罩幕阻擋。之後，形成第二組金屬閘極堆疊層於部分110B之上，且第一組金屬閘極堆疊層被其他圖案化罩幕覆蓋。
在一些實施例中，金屬閘極堆疊層包括閘極介電層118、阻障層120、功函數層122A和122B、阻擋層124、及金屬填充層126，這些層一起填充溝槽116並覆蓋介電層113和隔離元件134’。在一些實施例中，移除金屬堆疊層位於溝槽116之外的的部份。例如，利用平坦化製程部分地移除金屬閘極堆疊層，直到曝露出介電層113和隔離元件134’。平坦化製程可包括CMP製程、研磨製程、蝕刻製程、其他可應用的製程、或前述之組合。
根據一些實施例，在平坦化製程之後，形成包括金屬閘極堆疊133A和133B的多層金屬閘極堆疊，如第1I、2G、3C、3D圖所示。在一些實施例中，在平坦化製程之後，金屬填充層126被劃分成多個部分，包括金屬填充126A和126B，如第1I、2G、3C、3D圖所示。在這些情況中，金屬填充126A和126B的材料相同。在一些其他實施例中，金屬填充126A和126B具有不同的材料。在這些情況中，將兩個不同的金屬填充層沈積並圖案化以形成金屬填充126A和126B。在一些實施例中，閘極堆疊133A和133B的閘極介電層是閘極介電層118的一部分。在這些情況中，閘極堆疊133A和133B的閘極介電層具有相同的材料。
將金屬閘極堆疊層的一些層，像是閘極介電層118和阻障層120，沈積至溝槽116中，溝槽116大到足以包含兩個 或更多個閘極堆疊且具有相對低的深寬比(aspect ratio)。因此，這些層的沈積可被良好地實施。金屬閘極堆疊層的品質和可靠度顯著地提昇。在形成具有較窄的頂部分之經修飾的隔離元件134’之後，形成金屬閘極堆疊層的一些層，像是功函數層122A和122B、阻擋層124、及金屬填充層126。在部分地移除隔離元件134以形成經修飾的隔離元件134’之後，由於開口擴大，故這些層的沈積可被良好地實施。金屬閘極堆疊層的品質和可靠度顯著地提昇。由於隔離元件134’的側壁之上具有功函數層，故可更為精確地調整功函數的水平(level)，改良半導體元件結構的性能。
如第1I圖和第2G圖所示，根據一些實施例，隔離元件134’相鄰閘極堆疊133A和133B。在一些實施例中，隔離元件134’與功函數層122A和122B直接接觸，如第1I圖所示。在一些實施例中，功函數層122A延伸至隔離元件134’的側壁134s上，且功函數層122B延伸至隔離元件134’相對於側壁134s的側壁上。在一些實施例中，隔離元件134’與閘極堆疊133A和133B的金屬填充126A和126B沒有直接接觸。在一些實施例中，功函數層122A和122B與間隔元件112沒有直接接觸，如第3C圖和第3D圖所示。在一些實施例中，隔離元件134’也與閘極堆疊133A和133B的閘極介電層118直接接觸。在一些實施例中，隔離元件134’也與隔離特徵102直接接觸，如第1I圖所示。
如第1I圖和第2G圖所示，根據一些實施例，形成各包括閘極堆疊133A和133B的兩個電晶體。隔離元件134’形成於閘極堆疊133A和133B的末端之間，以電性隔離閘極堆疊 133A與閘極堆疊133B。閘極介電層和阻障層與隔離元件134’的較低部分直接接觸，且功函數層與隔離元件134’的較高部分直接接觸。
本揭露的實施例形成具有一個或更多個金屬閘極堆疊和鰭狀結構的半導體元件結構。將虛設閘極線移除以形成溝槽，並於溝槽中形成多於兩個的金屬閘極堆疊。用以形成金屬閘極堆疊的金屬閘極堆疊層的一些層沈積至大到足以包含兩個或更多個閘極堆疊的溝槽中。因此，這些層的沈積可被良好地實施。在具有較窄的頂部分之經修飾的隔離元件形成後，形成金屬閘極堆疊層的一些層，包括功函數層。因此，溝槽仍然具有一較低的深寬比(aspect ratio)，且這些層的沈積也可被良好地實施。由於隔離元件的側壁之上具有功函數層，半導體元件結構的性能獲得改良。
根據一些實施例，提供一種半導體元件結構。半導體元件結構包括位於一半導體基板之上的一鰭狀結構，且一閘極堆疊覆蓋鰭狀結構的一部分。閘極堆疊包括一功函數層和一閘極介電層。半導體元件結構也包括位於半導體基板之上且相鄰閘極堆疊的一隔離元件。隔離元件與功函數層和閘極介電層直接接觸，且隔離元件的一較低的寬度大於隔離元件的一較高的寬度。
根據一些實施例，提供一種半導體元件結構。半導體元件結構包括位於一半導體基板之上的一第一鰭狀結構和一第二鰭狀結構。半導體元件結構也包括覆蓋第一鰭狀結構的一部分的一第一閘極堆疊，及覆蓋第二鰭狀結構的一部分的 一第二閘極堆疊。半導體元件結構更包括相鄰第一閘極堆疊和第二閘極堆疊的一隔離元件。隔離元件的一較低的寬度大於隔離元件的一較高的寬度。
根據一些實施例，提供一種半導體元件結構的形成方法。此方法包括形成一第一鰭狀結構和一第二鰭狀結構於一半導體基板之上。此方法也包括形成一虛設閘極堆疊於半導體基板之上以部分地覆蓋第一鰭狀結構和第二鰭狀結構。此方法更包括移除虛設閘極以形成一溝槽於半導體基板之上，以及形成一閘極介電層於溝槽中。此外，此方法包括形成一凹槽於閘極介電層中，以及形成一隔離元件於溝槽中以填充凹槽。此方法也包括形成一功函數金屬層於閘極介電層之上和隔離元件的一側壁之上。
前述內文概述了許多實施例的特徵，以使本技術領域中具有通常知識者可以從各個方面更佳地了解本揭露。本技術領域中具有通常知識者應可理解，且可輕易地以本揭露為基礎來設計或修飾其他製程及結構，並以此達到相同的目的及/或達到與在此介紹的實施例等相同之優點。本技術領域中具有通常知識者也應了解這些相等的結構並未背離本揭露的發明精神與範圍。在不背離本揭露的發明精神與範圍之前提下，可對本揭露進行各種改變、置換或修改。
雖然本揭露已以數個較佳實施例揭露如上，然其並非用以限定本揭露，任何所屬技術領域中具有通常知識者，在不脫離本揭露之精神和範圍內，當可作任意之更動與潤飾，因此本揭露之保護範圍當視後附之申請專利範圍所界定者為 準。
100‧‧‧半導體基板
101A、101B‧‧‧鰭狀結構
102‧‧‧隔離特徵
110A、110B‧‧‧部分
118‧‧‧閘極介電層
120‧‧‧阻障層
120A、120B‧‧‧阻障元件
122A、122B‧‧‧功函數層
124‧‧‧阻擋層
126‧‧‧金屬填充層
133A、133B‧‧‧閘極堆疊
134’‧‧‧隔離元件
134s‧‧‧側壁
134b‧‧‧底部
L‧‧‧假想線
W1、W2‧‧‧寬度
H‧‧‧高度
P‧‧‧假想面
θ‧‧‧角度

Claims (9)

  1. 一種半導體元件結構，包括：一鰭狀結構，位於一半導體基板之上；一閘極堆疊，覆蓋該鰭狀結構的一部分，其中該閘極堆疊包括一功函數層和一閘極介電層；以及一隔離元件，位於該半導體基板之上且相鄰該閘極堆疊，其中該隔離元件與該功函數層和該閘極介電層直接接觸，且該隔離元件的一較低的寬度大於該隔離元件的一較高的寬度，該功函數層共形地延伸在該鰭狀結構之上和該隔離元件的一側壁之上。
  2. 如申請專利範圍第1項所述之半導體元件結構，更包括一間隔元件，位於該閘極堆疊的一側壁之上；其中該功函數層與該間隔元件沒有直接接觸。
  3. 一種半導體元件結構，包括：一第一鰭狀結構和一第二鰭狀結構，位於一半導體基板之上；一第一閘極堆疊，覆蓋該第一鰭狀結構的一部分；一第二閘極堆疊，覆蓋該第二鰭狀結構的一部分；以及一隔離元件，相鄰該第一閘極堆疊和該第二閘極堆疊，其中該隔離元件的一較低的寬度大於該隔離元件的一較高的寬度，該第一功函數層共形地延伸於該第一鰭狀結構之上和該隔離元件的一第一側壁之上，且該第二功函數層共形地延伸於該第二鰭狀結構之上和該隔離元件的一第二側壁之上。
  4. 如申請專利範圍第3項所述之半導體元件結構，其中該隔離元件與該第一閘極堆疊的一第一功函數層及該第二閘極堆疊的一第二功函數層直接接觸，更包括一間隔元件，位於該閘極堆疊的一側壁之上，其中該第一功函數層和該第二功函數層與該間隔元件沒有直接接觸。
  5. 如申請專利範圍第3或4項所述之半導體元件結構，更包括：一第一閘極介電層，位於該第一鰭狀結構和該第一功函數層之間；以及一第二閘極介電層，位於該第二鰭狀結構和該第二功函數層之間，其中該隔離元件與該第一閘極介電層和該第二閘極介電層直接接觸；其中該第一閘極介電層和該第二閘極介電層的材料相同。
  6. 如申請專利範圍第3或4項所述之半導體元件結構，更包括一隔離特徵，位於該半導體基板和該第一閘極堆疊之間，其中該隔離元件與該隔離特徵直接接觸。
  7. 一種半導體元件結構的形成方法，包括：形成一第一鰭狀結構和一第二鰭狀結構於一半導體基板之上；形成一虛設閘極堆疊於該半導體基板之上以部分地覆蓋該第一鰭狀結構和該第二鰭狀結構；移除該虛設閘極堆疊以形成一溝槽於該半導體基板之上；形成一閘極介電層於該溝槽中；形成一凹槽於該閘極介電層中； 形成一隔離元件於該溝槽中以填充該凹槽；形成一功函數層於該閘極介電層之上和該隔離元件的一側壁之上；以及形成一第二功函數層於該閘極介電層之上和該隔離元件的一第二側壁之上，其中該功函數層與該第二功函數層沒有直接接觸；其中該功函數層在該第二功函數層之前形成。
  8. 如申請專利範圍第7項所述之半導體元件結構的形成方法，更包括部分地移除該隔離元件，而使該隔離元件的一較低的寬度大於該隔離元件的一較高的寬度。
  9. 如申請專利範圍第7或8項所述之半導體元件結構的形成方法，其中該功函數層共形地延伸於該第一鰭狀結構之上和該隔離元件的該側壁之上；以及該第二功函數層共形地延伸於該第二鰭狀結構之上和該隔離元件的一第二側壁之上。
TW104138902A 2015-05-29 2015-11-24 半導體元件結構及其形成方法 TWI584472B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US14/725,118 US9559205B2 (en) 2015-05-29 2015-05-29 Structure and formation method of semiconductor device structure

Publications (2)

Publication Number Publication Date
TW201642465A TW201642465A (zh) 2016-12-01
TWI584472B true TWI584472B (zh) 2017-05-21

Family

ID=57398944

Family Applications (2)

Application Number Title Priority Date Filing Date
TW104138902A TWI584472B (zh) 2015-05-29 2015-11-24 半導體元件結構及其形成方法
TW104139095A TWI591694B (zh) 2015-05-29 2015-11-25 半導體元件結構及其形成方法

Family Applications After (1)

Application Number Title Priority Date Filing Date
TW104139095A TWI591694B (zh) 2015-05-29 2015-11-25 半導體元件結構及其形成方法

Country Status (4)

Country Link
US (8) US9553090B2 (zh)
KR (1) KR101820211B1 (zh)
CN (1) CN106206687B (zh)
TW (2) TWI584472B (zh)

Families Citing this family (68)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9553090B2 (en) 2015-05-29 2017-01-24 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and formation method of semiconductor device structure
US9601567B1 (en) * 2015-10-30 2017-03-21 Taiwan Semiconductor Manufacturing Co., Ltd. Multiple Fin FET structures having an insulating separation plug
US9583486B1 (en) * 2015-11-19 2017-02-28 International Business Machines Corporation Stable work function for narrow-pitch devices
US9786563B2 (en) * 2015-11-23 2017-10-10 International Business Machines Corporation Fin pitch scaling for high voltage devices and low voltage devices on the same wafer
KR102532169B1 (ko) * 2015-12-22 2023-05-16 인텔 코포레이션 핀 기반 iii-v족/si 또는 ge cmos sage 통합
US9899520B2 (en) * 2015-12-22 2018-02-20 United Microelectronics Corp. Method for fabricating semiconductor device
EP3394897A4 (en) * 2015-12-26 2019-08-21 Intel Corporation GATE ISOLATION IN NON-PLANAR TRANSISTORS
TWI612674B (zh) * 2016-03-24 2018-01-21 台灣積體電路製造股份有限公司 鰭式場效電晶體及其製造方法
CN107305866A (zh) * 2016-04-25 2017-10-31 联华电子股份有限公司 半导体元件及其制作方法
EP3244447A1 (en) * 2016-05-11 2017-11-15 IMEC vzw Method for forming a gate structure and a semiconductor device
US10002937B2 (en) * 2016-06-08 2018-06-19 International Business Machines Corporation Shared metal gate stack with tunable work function
CN107680938B (zh) * 2016-08-01 2021-05-28 中芯国际集成电路制造(上海)有限公司 半导体装置的制造方法
DE102017128047B4 (de) 2017-04-24 2024-08-01 Taiwan Semiconductor Manufacturing Co., Ltd. Verfahren zur herstellung einer halbleitervorrichtung
US10263090B2 (en) 2017-04-24 2019-04-16 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US10354997B2 (en) * 2017-04-28 2019-07-16 Taiwan Semiconductor Manufacturing Company, Ltd. Method for manufacturing semiconductor device with replacement gates
CN108933137B (zh) 2017-05-19 2021-02-09 中芯国际集成电路制造(上海)有限公司 静态随机存储器及其制造方法
US10283503B2 (en) 2017-07-31 2019-05-07 Taiwan Semiconductor Manufacturing Co., Ltd. Metal gate structure and methods thereof
DE102017126027B4 (de) 2017-07-31 2022-02-24 Taiwan Semiconductor Manufacturing Co., Ltd. Metallgatestruktur und Verfahren
US10535654B2 (en) * 2017-08-30 2020-01-14 Taiwan Semiconductor Manufacturing Co., Ltd. Cut metal gate with slanted sidewalls
US10811320B2 (en) * 2017-09-29 2020-10-20 Taiwan Semiconductor Manufacturing Company, Ltd. Footing removal in cut-metal process
US10490458B2 (en) * 2017-09-29 2019-11-26 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of cutting metal gates and structures formed thereof
DE102018101016B4 (de) * 2017-09-29 2021-07-29 Taiwan Semiconductor Manufacturing Co., Ltd. Verfahren zum Schneiden von Metall-Gates und daraus gebildete Strukturen
CN109585293B (zh) * 2017-09-29 2021-12-24 台湾积体电路制造股份有限公司 切割金属工艺中的基脚去除
KR102271008B1 (ko) * 2017-10-27 2021-06-29 삼성전자주식회사 반도체 장치
US10978351B2 (en) 2017-11-17 2021-04-13 Taiwan Semiconductor Manufacturing Co., Ltd. Etch stop layer between substrate and isolation structure
US10546937B2 (en) * 2017-11-21 2020-01-28 Taiwan Semiconductor Manufacturing Co., Ltd. Structures and methods for noise isolation in semiconductor devices
US10903336B2 (en) * 2017-11-28 2021-01-26 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method of manufacturing the same
KR102544153B1 (ko) * 2017-12-18 2023-06-14 삼성전자주식회사 반도체 장치 및 그 제조 방법
US10461171B2 (en) * 2018-01-12 2019-10-29 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of semiconductor device with metal gate stacks
US10297668B1 (en) * 2018-01-22 2019-05-21 International Business Machines Corporation Vertical transport fin field effect transistor with asymmetric channel profile
US10153209B1 (en) * 2018-02-05 2018-12-11 Globalfoundries Inc. Insulating gate separation structure and methods of making same
KR102472136B1 (ko) 2018-03-12 2022-11-30 삼성전자주식회사 집적회로 소자
KR102553251B1 (ko) 2018-04-06 2023-07-06 삼성전자주식회사 반도체 장치 및 그 제조 방법
US11393674B2 (en) 2018-05-18 2022-07-19 Taiwan Semiconductor Manufacturing Company, Ltd. Forming low-stress silicon nitride layer through hydrogen treatment
KR102460847B1 (ko) 2018-05-25 2022-10-28 삼성전자주식회사 반도체 장치 및 그 제조 방법
KR102636464B1 (ko) 2018-06-12 2024-02-14 삼성전자주식회사 게이트 분리층을 갖는 반도체 소자 및 그 제조 방법
US11398477B2 (en) 2019-05-29 2022-07-26 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US10854603B2 (en) 2018-06-29 2020-12-01 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US11101348B2 (en) * 2018-07-25 2021-08-24 Globalfoundries U.S. Inc. Nanosheet field effect transistor with spacers between sheets
KR102559270B1 (ko) * 2018-07-31 2023-07-24 삼성전자주식회사 반도체 장치 및 그 제조 방법
CN110854194B (zh) * 2018-08-20 2023-12-12 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
US10872891B2 (en) * 2018-09-25 2020-12-22 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuits with gate cut features
US10916477B2 (en) 2018-09-28 2021-02-09 Taiwan Semiconductor Manufacturing Company, Ltd. Fin field-effect transistor devices and methods of forming the same
DE102019101555B4 (de) * 2018-09-28 2023-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Metall-gate-schneideform
KR20210057185A (ko) 2018-10-10 2021-05-20 도쿄엘렉트론가부시키가이샤 반도체 소자의 함입형 형상부를 저-저항률 금속으로 충전하기 위한 방법
US10985075B2 (en) 2018-10-11 2021-04-20 International Business Machines Corporation Gate formation scheme for n-type and p-type transistors having separately tuned threshold voltages
US11069791B2 (en) 2018-10-31 2021-07-20 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing semiconductor devices and semiconductor devices
US10872826B2 (en) * 2018-10-31 2020-12-22 Taiwan Semiconductor Manufacturing Company, Ltd. Fin field-effect transistor device and method
DE102019112519B4 (de) 2018-11-30 2023-02-09 Taiwan Semiconductor Manufacturing Company, Ltd. Verfahren zur herstellung eines halbleiter-bauelements
US10861746B2 (en) * 2018-11-30 2020-12-08 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing a semiconductor device
CN110098109B (zh) * 2019-05-14 2021-03-26 上海集成电路研发中心有限公司 金属栅极及其制造方法
US11043495B2 (en) 2019-05-29 2021-06-22 Samsung Electronics Co., Ltd. Integrated circuit semiconductor device and method of manufacturing the same
US11380793B2 (en) 2019-07-31 2022-07-05 Taiwan Semiconductor Manufacturing Company, Ltd. Fin field-effect transistor device having hybrid work function layer stack
US11335679B2 (en) 2019-08-02 2022-05-17 Samsung Electronics Co., Ltd. Semiconductor device and method of fabricating the same
US11189531B2 (en) 2019-08-23 2021-11-30 Taiwan Semiconductor Manufacturing Company, Ltd. Fin field-effect transistor device and method
US20210118874A1 (en) * 2019-10-21 2021-04-22 Nanya Technology Corporation Semiconductor device and method for fabricating the same
US12002715B2 (en) 2019-10-29 2024-06-04 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method
US11264478B2 (en) 2019-10-31 2022-03-01 Taiwan Semiconductor Manufacturing Company, Ltd. Transistors with reduced defect and methods forming same
US11245028B2 (en) * 2020-01-30 2022-02-08 Taiwan Semiconductor Manufacturing Co., Ltd. Isolation structures of semiconductor devices
US11387346B2 (en) 2020-04-24 2022-07-12 Taiwan Semiconductor Manufacturing Co., Ltd. Gate patterning process for multi-gate devices
US11355696B2 (en) 2020-06-12 2022-06-07 Taiwan Semiconductor Manufacturing Co., Ltd. Magnetic tunnel junction structures and related methods
US11699736B2 (en) 2020-06-25 2023-07-11 Taiwan Semiconductor Manufacturing Co., Ltd. Gate structure and method
US11538805B2 (en) 2020-06-29 2022-12-27 Taiwan Semiconductor Manufacturing Company, Ltd. Method of tuning threshold voltages of transistors
US11848239B2 (en) 2020-07-10 2023-12-19 Taiwan Semiconductor Manufacturing Co., Ltd. Patterning method and structures resulting therefrom
US11658216B2 (en) * 2021-01-14 2023-05-23 Taiwan Semiconductor Manufacturing Company, Ltd. Method and structure for metal gate boundary isolation
CN114975603A (zh) * 2021-02-22 2022-08-30 上海华力集成电路制造有限公司 N型mosfet
US20220415890A1 (en) * 2021-06-25 2022-12-29 Intel Corporation Integrated circuit structures having metal gates with tapered plugs
US20230009485A1 (en) * 2021-07-09 2023-01-12 Taiwan Semiconductor Manufacturing Co., Ltd. Gate Structure in Semiconductor Device and Method of Forming the Same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140242775A1 (en) * 2012-02-28 2014-08-28 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating finfets
US20150054029A1 (en) * 2011-09-24 2015-02-26 Taiwan Semiconductor Manufacturing Company, Ltd. Metal Gate Stack Having TaAlCN Layer

Family Cites Families (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6200860B1 (en) * 1999-05-03 2001-03-13 Taiwan Semiconductor Manufacturing Company Process for preventing the reverse tunneling during programming in split gate flash
US7141468B2 (en) 2003-10-27 2006-11-28 Texas Instruments Incorporated Application of different isolation schemes for logic and embedded memory
US20070066074A1 (en) 2005-09-19 2007-03-22 Nace Rossi Shallow trench isolation structures and a method for forming shallow trench isolation structures
KR100744684B1 (ko) 2006-06-01 2007-08-01 주식회사 하이닉스반도체 벌브형 리세스와 새들형 핀을 결합한 반도체소자 및 그의제조 방법
JP2009158813A (ja) 2007-12-27 2009-07-16 Elpida Memory Inc 半導体装置の製造方法、及び半導体装置
US8329521B2 (en) 2010-07-02 2012-12-11 Taiwan Semiconductor Manufacturing Company. Ltd. Method and device with gate structure formed over the recessed top portion of the isolation structure
JP2012099517A (ja) * 2010-10-29 2012-05-24 Sony Corp 半導体装置及び半導体装置の製造方法
US8421132B2 (en) * 2011-05-09 2013-04-16 International Business Machines Corporation Post-planarization UV curing of stress inducing layers in replacement gate transistor fabrication
US9184100B2 (en) 2011-08-10 2015-11-10 United Microelectronics Corp. Semiconductor device having strained fin structure and method of making the same
US8728881B2 (en) 2011-08-31 2014-05-20 Institute of Microelectronics, Chinese Academy of Sciences Semiconductor device and method for manufacturing the same
CN103077947A (zh) 2011-10-26 2013-05-01 中国科学院微电子研究所 具有双金属栅的cmos器件及其制造方法
WO2013095474A1 (en) 2011-12-21 2013-06-27 Intel Corporation Methods for forming fins for metal oxide semiconductor device structures
CN104160507B (zh) * 2011-12-28 2017-10-24 英特尔公司 在三栅极（finfet）工艺上集成多个栅极电介质晶体管的方法
US8586436B2 (en) 2012-03-20 2013-11-19 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming a variety of replacement gate types including replacement gate types on a hybrid semiconductor device
KR20140006204A (ko) 2012-06-27 2014-01-16 삼성전자주식회사 반도체 장치 및 그 제조 방법
US9589803B2 (en) 2012-08-10 2017-03-07 Taiwan Semiconductor Manufacturing Company, Ltd. Gate electrode of field effect transistor
KR20140034347A (ko) 2012-08-31 2014-03-20 삼성전자주식회사 반도체 장치 및 그 제조 방법
CN103928333B (zh) 2013-01-15 2019-03-12 中国科学院微电子研究所 半导体器件及其制造方法
KR102067171B1 (ko) * 2013-02-14 2020-01-16 삼성전자주식회사 반도체 장치 및 그 제조 방법
US9041125B2 (en) 2013-03-11 2015-05-26 Taiwan Semiconductor Manufacturing Company, Ltd. Fin shape for fin field-effect transistors and method of forming
US8846491B1 (en) * 2013-06-19 2014-09-30 Globalfoundries Inc. Forming a diffusion break during a RMG process
US9219153B2 (en) * 2013-08-21 2015-12-22 Globalfoundries Inc. Methods of forming gate structures for FinFET devices and the resulting semiconductor products
US9142566B2 (en) * 2013-09-09 2015-09-22 Freescale Semiconductor, Inc. Method of forming different voltage devices with high-K metal gate
US9306032B2 (en) * 2013-10-25 2016-04-05 United Microelectronics Corp. Method of forming self-aligned metal gate structure in a replacement gate process using tapered interlayer dielectric
US9553171B2 (en) 2014-02-14 2017-01-24 Taiwan Semiconductor Manufacturing Co., Ltd. Fin field effect transistor (FinFET) device and method for forming the same
US9406746B2 (en) * 2014-02-19 2016-08-02 International Business Machines Corporation Work function metal fill for replacement gate fin field effect transistor process
US9362180B2 (en) * 2014-02-25 2016-06-07 Globalfoundries Inc. Integrated circuit having multiple threshold voltages
CN105097513B (zh) * 2014-04-24 2019-09-03 中芯国际集成电路制造(北京)有限公司 一种半导体器件的制造方法、半导体器件和电子装置
KR102158962B1 (ko) * 2014-05-08 2020-09-24 삼성전자 주식회사 반도체 장치 및 그 제조 방법
US9263586B2 (en) 2014-06-06 2016-02-16 Taiwan Semiconductor Manufacturing Company, Ltd. Quantum well fin-like field effect transistor (QWFinFET) having a two-section combo QW structure
US9431296B2 (en) 2014-06-26 2016-08-30 International Business Machines Corporation Structure and method to form liner silicide with improved contact resistance and reliablity
KR102218547B1 (ko) 2014-06-26 2021-02-22 에스케이하이닉스 주식회사 반도체장치 및 그 제조 방법
US9373641B2 (en) 2014-08-19 2016-06-21 International Business Machines Corporation Methods of forming field effect transistors using a gate cut process following final gate formation
CN105575805B (zh) * 2014-10-08 2019-01-04 联华电子股份有限公司 半导体结构的制造方法
KR102217246B1 (ko) * 2014-11-12 2021-02-18 삼성전자주식회사 집적회로 소자 및 그 제조 방법
US9634018B2 (en) * 2015-03-17 2017-04-25 Silicon Storage Technology, Inc. Split gate non-volatile memory cell with 3D finFET structure, and method of making same
US9553090B2 (en) 2015-05-29 2017-01-24 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and formation method of semiconductor device structure

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150054029A1 (en) * 2011-09-24 2015-02-26 Taiwan Semiconductor Manufacturing Company, Ltd. Metal Gate Stack Having TaAlCN Layer
US20140242775A1 (en) * 2012-02-28 2014-08-28 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating finfets

Also Published As

Publication number Publication date
US20170133490A1 (en) 2017-05-11
US20160351700A1 (en) 2016-12-01
US11682716B2 (en) 2023-06-20
US9559205B2 (en) 2017-01-31
US9553090B2 (en) 2017-01-24
US10326005B2 (en) 2019-06-18
KR101820211B1 (ko) 2018-01-18
US9899271B2 (en) 2018-02-20
US20160351568A1 (en) 2016-12-01
US20190305115A1 (en) 2019-10-03
US20200312985A1 (en) 2020-10-01
US20170084499A1 (en) 2017-03-23
TW201642326A (en) 2016-12-01
US10014394B2 (en) 2018-07-03
US20180174925A1 (en) 2018-06-21
US10686059B2 (en) 2020-06-16
US10686060B2 (en) 2020-06-16
TWI591694B (zh) 2017-07-11
KR20160140312A (ko) 2016-12-07
CN106206687B (zh) 2020-01-14
TW201642465A (zh) 2016-12-01
US20180308956A1 (en) 2018-10-25
CN106206687A (zh) 2016-12-07

Similar Documents

Publication Publication Date Title
TWI584472B (zh) 半導體元件結構及其形成方法
US20230275142A1 (en) Structure of Semiconductor Device Structure Having Fins
US11670717B2 (en) Structure of S/D contact and method of making same
US10325816B2 (en) Structure and method for FinFET device
TWI419208B (zh) 半導體裝置的製造方法
US11830926B2 (en) Semiconductor device structure with metal gate stacks
US10068982B2 (en) Structure and formation method of semiconductor device structure with metal gate