TWI575739B - 半導體裝置及其形成方法 - Google Patents
半導體裝置及其形成方法 Download PDFInfo
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- TWI575739B TWI575739B TW104118367A TW104118367A TWI575739B TW I575739 B TWI575739 B TW I575739B TW 104118367 A TW104118367 A TW 104118367A TW 104118367 A TW104118367 A TW 104118367A TW I575739 B TWI575739 B TW I575739B
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- 239000004065 semiconductor Substances 0.000 title claims description 129
- 238000000034 method Methods 0.000 title claims description 53
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- 229910052707 ruthenium Inorganic materials 0.000 description 24
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Classifications
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- H—ELECTRICITY
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
- H01L29/0669—Nanowires or nanotubes
- H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41708—Emitter or collector electrodes for bipolar transistors
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41791—Source or drain electrodes for field effect devices for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
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Description
本發明是關於一種半導體裝置及其製造方法,特別是有關於一種具有包覆矽化物的鰭式場效電晶體和其製作方法。
隨著積體電路(Integrated Circuit,IC)在材料和設計上技術之進步,產生了幾代的積體電路(ICs),其中每一代具有比上一代更小更複雜的電路。在積體電路演進過程中,當其幾何尺寸縮小時,其功能密度(例如:每一晶片區域的互連裝置數量)普遍的增加。這種按比例縮小的過程,一般透過提高生產效益和降低相關成本,以提供其效益。
比例縮小亦會增加積體電路在加工和製造上的複雜度。為了實現這些進展,在積體電路的加工和製造上需要類似的發展,例如,引入鰭式場效電晶體(Fin Field-Effect Transistor,FinFET),以取代平面的電晶體。鰭式場效電晶體的結構與其製造方法正在發展中。
根據本發明一些實施方式,一半導體裝置包含:複數個隔離區域,延伸進入一半導體基板,在這些隔離區域的複數個相對部份之間有一具有一第一寬度的基板條;一源極/汲極區域,具有一重疊基板條的部分,其中源極/汲極區域的一上部具有一大於第一寬度的第二寬度,以及源極/汲極區域的上部具有實質上垂直的複數個側壁;以及一源極/汲極矽化區域,具有複數個內部側壁接觸源極/汲極區域的這些垂直的側壁。
根據本發明一些替代實施方式,一半導體裝置包含:複數個淺溝槽隔離區域;一半導體條,在這些淺溝槽隔離區域的相對部份之間;一氧化區域,重疊半導體條;以及一源極/汲極區域,重疊氧化區域,源極/汲極區域包含:一下部,其中半導體條的各複數個邊緣、氧化區域以及源極/汲極區域實質上對齊排列;以及一上部,在下部之上,其中上部包含實質上垂直的複數個側壁,以及上部側向延伸越過下部的各這些邊緣。
根據本發明另一些替代實施方式,一種形成半導體裝置的方法,包含:形成一半導體鰭片,突出複數個隔離區域的複數個上表面;形成一閘極疊層,覆蓋半導體鰭片的一中部,半導體鰭片的一末端部沒有被閘極疊層覆蓋;形成複數個介電模板在半導體鰭片的末端部的異側;蝕刻半導體鰭片的末端部,以在這些介電模板之間形成一凹槽;從凹槽長出一源極/汲極區域,其中源極/汲極區域在凹槽中包含一第一部分以及一第二部分在這些介電模板之上,第二部分
比第一部分更寬;以及修整第二部分以減少第二部分的一寬度。
20‧‧‧基板
21‧‧‧反穿透區域、反穿透層、反穿透層區域
22‧‧‧矽鍺層、矽鍺條、半導體層
24‧‧‧半導體疊層、半導體條、半導體鰭片
26‧‧‧半導體層、矽條、矽層、半導體條
28‧‧‧半導體層、矽鍺層、矽鍺條、半導體條
30‧‧‧硬遮罩
32‧‧‧溝渠
34‧‧‧半導體條
36‧‧‧氧化矽層
38‧‧‧矽鍺氧化區域
40‧‧‧矽鍺氧化區域
42‧‧‧淺溝渠隔離區域
42A‧‧‧上表面
44‧‧‧虛擬氧化層、虛擬閘極氧化物
46‧‧‧虛擬閘極疊層、虛擬閘極
48‧‧‧虛擬閘極電極、多晶矽層
50‧‧‧硬遮罩層
50A‧‧‧氮化矽層
50B‧‧‧氧化矽層
54‧‧‧閘極間隙壁
56‧‧‧凹槽
58‧‧‧源極/汲極區域、磊晶區域
58’‧‧‧小平面
58”‧‧‧小平面
58A、58B、58C、58D‧‧‧部份
60‧‧‧層間介電質
62‧‧‧凹槽
64‧‧‧間隙
66‧‧‧氧化矽環
70‧‧‧閘極介電質
72‧‧‧閘極電極
74‧‧‧鰭式場效電晶體
76‧‧‧氧化矽
78‧‧‧高k介電質
100‧‧‧核心區域
122‧‧‧蝕刻終止層
124‧‧‧半導體層
126‧‧‧介電層
128‧‧‧介電區域
130‧‧‧介電層
132‧‧‧介電層、介電模板、閘極間隙壁
136‧‧‧凹槽
138‧‧‧間隙
140‧‧‧閘極間隙壁
144‧‧‧矽化區域
146‧‧‧接觸插塞
148‧‧‧金屬
200‧‧‧IO區域
300‧‧‧步驟流程
302-328‧‧‧步驟
400‧‧‧步驟流程
402-426‧‧‧步驟
H1‧‧‧高度
△H‧‧‧高度差
T1-T5‧‧‧厚度
W1、W2‧‧‧寬度
16B/16C-16B/16‧‧‧剖線
21C/21D-21C/21D‧‧‧剖線
A-A‧‧‧剖線
本發明內容的實施方式可從下面的詳細描述並結合參閱附圖得到最佳的理解。要強調的是,按照在業界的標準實務做法,各種特徵不一定是按比例繪製。事實上,為了清楚的討論各種特徵的尺寸可任意放大或縮小。
第1-21D圖係根據一些示例式實施方式,繪示出形成一鰭式場效電晶體之中間階段的剖面圖和透視圖。
第22圖係根據一些實施方式,繪示出形成一鰭式場效電晶體的步驟流程圖。
第23A、23B及23C圖係根據一些實施方式,繪示出鰭式場效電晶體之通道區域及閘極疊層的剖面圖。
第24-40C圖係根據一些示例式實施方式,繪示出形成一鰭式場效電晶體的剖面圖、上視圖及透視圖。
第41圖係根據一些實施方式,繪示出形成一鰭式場效電晶體的步驟流程圖。
應該理解到,以下揭露的內容提供多種不同的實施方式或實例,用於實現本發明內容的不同特徵。元件和配置的具體實例描述如下以簡化本發明內容。當然,這些僅僅是例子而沒有進行限制的目的。此外,下面某一第一特徵
形成在一第二特徵之上的描述可包括的實施方式為第一和第二特徵直接接觸形成,也可包括其他特徵介於第一與第二特徵之間,使得第一和第二特徵可以不直接接觸。除此之外,本發明內容於各個實例中可能用到重複的參考符號及/或用字。這些重複符號或用字係為了簡化與清晰的目的,並非用以限定各個實施方式及/或所述結構之間的關係。
另外,空間相對用語,如「下」、「低」、「上」等,是用以方便描述一元件或特徵與其他元件或特徵在圖式中的相對關係。這些空間相對用語旨在包含除了圖式中所示之方位以外,裝置在使用或操作時的不同方位。裝置可被另外定位(例如旋轉90度或其他方位),而本文所使用的空間相對敘述亦可相對應地進行解釋。
根據各種的示例式實施方式,提供了一種具有環繞式閘極(Gate-All-Around,GAA)結構之鰭式場效電晶體(Fin Field-Effect Transistors,FinFETs)及其形成方法。以下介紹形成鰭式場效電晶體之中間階段,並討論實施方式的變化。在各個視圖及其繪示之實施方式中,相同的元件符號代表相同的元件。可以理解的是,雖然第1-23C圖及第24-40C圖繪示出不同實施方式,但這些實施方式可結合以形成同一鰭式場效電晶體。例如,如第1-23C圖所示之實施方式,包含鰭式場效電晶體之通道區域及閘極疊層的形成,而如第24-40C圖所示之實施方式,則包含鰭式場效電晶體之源極/汲極區域與源極/汲極矽化物的形成。因此,根據本發明的一些實施方式,可結合通道區域及閘極疊層的形
成,和源極/汲極區域與源極/汲極矽化物的形成,以形成一鰭式場效電晶體。
第1-21D圖係根據一些實施方式繪示出形成鰭式場效電晶體中間階段的透視圖與剖面圖。第1-21D圖所示之步驟亦於第22圖所示之步驟流程300中按綱要式說明。在後續的討論中,第1-21D圖中顯示的製程步驟,將參照第22圖所示之製程步驟討論。
第1圖繪示出有可能是晶圓一部分之基板20的剖面圖。基板20可能為一半導體基板,進一步可能為矽基板、碳矽基板、絕緣層覆矽基板、或利用其他半導體材料形成的基板。基板20可能利用p型或n型雜質做輕摻雜。進行反穿透(Anti-Punch-Through,APT)植入(如箭頭所指)於基板20的頂部以形成反穿透區域21。其各自的步驟呈現在第22圖中製程流程的步驟302。植入於反穿透層的雜質導電型態與阱區(未顯示)中的相同。反穿透層21延伸至之後形成的源極/汲極區域58(第21A圖)底下,用來減少從源極/汲極區域58到基板20的洩漏。反穿透層21的摻雜濃度可能在大約1E18/cm3至大約1E19/cm3之間。為了做更清楚的表達,反穿透層區域21不會繪示於之後的圖式中。
參考第2圖,矽鍺層(silicon germanium,SiGe)22與半導體疊層24用磊晶的方式形成於基板20之上方。其各自的步驟呈現在第22圖中製程流程的步驟304。如前所述,矽鍺層22與半導體疊層24形成結晶層。根據本發明一些實施方式,矽鍺層22之厚度T1在大約5奈米至大約8
奈米的範圍之間。矽鍺層22之鍺比例(原子比例)在大約25%至大約35%的範圍之間,但亦可使用其他更高或更低的比例。可以理解的是,然而,說明書中所述之數值皆為舉例說明,其均可改變為其他數值。
在矽鍺層22上方的是半導體疊層24。根據一些實施方式,半導體疊層24包含交互堆疊的半導體層26與28。半導體層26可為不含鍺的純矽層。半導體層26亦可為實質上的純矽層,舉例來說,其鍺比例低於大約1%。此外,半導體層26可為本質性,其不摻雜p型或n型的雜質。這裡可為二、三、四或多個半導體層26。根據一些實施方式,半導體層26的厚度T2在大約6奈米至大約12奈米的範圍之間。
半導體層28為矽鍺層,其具有的鍺比例,低於矽鍺層22中的鍺比例。根據本發明一些實施方式,矽鍺層28的鍺比例在大約10%至大約20%的範圍之間。除此之外,矽鍺層22與矽鍺層28之間鍺的比例可差異至15%或更高。根據一些實施方式,矽鍺層28的厚度T3在大約2奈米至大約6奈米的範圍之間。
硬遮罩30形成於半導體疊層24之上。根據本發明一些實施方式,硬遮罩30的形成係利用氮化矽、氮氧化矽、碳化矽、碳氮化矽、或其他相似物。
接下來,如第3圖所示,硬遮罩30、半導體疊層24、矽鍺層22與基板20圖案化以形成溝渠32。其各自的步驟呈現在第22圖中製程流程的步驟306。因此而形成半導
體條34。溝渠32延伸進入基板20且具有一長度方向彼此平行。半導體疊層24剩下的部分可相應地以半導體條24之名詞來替換。
參照第4圖,於半導體條34暴露出之部分,進行氧化製程。其各自的步驟呈現在第22圖中製程流程的步驟308。根據本發明一些實施方式,在氧化之前,進行修整步驟以修整矽鍺條22與28,而矽條26不修整。矽鍺層22與28經過修整後,各自在矽條26邊緣形成側向凹槽。修整可以減少矽鍺層22的寬度,使其在之後的氧化過程中,矽鍺層22可以在不增加太多的時間及/或溫度之情況下就被完全氧化。
氧化的結果造成,矽鍺層22完全氧化以形成矽鍺氧化區域38,以及至少外部部分的矽鍺條28氧化以形成矽鍺氧化區域40。矽鍺氧化區域38之厚度可在大約5奈米至大約20奈米的範圍之間。在一些實施方式中,進行氧化的溫度可在大約400℃至600℃的範圍之間。氧化的時間,舉例來說,可在大約2分鐘至大約4小時的範圍之間。氧化矽鍺中之矽,會比氧化相同矽鍺中之鍺來得容易。因此,半導體條28中的矽原子被氧化,且半導體條28中之鍺原子可向內朝向矽鍺條28的中心擴散,所以剩下的矽鍺條28中之鍺比例,比矽鍺條28氧化之前多。
氧化的過程中,氧化矽層36亦形成於基板20與矽條26所暴露出之表面上。由於矽鍺(或矽)區域的氧化速率隨著鍺比例的增加而增加,矽層26與基板20的氧化會比矽
鍺層22與矽鍺條28的氧化慢得多。因此,氧化矽層36較薄,且半導體條34中大部分的矽層26與部分的基板20(參照在下文中的部分條)未被氧化。
接下來參照第5圖,隔離區域42形成於溝渠32之中(第4圖),且其可為淺溝渠隔離(Shallow Trench Isolation,STI)區域。形成的方式可包含填充介電層於溝渠32中,舉例來說,利用可流動式化學氣相沉積(Flowable Chemical Vapor Deposition,FCVD),再進行化學機械研磨(Chemical Mechanical Polish,CMP)以夷平介電材料之上表面和硬遮罩30之上表面。經過化學機械研磨後,硬遮罩30(第4圖)已被移除。
接下來,參照第6圖,凹槽化淺溝渠隔離區域42。第5、6圖所示之步驟顯示於第22圖中製程流程的步驟310。處理完的淺溝渠隔離區域42之上表面42A可與矽鍺氧化區域38之上表面、下表面平齊,或位於矽鍺氧化區域38上表面與下表面中間的任何水平高度。在說明書中,以下半導體疊層24亦可參做為半導體鰭片24。
第7圖繪示出虛擬氧化層44的形成,根據一些實施方式可包含氧化矽。故虛擬氧化層44保護半導體條24的側壁、矽鍺氧化區域38與半導體疊層24的上表面。虛擬氧化層44亦延伸至淺溝渠隔離區域42的上表面。由於虛擬氧化層44與淺溝渠隔離區域42可用相同介電材料(例如氧化矽)形成,因此雖然在一些實施方式中可區別,但虛擬氧化層44與淺溝渠隔離區域42之間的界面仍未顯示出來。在
其他實施方式中,此界面無法區別。
參照第8圖,形成虛擬閘極疊層46。其各自的步驟呈現在第22圖中製程流程的步驟312。根據本發明一些實施方式,虛擬閘極疊層46包含虛擬閘極電極48,舉例來說,其可利用多晶矽形成。虛擬閘極疊層46亦可包含在虛擬閘極電極48上方的硬遮罩層50。硬遮罩層50可包含氮化矽及/或氧化矽,舉例來說,亦可為單層或包含複數層的複合層。在一些實施方式中,硬遮罩層50包含氮化矽層50A與在氮化矽層50A上方的氧化矽層50B。虛擬閘極疊層46具有一長度方向,實質上垂直於半導體鰭片24之長度方向。
閘極間隙壁54形成在虛擬閘極疊層46的側壁。根據本發明一些實施方式,閘極間隙壁54係利用氮化矽形成並可為單層結構。在替代的實施方式中,閘極間隙壁54具有包含複數層的複合結構。舉例來說,閘極間隙壁54可包含氧化矽層及位於氧化矽層上方的氮化矽層。虛擬閘極疊層46與閘極間隙壁54覆蓋每一半導體鰭片24的中間部分,保留相對兩端部分未被覆蓋。
第9圖繪示出移除半導體鰭片24的端部。如第8圖所示,進行乾蝕刻以蝕刻虛擬氧化層44、半導體疊層24與矽鍺氧化區域38。結果可形成凹槽56。根據本發明一些實施方式,虛擬氧化層44的一些部分可被豎立與排列在淺溝渠隔離區域42的邊緣,並於其之間形成凹槽56。
接下來參照第10圖,將半導體材料選擇性生長於凹槽56(第9圖)中以形成磊晶區域(源極/汲極區域)58。根
據本發明一些實施方式,源極/汲極區域58的形成包含磊晶生長。根據替代的實施方式,形成源極/汲極區域58的完成係透過採取如第28-37A圖所示之製程步驟。其各自的步驟呈現在第22圖中製程流程的步驟314。如第10圖所示,由於虛擬氧化層44剩下部份的阻擋,源極/汲極區域58在凹槽56(第9圖)中,會優先垂直生長,而在此期間,源極/汲極區域58不水平生長。在凹槽56完全填滿後,源極/汲極區域58會朝垂直及水平方向生長以形成複數個小平面。
在一些示例式的實施方式中,其所產生的鰭式場效電晶體為n型鰭式場效電晶體,源極/汲極區域58包含矽磷(silicon phosphorous,SiP)或磷摻雜碳化矽(phosphorous-doped silicon carbon,SiCP)。在替代示例式的實施方式中,其所產生的鰭式場效電晶體為n型鰭式場效電晶體,源極/汲極區域58包含矽鍺,以及p型雜質例如硼或銦,可於磊晶時同步摻雜。
接下來如第11圖所示,形成層間介電質(Inter-Layer Dielectric,ILD)。其各自的步驟呈現在第22圖中製程流程的步驟316。進行化學機械研磨將層間介電質60、虛擬閘極疊層46(第10圖)與閘極間隙壁54(第10圖)的上表面磨平至相同高度。每個層間介電質60、閘極間隙壁54與隔離區域42與其他層間介電質60、閘極間隙壁54與淺溝渠隔離區域42可以具有可區別的界面,因為其形成於不同的製程步驟、具有不同密度、及/或包含不同介電材料。
接下來,第10圖中所示之虛擬閘極46在蝕刻步
驟中被移除,使凹槽62可形成延伸進入層間介電質60如第11圖所示。其各自的步驟呈現在第22圖中製程流程的步驟318。為了繪示層間介電質60前面部分後面的特徵,前面部分的層間介電質60沒有在之後的圖中顯示,以便繪示其內部的特徵。可以理解的是,層間介電質60未繪示出的部分依然存在。將虛擬閘極疊層46移除後,半導體疊層(鰭片)24的中間部分向凹槽62暴露出來。在移除虛擬閘極疊層46的時候,當上層被蝕刻時,虛擬閘極氧化物44(第7圖)被用來當作蝕刻終止層。而後移除虛擬閘極氧化物44,半導體鰭片24因此向凹槽62暴露出來。
參照第12A圖,進行一蝕刻步驟以移除矽鍺氧化區域40(亦參照第9圖)、集中的半導體條28與矽鍺氧化區域38(第8圖)的一些頂部。其各自的步驟呈現在第22圖中製程流程的步驟320。因此,矽條26藉由間隙64將彼此分開。此外,位於底部之矽條26亦可藉由間隙64,將其與剩下之矽鍺氧化區域38分離,結果產生懸浮之矽條26。懸浮矽條26之相對兩端連接至源極/汲極區域58。可以理解的是,淺溝渠隔離區域42包含在下面且向凹槽62暴露出來的第一部分,和被閘極間隙壁54與層間介電質60覆蓋的第二部分。根據本發明一些實施方式,凹槽化淺溝渠隔離區域42第一部分,使其上表面低於淺溝渠隔離區域42第二部分之上表面。
第12B圖將矽條26之部分較清晰的繪示出。第12A圖所示之層間介電質60、源極/汲極區域58與閘極間隙
壁54雖然未於第12B圖中顯示,但其特徵依然存在。
參照第13A與13B圖,進行氧化步驟。其各自的步驟呈現在第22圖中製程流程的步驟322。第13B圖亦繪示出第13A圖所示之結構的一些部份,其中第13A圖所示之層間介電質60、源極/汲極區域58與閘極間隙壁54雖然未於第13B圖中顯示,但其特徵依然存在。根據本發明一些實施方式,氧化步驟的進行可利用水蒸氣的蒸氣氧化、氧的熱氧化或其他類似方法。根據本發明一些實施方式,氧化步驟係利用水蒸氣在溫度介於大約400℃至大約600℃的範圍之間進行。氧化步驟持續的時間可介於大約20秒至大約20分的範圍之間。如第13B圖所示,氧化步驟完成後,矽條26之外部部分會被氧化以形成氧化矽環66,環繞於矽條26之剩下部分。在一些實施方式中,氧化矽環66係從鄰近的矽條26相互接觸而形成。此外,在一些實施方式中,氧化矽環66係形成於位於底部之矽條26,且可與矽鍺氧化區域38之上表面接觸。在替代的實施方式中,氧化矽環66係形成於鄰近之矽條26間,且可將其彼此間隔開。
在氧化步驟中,核心電路(亦稱為邏輯電路)中之核心鰭式場效電晶體與輸入/輸出(input/output,IO)電路中之輸入/輸出(input/output,IO)鰭式場效電晶體,分別具有其各自之半導體條,而該半導體條會同時氧化。第13A、13B圖繪示出核心鰭式場效電晶體與IO鰭式場效電晶體之結構。在後續步驟中,如第14A圖所示,形成光阻68以覆蓋IO區域200之氧化矽環66,但核心區域100未被覆
蓋。而後進行蝕刻以移除核心區域100中之氧化矽環66,使矽條26暴露出。另一方面,IO區域200中之氧化矽環66未被移除,因此於蝕刻後仍能保留下來。其各自的步驟呈現在第22圖中製程流程的步驟324。而後將光阻68移除。在蝕刻後,位於核心區域100之矽條26再藉由間隙將彼此分開,而位於底部之矽條26亦可藉由間隙,將其與矽鍺氧化區域38之上表面間隔開。第14B圖繪示出第14A圖所示結構之一些部分,其中第14A圖所示之層間介電質60、源極/汲極區域58與閘極間隙壁54雖然未於第14B圖中顯示,但其特徵依然存在。
在後續步驟中,形成閘極介電質70。其各自的步驟呈現在第22圖中製程流程的步驟326。對於在核心區域(第14A、14B圖中之100)中之核心鰭式場效電晶體,閘極介電質70形成於矽條26暴露出的表面之上(第14A、14B圖)。最後之結構顯示於第15A、15B圖。對於IO區域(第14A、14B圖中之200)中之IO鰭式場效電晶體,閘極介電質70形成於已形成之氧化矽環66之上,因此氧化矽環66成為閘極介電質70之一部分。因此,核心鰭式場效電晶體與IO鰭式場效電晶體具有顯示於第15A及15B圖之結構,其中IO鰭式場效電晶體的閘極介電質70,較核心鰭式場效電晶體的閘極介電質70來得厚。再者,第15B圖亦繪示出第15A圖所示結構之一些部分,其中第15A圖所示之層間介電質60、源極/汲極區域58與閘極間隙壁54未於第14B圖中顯示。
根據一些實施例,閘極介電質70之形成包含完成一界面(介電質)層,而後形成高k介電質層於界面層之上。界面層可包含氧化矽,氧化矽之形成係利用化學溶液處理第14A及14B圖中所示之結構,使矽條26被氧化以形成化學氧化物(氧化矽)。結果所產生的IO區域中之閘極介電質70,將比位於核心區域之閘極介電質來得厚。接著,高k介電質沉積於介面層之上。在一些實施方式中,高k介電質具有大於約7.0的k值,且可包含金屬氧化物或鉿(Hf)、鋁(Al)、鋯(Zr)、鑭(La)之矽酸鹽(silicate),以及其他類似物。
第16A圖繪示出閘極電極72的形成。其各自的步驟呈現在第22圖中製程流程的步驟328。此形成的步驟包含將導電材料填入凹槽62,以及進行平坦化例如化學機械研磨。閘極電極72可包括含金屬材料例如氮化鈦(TiN)、氮化鉭(TaN)、碳化鉭(TaC)、鈷(Co)、釕(Ru)、鋁(Al)、銅(Cu)、鎢(W)、其組合物或其多層組合。鰭式場效電晶體74因此而形成。反穿透區域21位於矽鍺氧化區域38與源極/汲極區域58之下方。
第16B、16C圖繪示出第16A圖所示鰭式場效電晶體74之一些部分的剖面圖,其中該剖面圖係從第16A圖中垂直平面之16B/16C-16B/16C剖線而得到的。如第16B、16C圖所示,閘極介電質70完全填入位於鄰近矽條26間之間隙。因此,閘極電極72將無法填入位於鄰近矽條26間之間隙,且不會導致源極/汲極區域58的短路(第16A圖)。
第16B、16C圖亦繪示出閘極介電質70包含氧化矽76和位於氧化矽76外側之高k介電質78。當鰭式場效電晶體74為核心鰭式場效電晶體,氧化矽76包含界面層。當鰭式場效電晶體74為IO鰭式場效電晶體,氧化矽76包含氧化矽環66(第13A、13B圖)與界面層。根據一些實施方式,在第16B圖中,氧化矽76形成於鄰近矽條26之上且彼此相互接觸。根據一些實施方式,在第16C圖中,氧化矽76形成鄰近矽條26之上但不會彼此接觸,且高k介電質78填入位於氧化矽76間之間隙,而前述之氧化矽76係形成於鄰近矽條26之上。
根據一些替代的實施方式,第17A-22圖繪示出形成鰭式場效電晶體中間階段的剖面圖。除非另有說明,在這些實施方式中的元件,其材料及形成方法實質上與類似元件相同,而類似元件在第1-16C圖所示之實施方式中皆以相同的元件符號表示。關於第17A-22圖所示結構之詳細形成步驟與材料,可參考第1-16C圖所示之實施方式的說明。
如第1-11圖所示,這些實施方式的起始步驟實質上相同。接著,第17A、17B圖繪示出類似於第12A、12B圖所示之蝕刻步驟。參考第17A圖,進行蝕刻以移除矽鍺氧化區域40(亦參考第9圖)、集中的半導體條28與矽鍺氧化區域38(第8圖)的一些頂部。因此,矽條26藉由間隙64將彼此分開。此外,位於底部之矽條26亦可藉由間隙64,將其與剩下之矽鍺氧化區域38分離。將其與第12A、12B圖所示之步驟比較,其中部分的淺溝渠隔離區域42與矽鍺氧化區域
38之凹槽深度較第12A、12B圖來得深。結果造成,矽條26底部與矽鍺氧化區域38上表面之間的間隙64高於第12A、12B圖所示。
接著,第18A、18B圖分別繪示出與第13A、13B圖實質上相同之製程步驟與結構,其中包含氧化步驟的進行以及氧化矽環66的形成。位於底部的氧化矽環66可藉由間隙64,將其與矽鍺氧化區域38之上表面間隔開。第19A、19B圖繪示出與第14A、14B圖實質上相同之製程步驟與結構,其中包含從核心裝置區域移除氧化矽環66。在此同時,IO區域(未顯示)中之氧化矽環66會被保護而不會被移除。第20A、20B圖繪示出與第15A、15B圖實質上相同之製程步驟與結構,其中包含閘極介電質70的形成。第21A、21B圖繪示出與第16A、16B圖實質上相同之製程步驟與結構,其中包含閘極電極72的形成。
第21C、21D圖繪示出第21A圖所示鰭式場效電晶體74之一些部分的剖面圖,其中該剖面圖係從第21A圖中垂直平面之21C/21D-21C/21D剖線而得到的。如第21C、21D圖所示,閘極介電質70完全填入位於鄰近矽條26間之間隙。因此,閘極電極72將無法填入位於鄰近矽條26間之間隙,且不會導致源極/汲極區域58的短路(第16A圖)。
如第17A、17B圖所示,因為淺溝槽隔離區域42與矽鍺氧化區域38較深的凹槽化,使淺溝槽隔離區域42與矽鍺氧化區域38更遠離其上方之矽條26。如第21C、21D圖所示,至少一些矽鍺氧化區域38的上表面,會與形成於
矽條26底部之閘極介電質70間隔開。在第21C圖中,矽鍺氧化區域38的中央部份具有較少的凹槽化,因而會突出高於矽鍺氧化區域38相對於中央部分的相對側部分。閘極介電質70填入矽鍺氧化區域38中央部分與矽條26底部之間的空間。在第21D圖中,形成於矽條26底部之閘極介電質可藉由間隙,將其與形成於矽鍺氧化區域38和淺溝槽隔離區域42之上表面的介電質(亦標示為70)間隔開。而閘極電極72則填入該間隙。
第23A、23B及23C圖係根據替代的實施方式繪示出鰭式場效電晶體之通道與閘極的剖面圖。在這些實施方式中,以二代替三或四之矽條26。此外,半導體條26具有一高度大於其各自的寬度。舉例來說,每一矽條26之高度H1可為介於大約10nm至大約30nm之間的範圍,且每一矽條26之寬度W1可為介於大約6nm至大約12nm之間的範圍。第23A、23B及23C圖繪示出一些各自對應於第16B/16C、21C及1D之實施方式,因此其詳細說明在此便不再重複。
本發明一些實施方式具有一些優勢特徵。在通道材料(矽條26)的形成之前進行反穿透植入。於是,所產生之鰭式場效電晶體的通道不會受到植入之摻雜物的影響。因此可以消除,傳統的反穿透植入所導致的雜質散射與載子遷移率降低之問題。所產生之鰭式場效電晶體為一種具有複數個通道之環繞式閘極鰭式場效電晶體(GAA FinFET)。因此,可改善汲極引致能障下降(Drain-Induced Barrier
Lowering,DIBL)相關的短通道效應。此外,因為複數個通道,亦可改善鰭式場效電晶體的驅動電流。
根據一些替代的實施方式,第24-40C圖繪示出形成鰭式場效電晶體中間階段的剖面圖。除非另有說明,在這些實施方式中的元件,其材料及形成方法實質上與類似元件相同,而類似元件在第1-23C圖所示之實施方式中皆以相同的元件符號表示。關於第24-40C圖所示結構之詳細形成步驟與材料,可參考第1-23C圖所示之實施方式的說明。第24-40C圖所示之步驟亦於第41圖所示之步驟流程400中按綱要式說明。
第24圖繪示出反穿透植入(如箭頭所指)的形成以於基板20中以形成反穿透區域21。其各自的步驟呈現在第41圖中製程流程的步驟402。製程步驟和製程細節與第1圖所示實質上相同,因此其詳細說明在此便不再重複。
接下來如第25圖所示,矽鍺層22與半導體層124用磊晶的方式形成於基板20之上方。其各自的步驟呈現在第41圖中製程流程的步驟404。如前所述,矽鍺層22形成結晶層。矽鍺層22之鍺比例(原子比例)在大約25%至大約35%的範圍之間,但亦可使用其他更高或更低的比例。根據本發明一些實施方式,矽鍺層22之厚度T4在大約5奈米至大約8奈米的範圍之間。
半導體層124形成於矽鍺層22之上。根據本發明一些實施方式,半導體層124可為由均質的半導體材料所形成的單層,舉例來說,半導體層124的形成係利用不含鍺
的矽。半導體層124亦可為實質上的純矽層,舉例來說,其鍺比例低於大約1%。此外,半導體層124可為本質性,其不摻雜p型或n型的雜質。根據一些實施方式,半導體層124的厚度T4在大約30奈米至大約80奈米的範圍之間。
根據本發明一些替代的實施方式,半導體層124可為複合結構,其為具有實質上與第2圖所示之半導體疊層24相同結構的半導體疊層,因此,複合半導體層124的結構和材料可參考半導體疊層24的描述。
此外,硬遮罩(未顯示)可形成於半導體疊層124之上。根據本發明一些實施方式,硬遮罩的形成係利用氮化矽、氮氧化矽、碳化矽、碳氮化矽、或其他相似物。
接下來,如第26圖所示,硬遮罩、半導體層124、矽鍺層22與基板20圖案化以形成溝渠32。其各自的步驟呈現在第41圖中製程流程的步驟406。因此而形成半導體條34。溝渠32延伸進入基板20,且溝渠32和半導體條34具有彼此平行的長度方向。半導體層124剩下的部分可相應地以條之名詞來替換。在後續步驟中,溝渠32被淺溝渠隔離區域42填滿,接著凹槽化淺溝渠隔離區域42。在第26圖和之後的圖中,沒有顯示淺溝渠隔離區域42和基板20的下部,在半導體層22之下的結構部分實質上與第6圖所示結構的下部相同,基板20的部份(參照在下文中的基板條)位於淺溝渠隔離區域42的相對部份之間。
在淺溝渠隔離區域42的凹槽化之後,淺溝渠隔離區域42的上表面低於矽鍺條22的上表面。根據本發明一
些實施方式,淺溝渠隔離區域42的上表面平齊於或略低於矽鍺條22的上表面,使矽鍺條22的側壁的至少一些部份和可能全部的部份暴露出來。
接下來參照第27圖,在半導體條(鰭片)34暴露出之部分,進行氧化製程以形成矽鍺氧化區域38。其各自的步驟呈現在第41圖中製程流程的步驟408。氧化步驟完成後,矽鍺層22被完全氧化以形成矽鍺氧化區域38。根據一些實施方式,進行氧化的溫度可在大約400℃至600℃的範圍之間。氧化的時間,舉例來說,可在大約2分鐘至大約4小時的範圍之間。氧化的過程中,氧化矽(未顯示)亦形成於半導體條124暴露出之表面上。因為矽的氧化速率會比矽鍺的氧化速率慢得多,在半導體條124上的氧化矽層會較薄,因此,在此便不再說明。
在一些實施方式中,半導體條124具有如第3圖所示之半導體條24相同的結構。在氧化後,最後之結構將包含矽鍺氧化區域38、集中的矽鍺區域28,與第4圖所示之相似。
接下來參照第28-30圖,形成蝕刻終止層(Etch Stop Layer)122。其各自的步驟呈現在第41圖中製程流程的步驟410。在接觸開口的後續形成中,以蝕刻終止層122充當蝕刻終止層,接觸開口是為了形成源極/汲極矽化物和源極/汲極接觸。根據本發明一些實施方式,蝕刻終止層122包含氮碳化矽(SiCN),然而也可使用其他介電材料。蝕刻終止層122可具有厚度在大約3奈米至大約10奈米的範圍之
間。
參照第28圖,蝕刻終止層122形成為保形層(Conformal Layer),因此覆蓋半導體鰭片124的側壁和上表面以及矽鍺氧化區域38的的上表面。根據一些實施方式,蝕刻終止層122之厚度T5在大約3奈米至大約10奈米的範圍之間。
接下來參照第29圖,形成介電區域128以填充溝渠32(第28圖)。舉例來說,可以使用可流動式化學氣相沉積進行填充。根據一些實施方式,介電區域128可包含氧化矽。剩下之介電區域128的上表面高於矽鍺氧化區域38的上表面。
第29圖亦繪示出蝕刻終止層122暴露出之部分的氧化,使蝕刻終止層122暴露出之部分轉變成介電層126。當蝕刻終止層122由氮碳化矽形成,剩下之介電層包含氮碳氧化矽(SiOCN),其具有與碳氮化矽不同的蝕刻特性,此外,使用濕蝕刻時,氮碳氧化矽比氮碳化矽更容易被移除。因此,這樣的轉變可在不破壞半導體鰭片124的情況下移除蝕刻終止層122暴露出之部分。根據本發明一些實施方式,蝕刻終止層122的氧化步驟的進行可利用爐退火(Furnace Anneal)(在含氧氣體中)、氧植入(Oxygen Implantation)、或其它相似物。
形成介電層126之後,舉例來說,以溼蝕刻移除介電層126,最後之結構顯示於第30圖,結果造成,半導體鰭片124暴露出來,蝕刻終止層122之未轉變的部分維持
原樣。在剖面圖中,蝕刻終止層122剩下的部分具有U型(也包含L型)。根據本發明一些實施方式,剩下的蝕刻終止層122之上表面齊高於或高於矽鍺氧化區域38之上表面,使蝕刻終止層122亦能在為了形成接觸開口的後續蝕刻之中,保護矽鍺氧化區域38。在最後之結構中,蝕刻終止層122的垂直部分可具有一部分與矽鍺氧化區域38共平面,又或是,蝕刻終止層122的垂直部分可高於矽鍺氧化區域38。
第31圖繪示出虛擬閘極疊層46的形成的上視圖,虛擬閘極疊層形成在半導體鰭片124的上表面和側壁上。其各自的步驟呈現在第41圖中製程流程的步驟412。虛擬閘極疊層46的剖面圖可實質上與第34B圖所示之相同,此時,沒有閘極間隙壁形成在虛擬閘極疊層46的側壁上。根據一些實施方式,虛擬閘極疊層包含虛擬閘極電極48,舉例來說,虛擬閘極電極48可利用多晶矽形成。虛擬閘極疊層46亦可包含硬遮罩層50。舉例來說,硬遮罩層50可包含氮化矽層50A和在氮化矽層50A之上的氧化矽層50B。虛擬閘極疊層46具有一長度方向,實質上垂直於半導體鰭片124之長度方向,其中,半導體鰭片124的相對兩端未被虛擬閘極疊層46覆蓋。
第32-38B圖繪示源極和汲極區域的形成(參照在下文中的源極/汲極區域),第32-38圖的圖示編號後有字母「A」或字母「B」,其中字母「A」表示各自的圖示得自於與含有第31圖的剖線A-A的垂直平面一樣的平面,字母「B」表示各自的圖示(除了第34B圖)得自於與含有第31
圖的線B-B的垂直平面一樣的平面,因此,圖示編號後有字母「A」繪示源極/汲極區域的剖面圖,圖示編號後有字母「B」繪示虛擬閘極疊層46的剖面圖。
第32-34B圖繪示為了磊晶生長源極/汲極區域的源極/汲極模板的形成。其各自的步驟呈現在第41圖中製程流程的步驟414。參照第32圖,形成介電層130,接著形成介電層132在介電層130之上。介電層130和132的材料是不同的,根據一些實施方式,介電層132的形成係利用氮碳氧化矽,介電層130的形成係利用不同於介電層132的材料,舉例來說,在一些實施方式中,介電層130的形成係利用氧化矽。介電層130的形成具有增加最後的源極/汲極區域寬度的優勢特徵,將在後續的段落中討論。形成介電層130和132為保形層,因此亦將在虛擬閘極疊層的側壁(如第34B圖所示)和上表面之上延伸。
第33圖繪示出透過蝕刻移除半導體鰭片124,其中,被移除的部分沒有被虛擬閘極疊層46(第31圖)覆蓋。在蝕刻中,也移除介電層130和132在半導體鰭片124之上的一些部分,在半導體鰭片124的蝕刻之後,矽鍺氧化區域(第32圖)亦被蝕刻,因此形成源極/汲極凹槽136延伸至淺溝渠隔離區域42之間的基板20的一些部分上,凹槽136具有實質上垂直的側壁,其側壁包含介電層130和蝕刻終止層122的側壁。根據一些實施方式,蝕刻為非等方向性的。
接下來,進行蝕刻步驟移除介電層130,最後之結構顯示於第34A、34B圖,其分別繪示源極/汲極區域
的剖面圖、源極/汲極區域和虛擬閘極疊層46的側視圖。蝕刻可為等方向性的,舉例來說,使用溼蝕刻。結果,增加凹槽136的側向寬度超過第33圖中所示,這可有利於增加後續在凹槽136中生長的源極/汲極區域的寬度。此外,介電層132(參照在下文中的介電模板132)之剩下部分的下表面藉由間隙138與下面的介電區域128相隔。因此產生懸浮之介電模板132。
如第34B圖之透視圖所示,介電模板132連接至在虛擬閘極疊層46側壁上的介電層132的一些部份,因此不會脫落,同樣的,在虛擬閘極疊層46側壁上的介電層130的一些部份仍能保留下來,且暴露於凹槽136。
在後續的步驟中,如第34A圖和第34B圖所示,源極/汲極區域磊晶生長在凹槽136之中。其各自的步驟呈現在第41圖中製程流程的步驟416。間隙138(第34B圖)的存在,使前驅物(Precursor)容易到達凹槽136的底部和內部,因此,最後之源極/汲極區域較不可能有孔洞(Void)。第35圖繪示最後之源極/汲極區域58,最後之源極/汲極區域的材料和形成步驟與第10圖所示之類似,因此在此便不再重複。源極/汲極區域58包含具有垂直側壁的部份58A,具有小平面58’和58”的部份58B,介於蝕刻終止層122和形成在間隙138(第34A圖)中的部份58D之間的部份58C。
第36A-37B圖繪示源極/汲極區域58的修整,使第35圖中的小平面58’和58”被移除以形成垂直的源極/
汲極區域58。其各自的步驟呈現在第41圖中製程流程的步驟418。參照第36A圖,形成介電層140。根據一些實施方式,介電層140的形成係利用與介電層132一樣的材料,舉例來說,其可包含氮碳氧化矽。如第36B圖所示,其繪示虛擬閘極疊層46以及介電層140,介電層140亦形成在虛擬閘極疊層46上且接觸介電層132。
接下來,如第37A-37B圖所示,進行乾蝕刻以蝕刻介電層140重疊於源極/汲極區域58的一些部份,使源極/汲極區域58暴露出來。接著進行修整步驟,舉例來說,使用非等方向性(乾)蝕刻,以移除源極/汲極區域58的小平面。最後的結構如第38A-38B圖所示,分別繪示出源極/汲極部份和虛擬閘極疊層。因為修整源極/汲極,最後之源極/汲極區域58具有實質上垂直的側壁,沒有任何實質上的小平面保留下來。暴露出來的源極/汲極區域58的側壁為實質上垂直且平直的。接下來,進行乾蝕刻移除介電層132和140在源極/汲極區域58側壁上的部份,蝕刻終止層122因此暴露出來。在此同時,如第38B圖所示,虛擬閘極疊層46的上表面亦暴露出來,介電層132和140之剩下部份形成閘極間隙壁132/140,可以理解的是,因為介電層132和140在不同的流程步驟中形成,兩者可具有可區分的界面,無論此兩者是否以相同或不同的材料形成。介電層140的形成有利於增加閘極間隙壁的厚度,使第38B圖的結構中,閘極間隙壁132/140的上部末端高於多晶矽層48的上表面,在最後之結構中,閘極間隙壁132/140之厚度在大約3奈米至大約10奈
米的範圍之間。
接下來,如第39A-39B圖所示,形成層間介電質60。其各自的步驟呈現在第41圖中製程流程的步驟420。進行化學機械研磨將層間介電質60、虛擬閘極疊層46與閘極間隙壁132/140的上表面磨平至相同高度。在後續步驟中,如第40A圖所示,移除虛擬閘極疊層46(第39B圖),閘極介電質(未顯示)和閘極電極72形成替代閘極。其各自的步驟呈現在第41圖中製程流程的步驟422。在一些實施方式中,半導體鰭片124(第34B圖)的形成係利用均質的材料。替代閘極的形成包含形成界面介電質層和高k介電質層在半導體鰭片124(第34B圖)的側壁和上表面之上;形成導電材料在高k介電質層之上;以及進行化學機械研磨使界面介電質層、高k介電質層以及導電材料的上表面與層間介電質60之上表面平齊。在替代的實施方式中,其中半導體鰭片124具有如第2圖所示之半導體疊層24所示之相同結構,可進行第11-16B圖所示之步驟以形成替代閘極。
再次參照第40A圖,在形成替代閘極之後,蝕刻層間介電質60以形成接觸開口(被如第40A和40B所示之接觸插塞146填滿),其中源極/汲極區域58暴露於接觸開口。在層間介電質60的蝕刻中,蝕刻終止層122做為保護下面的淺溝渠隔離區域42的蝕刻終止層。蝕刻終止層122的上部末端可高於矽鍺氧化區域38的上部末段,高度差為△H,可在大約2奈米至大約5奈米的範圍之間,使矽鍺氧化區域38受到恰當的保護而不被蝕刻。根據本發明一些實施方
式,如第40A圖所示,蝕刻終止層122的大部分高於矽鍺氧化區域38。在替代的實施方式中,如第30圖所示,蝕刻終止層122和矽鍺氧化區域38的大部分彼此齊平。
接下來,進行矽化步驟以形成源極/汲極矽化區域144在源極/汲極區域58的側壁上,接著以導電材料填充剩下之接觸開口以形成源極/汲極接觸插塞146。其各自的步驟呈現在第41圖中製程流程的步驟424和426。根據本發明一些實施方式,矽化區域包含矽化鎳、矽化鈦、矽化鈷、或其他類似物。接觸插塞146可包含鈷、鎢、或其他類似物。如第40A圖所示,因此形成鰭式場效電晶體74。
根據各種實施方式,第40B圖和第40C圖繪示鰭式場效電晶體74的源極/汲極部分的剖面圖,其中剖面圖得自第40A圖中的含有剖線A-A的平面。在第40B圖中,在矽化步驟之後,移除用以形成矽化金屬的剩下之金屬,因此,接觸插塞146接觸矽化區域144。在第40C圖中,用以形成矽化金屬的剩下之金屬148沒有被移除,金屬148包含鎳、鈦、鈷、或其他類似物。
本發明一些實施方式具有一些優勢特徵。如第40B圖所示,相鄰的淺溝渠隔離區域42具有距離W1,其為介於淺溝渠隔離區域42之間的基板20的條部分之寬度,源極/汲極區域58有寬度為W1的下部58C,源極/汲極區域58進一步具有寬度為W2的上部58A/58B,寬度W2大於W1。舉例來說,寬度W1可為介於大約2nm至大約6nm之間的範圍,寬度W2可為介於大約6nm至大約12nm之間的範圍,寬
度差(W2-W1)的產生是由於介電層130(第32圖)的形成和移除,因此,源極/汲極區域的寬度是優勢地大於下面的基板部分的寬度,此外,藉由形成介電模板,從模板形成源極/汲極區域,然後修整源極/汲極區域,使最後之源極/汲極區域可具有很高的高度,但仍具有垂直側壁。因此,矽化區域可形成在源極/汲極區域的高且垂直的側壁上,因此,減少源極/汲極接觸電阻,導致最後之鰭式場效電晶體的飽和電流增加。
根據本發明一些實施方式,一半導體裝置包含:複數個隔離區域,延伸進入一半導體基板,在這些隔離區域的複數個相對部份之間有一具有一第一寬度的基板條;一源極/汲極區域,具有一重疊基板條的部分,其中源極/汲極區域的一上部具有一大於第一寬度的第二寬度,以及源極/汲極區域的上部具有實質上垂直的複數個側壁;以及一源極/汲極矽化區域,具有複數個內部側壁接觸源極/汲極區域的這些垂直的側壁。
根據本發明一些替代實施方式,一半導體裝置包含:複數個淺溝槽隔離區域;一半導體條,在這些淺溝槽隔離區域的相對部份之間;一氧化區域,重疊半導體條;以及一源極/汲極區域,重疊氧化區域,源極/汲極區域包含:一下部,其中半導體條的各複數個邊緣、氧化區域以及源極/汲極區域實質上對齊排列;以及一上部,在下部之上,其中上部包含實質上垂直的複數個側壁,以及上部側向延伸越過下部的各這些邊緣。
根據本發明另一些替代實施方式,一種形成半導體裝置的方法,包含:形成一半導體鰭片,突出複數個隔離區域的複數個上表面;形成一閘極疊層,覆蓋半導體鰭片的一中部,半導體鰭片的一末端部沒有被閘極疊層覆蓋;形成複數個介電模板在半導體鰭片的末端部的異側;蝕刻半導體鰭片的末端部,以在這些介電模板之間形成一凹槽;從凹槽長出一源極/汲極區域,其中源極/汲極區域在凹槽中包含一第一部分以及一第二部分在這些介電模板之上,第二部分比第一部分更寬;以及修整第二部分以減少第二部分的一寬度。
前面已概述了一些實施方式的特徵,使得本技術領域中具有通常知識者可以更佳理解其中的詳細描述。本技術領域中具有通常知識者應當理解,其可以容易使用本發明內容作為用於實現相同目的及/或實現本文中所介紹的實施方式中相同的優點設計或修改其他過程和結構基礎。本技術領域中具有通常知識者也應該認識到,此類等效構造不脫離本發明內容中所揭露的精神和範圍,並且可以對其進行各種改變,替代和變更,而不脫離本發明內容之精神和範圍。
20‧‧‧基板
42‧‧‧淺溝渠隔離區域
58‧‧‧源極/汲極區域、磊晶區域
72‧‧‧閘極電極
74‧‧‧鰭式場效電晶體
122‧‧‧蝕刻終止層
132‧‧‧介電層、介電模板、閘極間隙壁
140‧‧‧閘極間隙壁
144‧‧‧矽化區域
146‧‧‧接觸插塞
Claims (10)
- 一半導體裝置,包含:複數個隔離區域,延伸進入一半導體基板,在該些隔離區域的複數個相對部份之間有一具有一第一寬度的基板條;一源極/汲極區域,具有一重疊該基板條的部分,其中該源極/汲極區域的一上部具有一大於該第一寬度的第二寬度,以及該源極/汲極區域的該上部具有實質上垂直的複數個側壁;以及一源極/汲極矽化區域,具有複數個內部側壁接觸該源極/汲極區域的該些垂直的側壁。
- 如請求項1所述之半導體裝置,進一步包含:一介電蝕刻終止層,包含:一水平部分,具有一下表面接觸該些隔離區域的一上表面;以及一垂直部分,包含一底部末端連接該水平部分的一末端,其中該源極/汲極區域包含一側壁接觸該介電蝕刻終止層的該垂直部分的一內部側壁。
- 如請求項2所述之半導體裝置,進一步包含一具有一側壁之接觸插塞,包含:一上部,接觸該源極/汲極矽化區域的一外部側壁;以及 一下部,接觸該介電蝕刻終止層的該垂直部份的該垂直部份的一外部側壁。
- 一半導體裝置,包含:複數個淺溝槽隔離區域;一半導體條,在該些淺溝槽隔離區域的複數個相對部份之間;一氧化區域,重疊該半導體條;以及一源極/汲極區域,重疊該氧化區域,該源極/汲極區域包含:一下部,其中該半導體條的各複數個邊緣、該氧化區域以及該源極/汲極區域實質上對齊排列;以及一上部,在該下部之上,其中該上部包含實質上垂直的複數個側壁,以及該上部側向延伸越過該下部的各該些邊緣。
- 如請求項4所述之半導體裝置,進一步包含一介電蝕刻終止層,包含在該源極/汲極區域的該下部的相對側的複數個部分,其中該介電蝕刻終止層的複數個側壁接觸該源極/汲極區域的該下部的複數個側壁。
- 如請求項5所述之半導體裝置,其中該介電蝕刻終止層包含:一下部接觸該淺溝槽隔離區域的一上表面;以及一上部與該下部形成一L型。
- 如請求項6所述之半導體裝置,進一步包含一接觸插塞接觸該介電蝕刻終止層的該下部的一側壁以及該介電蝕刻終止層的該上部的一上表面。
- 如請求項4所述之半導體裝置,其中該源極/汲極區域由一鰭式場效電晶體組成。
- 一種形成半導體裝置的方法,包含:形成一半導體鰭片,突出於複數個隔離區域的複數個上表面;形成一閘極疊層,覆蓋該半導體鰭片的一中部,該半導體鰭片的一末端部沒有被該閘極疊層覆蓋;形成複數個介電模板在該半導體鰭片的該末端部的相對側;蝕刻該半導體鰭片的該末端部,以在該些介電模板之間形成一凹槽;從該凹槽長出一源極/汲極區域,其中該源極/汲極區域在該凹槽中包含一第一部分以及一第二部分在該些介電模板之上,該第二部分比該第一部分更寬;以及修整該第二部分以減少該第二部分的一寬度。
- 如請求項9所述之方法,進一步包含形成一介電蝕刻終止層,包含:形成一保形介電層在該半導體鰭片的複數個側壁上; 形成一介電區域接觸該保形介電層的一下部的一側壁;以及移除在該介電區域的一上表面之上的該保形介電層的複數個部分,其中該保形介電層的一剩餘部分低於該介電區域的該上表面,形成該介電蝕刻終止層。
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US20190355850A1 (en) | 2019-11-21 |
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KR20160099447A (ko) | 2016-08-22 |
KR101709400B1 (ko) | 2017-02-22 |
US9991388B2 (en) | 2018-06-05 |
TW201601311A (zh) | 2016-01-01 |
US11211498B2 (en) | 2021-12-28 |
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