CN109494190B - 一种鳍式场效应半导体的形成方法 - Google Patents

一种鳍式场效应半导体的形成方法 Download PDF

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CN109494190B
CN109494190B CN201710812750.2A CN201710812750A CN109494190B CN 109494190 B CN109494190 B CN 109494190B CN 201710812750 A CN201710812750 A CN 201710812750A CN 109494190 B CN109494190 B CN 109494190B
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CN109494190A (zh
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周飞
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Beijing Corp
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Abstract

一种半导体结构的形成方法，包括：形成半导体基底，所述半导体基底包括衬底、凸出于所述衬底的鳍部，所述衬底包括第一区域和第二区域，凸出于所述第一区域衬底的鳍部为第一鳍部，凸出于所述第二区域衬底的鳍部为第二鳍部；所述第二鳍部包括牺牲层，以及覆盖所述牺牲层的半导体层；首先，采用蒸汽原位生成以及去耦等离子氮处理工艺形成第一伪栅氧化层；然后，在第二鳍部表面形成第二伪栅氧化层。本发明的半导体结构形成方法，避免采用蒸汽原位生成(ISSG)以及去耦等离子氮处理(DPN)工艺对包含牺牲层的鳍部氧化处理时，牺牲层中的物质向半导体层渗透迁移使得其性能变差。

Description

一种鳍式场效应半导体的形成方法
技术领域
本发明涉及半导体领域，尤其涉及一种鳍式场效应半导体的形成方法。
背景技术
在半导体制造中，随着超大规模集成电路的发展趋势，集成电路特征尺寸持续减小。为了适应特征尺寸的减小，MOSFET场效应管的沟道长度也相应不断缩短。然而，随着器件沟道长度的缩短，器件源极与漏极间的距离也随之缩短，因此栅极对沟道的控制能力随之变差，栅极电压夹断(pinch off)沟道的难度也越来越大，使得亚阈值漏电(subthreshold leakage)现象，即所谓的短沟道效应(SCE：short-channel effects)更容易发生。
因此，为了更好的适应特征尺寸的减小，半导体工艺逐渐开始从平面MOSFET晶体管向具有更高功效的三维立体式的晶体管过渡，如鳍式场效应管(FinFET)。FinFET中，栅至少可以从两侧对超薄体(鳍部)进行控制，具有比平面MOSFET器件强得多的栅对沟道的控制能力，能够很好的抑制短沟道效应；且FinFET相对于其他器件，具有更好的现有的集成电路制作技术的兼容性。为了不断提高电流的驱动能力且抑制短沟道效应，传统鳍式场效应管已经难以满足工艺节点不断减小的需求，因此环栅((GAA，Gate-Al l-Around)场效应管的概念被提出，环栅场效应管的应用，能够获得更大的集成度，且有效的改善短沟道效应问题。
其中，FinFET器件通常包括核心器件(Core)和输入输出器件(IO)，在器件制备过程中核心器件和输入输出器件需要形成不同的结构，核心器件采用环栅，在其制备过程中，为了保证输入输出器件(IO)的性能，通常采用蒸汽原位生成(ISSG)以及去耦等离子氮处理(DPN)工艺同时对输入输出器件和核心器件的鳍部进行处理形成伪栅氧化层，这种高温热氧处理容易导致核心器件鳍部中牺牲层中的物质向半导体层渗透迁移，从而影响鳍式场效应管的性能。
发明内容
本发明的目为：形成包含环栅器件的FINFET，当采用蒸汽原位生成(ISSG)以及去耦等离子氮处理(DPN)工艺对鳍部进行处理形成伪栅氧化层时，由于高温热氧处理容易导致用于形成环栅器件的鳍部牺牲层中的物质渗透迁移，而影响其性能的问题，提供如下的技术方案：
一种半导体结构的形成方法，包括：形成半导体基底，所述半导体基底包括衬底、凸出于所述衬底的鳍部，所述衬底包括第一区域和第二区域，凸出于所述第一区域衬底的鳍部为第一鳍部，凸出于所述第二区域衬底的鳍部为第二鳍部；所述第二鳍部包括牺牲层，以及覆盖所述牺牲层的半导体层；采用蒸汽原位生成以及去耦等离子氮处理工艺在第一鳍部表面形成第一伪栅氧化层；在第二鳍部表面形成第二伪栅氧化层。
优选的，在第二鳍部表面形成第二伪栅氧化层的工艺为原子层沉积工艺。
优先的，所述衬底上形成有覆盖所述鳍部的氧化介质层，首先，去除第一区域的部分氧化介质层露出部分第一鳍部，采用蒸汽原位生成以及去耦等离子氮处理工艺在第一鳍部表面形成第一伪栅氧化层；然后，去除第二区域的部分氧化介质层露出部分第二鳍部，在第二鳍部表面形成第二伪栅氧化层。
优选的，所述牺牲层的材料为锗硅。
优选的，所述牺牲层中，锗的质量百分占比为30％～85％。
优选的，所述半导体层的材料为硅。
优选的，所述第一鳍部的材料为硅。
优选的，形成第二伪栅氧化层的原子层沉积工艺的工艺条件为：向原子层沉积室内通入的前驱体为含硅/氧前驱体，工艺温度为80～300℃，压强为500mTorr～10Torr,沉积次数为5～50次。
优选的，所述蒸汽原位生成以及去耦等离子氮处理工艺的工艺条件为：等离子体处理功率为300～600W等离子体处理压强为10～30mTorr,等离子体处理气体为N2/He,其中N2流量为50～120SCCM,He流量为80～150SCCM。
优选的，所述第一区域用于形成输入输出器件；所述第二区域用于形成核心器件。
优选的，在所述去除第二区域的部分氧化介质层之前，在第一伪栅氧化层上形成保护层。
优选的，形成所述保护层的工艺为原子层沉积工艺。
优选的，所述半导体基底的材料为硅。
优选的，去除第一区域的部分氧化介质层的工艺包括，在第二区域的氧化介质层表面形成掩膜层，刻蚀去除第一区域的部分氧化介质层。
优选的，形成所述第二鳍部的方法包括：将所述半导体基底的第二区域衬底以上的基底材料去除，形成牺牲层和半导体层，然后刻蚀处理形成第二鳍部。
优选的，采用外延生长工艺形成所述牺牲层和半导体层。
优选的，还包括：在第二鳍部形成环栅结构。
优选的，在第二鳍部形成第二伪栅结构，去除第二伪栅结构的伪栅极形成第二开口，去除牺牲层在半导体层之间形成层间隧道，在所述第二开口及层间隧道的内壁依次形成高K栅介质层、功函数金属层以及栅电极金属层从而形成所述的环栅结构。
优选的，所述高K栅介质层、功函数金属层以及栅电极金属层采用原子层沉积工艺形成。
与现有技术相比，本发明的技术方案具有以下优点：
本发明的鳍式场效应半导体的形成方法，采用不同的工艺方法形成鳍部的伪栅氧化层，避免采用蒸汽原位生成(ISSG)以及去耦等离子氮处理(DPN)工艺对包含牺牲层的鳍部氧化处理时，牺牲层中的物质向半导体层渗透迁移，使得其性能变差。
附图说明
图1至图9为一种鳍式场效应半导体的形成方法各步骤对应的结构示意图。
图10至图26为本发明鳍式场效应半导体的形成方法一实施例中各步骤对应结构示意图。
具体实施方式
图1至图9为一种鳍式场效应半导体的形成方法各步骤对应的结构示意图。参考图1到9，所述鳍式场效应半导体的形成方法包括以下步骤：
参考图1，形成半导体基底100；所述半导体基底100包括第一区域Ⅰ和第二区域Ⅱ，所述第一区域Ⅰ用于形成输入输出(IO)器件，所述第二区域Ⅱ用于形成核心(Core)器件。
参考图2，在所述半导体基底上形成盖帽层120。
参考图3，对所述第二区域Ⅱ部分基底材料进行刻蚀去除。
参考图4，对所述第二区域Ⅱ部分刻蚀去除形成的缺口，采用外延生长的方式依次形成相互间隔的硅锗牺牲层131(SiGe)、硅半导体层132(Si)。
参考图5，在上述外延生长完成后，对其平坦化处理，然后形成氮化硅(SiN)盖帽层140。
参考图6，刻蚀所述半导体基底100形成衬底110，在所述第一区域Ⅰ和第二区域Ⅱ分别形成第一鳍部和第二鳍部，从而所述第二鳍部包括相互间隔的硅锗牺牲层131(SiGe)、硅半导体层132(Si)。
参考图7，在所述衬底110上形成氧化介质层，所述氧化介质层包括线形氧化层151以及充满沟槽的氧化填充层152。
参考图8，刻蚀去除第一区域Ⅰ和第二区域Ⅱ的部分氧化介质层，露出部分第一鳍部和部分第二鳍部。
参考图9，采用蒸汽原位生成以及去耦等离子氮处理工艺在露出的部分第一鳍部形成第一伪栅氧化层，采用蒸汽原位生成以及去耦等离子氮处理工艺在露出的部分第二鳍部形成第二伪栅氧化层。
如图9所示，采用蒸汽原位生成以及去耦等离子氮处理工艺在露出的部分第一鳍部形成第一伪栅氧化层，可以保证在第一区域形成的输入输出器件的可靠性，但是，当采用蒸汽原位生成以及去耦等离子氮处理工艺在露出的部分第二鳍部形成第二伪栅氧化层，由于所述工艺需要采取高温热氧化，在这个过程中，容易导致锗硅牺牲层中的锗渗透迁移至硅半导体层中，从会使该区域形成的核心器件的性能表差。
为解决上述问题，本发明提供一种半导体结构的形成方法，包括：形成半导体基底，所述半导体基底包括衬底、凸出于所述衬底的鳍部，所述衬底包括第一区域和第二区域，凸出于所述第一区域衬底的鳍部为第一鳍部，凸出于所述第二区域衬底的鳍部为第二鳍部；所述第二鳍部包括牺牲层，以及覆盖所述牺牲层的半导体层；采用蒸汽原位生成以及去耦等离子氮处理工艺在第一鳍部表面形成第一伪栅氧化层；然后，在第二鳍部形成第二伪栅氧化层，考虑到便于工艺控制，优选为采用原子层沉积工艺在第二鳍部形成第二伪栅氧化层。
本发明的半导体结构的形成方法，采用蒸汽原位生成以及去耦等离子氮处理工艺在第一鳍部表面形成第一伪栅氧化层；采用原子层沉积工艺在第二鳍部表面形成第二伪栅氧化层。由于在第二鳍部表面，采用原子层沉积工艺而非蒸汽原位生成以及去耦等离子氮处理工艺形成第二伪栅氧化层，可以避免前述的蒸汽原位生成以及去耦等离子氮处理工艺过程中高温热氧化所引起的锗硅牺牲层中的锗渗透迁移至硅半导体层中。
为使本发明的上述目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。
图10至图26为本发明鳍式场效应半导体的形成方法一实施例中各步骤对应结构示意图。
参考图16-21，形成半导体基底200，所述半导体基底200包括衬底210、凸出于所述衬底210的鳍部，所述衬底210包括第一区域Ⅰ和第二区域Ⅱ，凸出于所述第一区域Ⅰ衬底的鳍部为第一鳍部，凸出于所述第二区域Ⅱ衬底的鳍部为第二鳍部；所述第二鳍部包括牺牲层231，以及覆盖所述牺牲层231的半导体层232；采用蒸汽原位生成以及去耦等离子氮处理工艺在第一鳍部表面形成第一伪栅氧化层260；采用原子层沉积工艺在第二鳍部表面形成第二伪栅氧化层262。
本实施例中，所述牺牲层231为两层，在其它的实施例中，所述牺牲层231可以是一层或三层及以上。
所述半导体基底200可以为硅半导体基底、硅锗半导体基底、碳化硅半导体基底、绝缘体上硅(SOI)半导体基底、绝缘体上锗(GOI)半导体基底、玻璃半导体基底或III-V族化合物半导体基底(例如氮化硅或砷化镓等)等等。本实施例中，所述半导体基底200的材料为硅。
所述第一鳍部的材料包括硅、锗、锗化硅、碳化硅、砷化镓或镓化铟。本实施例中，所述第一鳍部的材料为硅。
所述第二鳍部半导体层232的材料包括硅、锗、锗化硅、碳化硅、砷化镓或镓化铟，所述第二鳍部牺牲层231的材料为不同于半导体层的易于后续去除的材料。本实施例中，所述半导体层232的材料为硅，所述牺牲层231的材料为锗硅，为便于后续牺牲层的进一步去除，所述牺牲层中，锗的质量百分占比为30％～85％。
本实施例中，所述蒸汽原位生成以及去耦等离子氮处理工艺的工艺条件为：向原子层沉积室内通入的前驱体为含硅/氧前驱体，工艺温度为80～300℃，压强为500mTorr～10Torr,沉积次数为5～50次。
本实施例中，形成第二伪栅氧化层的原子层沉积工艺的工艺条件为：等离子体处理功率为300～600W等离子体处理压强为10～30mT,等离子体处理气体为N2/He,其中N2流量为50～120SCCM,He流量为80～150SCCM。
本实施例中，所述第一区域Ⅰ用于形成输入输出器件；所述第二区域Ⅱ用于形成核心器件。
本实施例中，参考图16，在所述衬底210上形成有覆盖所述鳍部的氧化介质层252，参考图17，首先，去除第一区域Ⅰ的部分氧化介质层252露出部分第一鳍部，参考图18，采用蒸汽原位生成以及去耦等离子氮处理工艺在第一鳍部表面形成第一伪栅氧化层260；参考图20，然后，去除第二区域Ⅱ的部分氧化介质层252露出部分第二鳍部，参考图21，采用原子层沉积工艺在第二鳍部表面形成第二伪栅氧化层262。
所述氧化介质层252材料包括但不限于氧化硅、氮氧化硅或氢氧化硅，本实施例中为氧化硅。
本实施例中，参考图19，在去除第二区域Ⅱ的部分氧化介质层之前，在第一伪栅氧化层260上形成保护层261。
所述保护层261的材料包括但不限于氧化硅、氮氧化硅或氢氧化硅，本实施例中为氧化硅。
形成所述保护层261的方法为沉积工艺，如原子层沉积工艺、低压化学气相沉积工艺或等离子体增强化学气相沉积工艺，本实施例中为原子层沉积工艺。
本实施例中，去除第一区域Ⅰ的部分氧化介质层252的工艺包括，在第二区域Ⅱ的氧化介质层252表面形成掩膜层，刻蚀去除第一区域Ⅰ的部分氧化介质层252。接着，还包括：去除所述掩膜层。
本实施例中，去除第二区域Ⅱ的部分氧化介质层252的工艺包括，在第一区域Ⅰ的氧化介质层252以及第一鳍部表面形成掩膜层，刻蚀去除第二区域Ⅱ的部分氧化介质层252。接着，还包括：去除所述掩膜层。
本实施例中，所述掩膜层的材料为光刻胶，采用湿法去胶或灰化工艺去除所述掩膜层。
本实施例中，参考图11至图15，形成所述第二鳍部的方法包括：将所述半导体基底200的第二区域Ⅱ衬底210以上的基底材料去除，形成牺牲层231和半导体层232，然后刻蚀处理形成第二鳍部。具体如下：
参考图11，形成半导体基底200；所述半导体基底200包括第一区域Ⅰ和第二区域Ⅱ，所述第一区域Ⅰ用于形成输入输出(IO)器件，所述第二区域Ⅱ用于形成核心(Core)器件，在所述半导体基底上形成盖帽层220。
参考图12，对所述第二区域Ⅱ部分基底材料进行刻蚀去除。
参考图13，对所述第二区域Ⅱ部分刻蚀去除形成的缺口，采用外延生长的方式依次形成相互间隔的牺牲层231和半导体层232。
参考图14，在上述外延生长完成后，对其平坦化处理，然后形成氮化硅(SiN)盖帽层240。
参考图15，刻蚀所述半导体基底200形成衬底210，在所述第一区域Ⅰ和第二区域Ⅱ分别形成第一鳍部和第二鳍部，从而所述第二鳍部包括相互间隔的牺牲层231和半导体层232。
本发明的半导体结构的形成方法，还包括：在第二鳍部形成环栅结构。
参考图22至图26，本实施例中，在第二鳍部形成第二伪栅结构，去除第二伪栅结构的伪栅极形成第二开口281，去除牺牲层231在半导体层232之间形成层间隧道282，在所述第二开口281及层间隧道282的内壁依次形成高K栅介质层、功函数金属层以及栅电极金属层290从而形成所述的环栅结构。
具体方法如下：
参考图22，在第二鳍部形成第二源漏区270、第二伪栅结构、以及鳍部之间的沟槽中填充的氧化介质层，所述第二伪栅结构包括第二伪栅极280。所述第二源漏区270的形成步骤包括：在所述伪栅极结构两侧的衬底内形成沟槽；采用外延工艺在所述沟槽内形成应力层；在所述应力层内掺杂离子以形成第二源漏区270。所述鳍部之间的沟槽中填充的氧化介质层形成步骤包括：在鳍部之间的沟槽中沉积填充氧化介质层直至没过第二伪栅极280，平坦化该沉积填充的氧化介质层直至露出第二伪栅极280。
参考图23，去除第二伪栅结构的第二伪栅极280形成第二开口281，去除第二伪栅电极的工艺为刻蚀工艺。
参考图24，刻蚀去除鳍部之间的沟槽中填充的氧化介质层直至所述牺牲层231完全暴露。
参考图25，将第二鳍部牺牲层231以外的表面形成掩膜层，刻蚀去除第二鳍部牺牲层231，形成层间隧道282。接着，还包括：去除所述掩膜层。所述掩膜层的材料为光刻胶，采用湿法去胶或灰化工艺去除所述掩膜层。
参考图26，在所述第二开口281及层间隧道282的内壁依次形成高K栅介质层、功函数金属层以及栅电极从而形成所述的环栅结构。所述高k栅介质层的材料为相对介电常数大于氧化硅相对介电常数的栅介质材料。所述高k栅介质层的材料可以为HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、ZrO2或Al2O3等。所述功函数金属层为P型功函数金属层或N型功函数金属层。所述栅电极金属层290的材料为W，其也可以为Al、Cu、Ag、Au、Pt、Ni、Ti等。
本实施例中，所述高K栅介质层、功函数金属层以及栅电极金属层290采用原子层沉积工艺形成，在其它实施例中也可以采用采用化学气相沉积、物理气相沉积等工艺。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (17)

1.一种半导体结构的形成方法，其特征在于，包括：
形成半导体基底，所述半导体基底包括衬底、凸出于所述衬底的鳍部，所述衬底包括第一区域和第二区域，凸出于所述第一区域衬底的鳍部为第一鳍部，凸出于所述第二区域衬底的鳍部为第二鳍部；
所述第二鳍部包括牺牲层，以及覆盖所述牺牲层的半导体层；
采用蒸汽原位生成以及去耦等离子氮处理工艺在第一鳍部表面形成第一伪栅氧化层；
在第二鳍部表面形成第二伪栅氧化层，在第二鳍部表面形成第二伪栅氧化层的工艺为原子层沉积工艺；
所述衬底上形成有覆盖所述鳍部的氧化介质层，首先，去除第一区域的部分氧化介质层露出部分第一鳍部，采用蒸汽原位生成以及去耦等离子氮处理工艺在第一鳍部表面形成第一伪栅氧化层；然后，去除第二区域的部分氧化介质层露出部分第二鳍部，在第二鳍部表面形成第二伪栅氧化层。
2.根据权利要求1所述的半导体结构的形成方法，其特征在于，所述牺牲层的材料为锗硅。
3.根据权利要求2所述的半导体结构的形成方法，其特征在于，所述牺牲层中，锗的质量百分占比为30％～85％。
4.根据权利要求1所述的半导体结构的形成方法，其特征在于，所述半导体层的材料为硅。
5.根据权利要求1所述的半导体结构的形成方法，其特征在于，所述第一鳍部的材料为硅。
6.根据权利要求1所述的半导体结构的形成方法，其特征在于，形成第二伪栅氧化层的原子层沉积工艺的工艺条件为：向原子层沉积室内通入的前驱体为含硅/氧前驱体，工艺温度为80～300℃，压强为500mTorr～10Torr,沉积次数为5～50次。
7.根据权利要求1所述的半导体结构的形成方法，其特征在于，所述蒸汽原位生成以及去耦等离子氮处理工艺的工艺条件为：等离子体处理功率为300～600W等离子体处理压强为10～30mTorr,等离子体处理气体为N2/He,其中N2流量为50～120SCCM,He流量为80～150SCCM。
8.根据权利要求1所述的半导体结构的形成方法，其特征在于，所述第一区域用于形成输入输出器件；所述第二区域用于形成核心器件。
9.根据权利要求1所述的半导体结构的形成方法，其特征在于，在去除第二区域的部分氧化介质层之前，在第一伪栅氧化层上形成保护层。
10.根据权利要求9所述的半导体结构的形成方法，其特征在于，形成所述保护层的工艺为原子层沉积工艺。
11.根据权利要求1所述的半导体结构的形成方法，其特征在于，所述半导体基底的材料为硅。
12.根据权利要求1所述的半导体结构的形成方法，其特征在于，去除第一区域的部分氧化介质层的工艺包括，在第二区域的氧化介质层表面形成掩膜层，刻蚀去除第一区域的部分氧化介质层。
13.根据权利要求1所述的半导体结构的形成方法，其特征在于，形成所述第二鳍部的方法包括：将所述半导体基底的第二区域衬底以上的基底材料去除，形成牺牲层和半导体层，然后刻蚀处理形成第二鳍部。
14.根据权利要求13所述的半导体结构的形成方法，其特征在于，采用外延生长工艺形成所述牺牲层和半导体层。
15.根据权利要求1所述的半导体结构的形成方法，其特征在于，还包括：在第二鳍部形成环栅结构。
16.根据权利要求15所述的半导体结构的形成方法，其特征在于，在第二鳍部形成第二伪栅结构，去除第二伪栅结构的伪栅极形成第二开口，去除牺牲层在半导体层之间形成层间隧道，在所述第二开口及层间隧道的内壁依次形成高K栅介质层、功函数金属层以及栅电极金属层从而形成所述的环栅结构。
17.根据权利要求16所述的半导体结构的形成方法，其特征在于，所述高K栅介质层、功函数金属层以及栅电极金属层采用原子层沉积工艺形成。
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