TWI574363B - 晶片封裝體 - Google Patents

晶片封裝體 Download PDF

Info

Publication number
TWI574363B
TWI574363B TW100123745A TW100123745A TWI574363B TW I574363 B TWI574363 B TW I574363B TW 100123745 A TW100123745 A TW 100123745A TW 100123745 A TW100123745 A TW 100123745A TW I574363 B TWI574363 B TW I574363B
Authority
TW
Taiwan
Prior art keywords
wafer
chip package
top surface
layer
wire
Prior art date
Application number
TW100123745A
Other languages
English (en)
Other versions
TW201304099A (zh
Inventor
吳開文
Original Assignee
鴻海精密工業股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 鴻海精密工業股份有限公司 filed Critical 鴻海精密工業股份有限公司
Priority to TW100123745A priority Critical patent/TWI574363B/zh
Priority to US13/220,715 priority patent/US20130010444A1/en
Publication of TW201304099A publication Critical patent/TW201304099A/zh
Application granted granted Critical
Publication of TWI574363B publication Critical patent/TWI574363B/zh

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/043—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
    • H01L23/047—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body the other leads being parallel to the base
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • H05K1/0203—Cooling of mounted components
    • H05K1/0207—Cooling of mounted components using internal conductor planes parallel to the surface for thermal conduction, e.g. power planes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10106—Light emitting diode [LED]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10954—Other details of electrical connections
    • H05K2201/10977—Encapsulated connections

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Description

晶片封裝體
本發明涉及一種晶片封裝體。
一般地，晶片封裝體包括晶片、電路板及其它電子元件。將晶片與電路板或其它元件達成電連接的方法包括打線接合(wire bonding)。在這方法中，金線或鋁線等材質的金屬線會被作為導線使用。這些金屬線的等效電路為電感。電感效應(特別係當操作在高頻時電感效應會特別顯著)會影響電路特性，使電路阻抗難以匹配，並增加訊號損耗。
有鑒於此，有必要提供一種可降低電感效應的晶片封裝體，以使電路阻抗容易匹配，並減少訊號損耗。
一種晶片封裝體，其包括電路板、晶片及導線。該電路板包括金屬底層，形成在該金屬底層的中間層及形成在該中間層的導電線路層，該金屬底層用於連接地端，該晶片封裝體開設貫穿該導電線路層及該中間層的通孔以暴露該金屬底層，該晶片置於該通孔內且位於該金屬底層上，該導線連接該晶片及該導電線路層。
本發明提供的晶片封裝體，將晶片置於該通孔內且位於該金屬底層上，使晶片相對於導電線路層的高度降低，進而使得連接晶片與導電線路層的導線變短，因此可降低導線的等效電感值而降低 導線的電感效應而使得電路阻抗容易匹配並減少訊號損耗，同時也可以減少導線的使用，節約成本。
100，200‧‧‧晶片封裝體
10‧‧‧電路板
20，220‧‧‧晶片
30‧‧‧導線
40，80‧‧‧保護層
50‧‧‧封裝玻璃
101‧‧‧基層
102‧‧‧金屬底層
103‧‧‧中間層
104‧‧‧導電線路層
114‧‧‧連接墊
60，120‧‧‧通孔
201‧‧‧第一頂面
202‧‧‧晶片電極墊
203‧‧‧暴露區域
124‧‧‧第二頂面
圖1為本發明第一實施方式提供的一種具有封裝玻璃的晶片封裝體的截面示意圖。
圖2為圖1的晶片封裝體未安裝該封裝玻璃時的俯視圖。
圖3為本發明第二實施方式提供的一種晶片封裝體的截面示意圖。
下面將結合圖式對本發明作進一步詳細說明。
請參閱圖1至圖2，本發明第一實施方式提供的一種晶片封裝體100包括電路板10、晶片20、導線30、保護層40及封裝玻璃50。
該電路板10包括基層101、金屬底層102、中間層103及導電線路層104。該金屬底層102形成在該基層101上，該中間層103形成在該金屬底層102上，該導電線路層104形成在該中間層103上。該中間層103可為一層絕緣層或可為包含如金屬層與絕緣層交替堆疊的多層結構。
本實施方式中，該基層101的材料為陶瓷。金屬底層102用於連接地端。本實施方式中，請參圖2，(圖2為去掉封裝玻璃50及保護層40的晶片封裝體100的俯視圖)該導電線路層104包括4個連接墊114。
該晶片封裝體100開設貫穿該導電線路層104及該中間層103的通孔60以暴露該金屬底層102。該晶片20置於該通孔60內且位於該 金屬底層102上。金屬底層102有利於晶片20的散熱從而提升晶片封裝體100的散熱性能，而接地端的金屬底層102可以濾除掉來自晶片20附近電路產生的電磁波干擾及濾除掉晶片20在工作時產生的電磁波干擾，避免了晶片20與該附近電路的互相干擾。該附近電路可包括該晶片封裝體100包含的其它電路及/或該晶片封裝體100應用至其它電子裝置時，該電子裝置包含的電路。晶片20的背面可通過絕緣黏膠黏著在金屬底層102上而使得該晶片20與該金屬底層102相互絕緣。
該導線30連接該晶片20及該導電線路層104。具體地，該晶片20包括第一頂面201及位於該第一頂面201上的4個晶片電極墊202，該導電線路層104包括第二頂面124，該第一頂面201與該第二頂面124處於同一水平面。導線30包括4個導線，導線30連接晶片電極墊202及該連接墊114。導線30可通過如打線接合(wire bonding)的方法而連接該晶片電極墊202及該連接墊114。導線30可為金線，鋁線或銅線等金屬線。
保護層40的材料為熱固化樹脂，如聚醯亞胺樹脂(polyimide resin)、環氧樹脂(epoxy resin)、有機矽樹脂(silicone resin)及類似物。當然，保護層40的材料也不限於上述所列舉，凡發明所屬技術領域內的保護層材料也可用於本發明。本實施方式中，該保護層40覆蓋該導線30、該導線30與該晶片電極墊202的連接處及該導線30與該連接墊114的連接處及填充通孔60。保護層40可加強導線30分別與導電線路層104及晶片20的連接強度同時還可增加導線30、晶片電極墊202及連接墊114的抗氧化性以延長晶片封裝體100的使用壽命。本實施方式中，晶片20的第一 頂面201包括未被保護層40覆蓋的暴露區域203。當晶片20為發光晶片或感光晶片時，這種結構有利於提升晶片20的出光效率或收光效率。該暴露區域203對應為發光部分或感光部分。
封裝玻璃50黏合於保護層40上，以將晶片20封裝在晶片封裝體100中以保護晶片20免受水汽及灰塵的侵蝕及密封該暴露區域203。
上術晶片封裝體100，將晶片20置於該通孔60內且位於該金屬底層102上，使晶片20相對於導電線路層104的高度降低，進而使得連接晶片20與導電線路層104的導線30變短，因此可降低導線30的等效電感值而降低導線30的電感效應，同時也可以減少導線30的使用，節約成本。可以理解，晶片20的類型也不限於上述所列的類型，也可為本領域內的包括高頻晶片的其他類型晶片。
請參閱圖3，本發明第二實施方式提供的一種晶片封裝體200。該晶片封裝體200與第一實施方式的晶片封裝體100不同之處在於：保護層80填充通孔120並覆蓋晶片220，而省略了封裝玻璃。
綜上所述，本發明確已符合發明專利之要件，遂依法提出專利申請。惟，以上所述者僅為本發明之較佳實施方式，自不能以此限制本案之申請專利範圍。舉凡熟悉本案技藝之人士爰依本發明之精神所作之等效修飾或變化，如在其他實施方式中，晶片20可部分地位於通孔60內而使得晶片20的第一頂面201比第二頂面124高，使得相較於沒開設通孔60的晶片封裝體，導線30也能縮短；或在其他實施方式中，晶片20的第一頂面201比第二頂面124低，使得相較於沒開設通孔60的晶片封裝體時，導線30也能縮短等，皆應涵蓋於以下申請專利範圍內。
100‧‧‧晶片封裝體
10‧‧‧電路板
20‧‧‧晶片
30‧‧‧導線
40‧‧‧保護層
50‧‧‧封裝玻璃
101‧‧‧基層
102‧‧‧金屬底層
103‧‧‧中間層
104‧‧‧導電線路層
60‧‧‧通孔
201‧‧‧第一頂面
202‧‧‧晶片電極墊
203‧‧‧暴露區域
124‧‧‧第二頂面

Claims (10)

  1. 一種晶片封裝體，其包括電路板、晶片及導線，該電路板包括金屬底層，形成在該金屬底層的中間層及形成在該中間層的導電線路層，該金屬底層用於連接地端，該晶片封裝體開設貫穿該導電線路層及該中間層的通孔以暴露該金屬底層，該晶片置於該通孔內且通過絕緣黏膠黏著在該金屬底層上，該導線連接該晶片及該導電線路層。
  2. 如申請專利範圍第1項所述的晶片封裝體，其中，該晶片包括晶片電極墊，該導電線路層包括連接墊，該導線連接該晶片電極墊及該連接墊。
  3. 如申請專利範圍第1項所述的晶片封裝體，其中，該晶片包括第一頂面，該導電線路層包括第二頂面，該第一頂面與該第二頂面處於同一水平面。
  4. 如申請專利範圍第2項所述的晶片封裝體，其中，該晶片封裝體還包括保護層，該保護層覆蓋該導線、該導線與該晶片電極墊的連接處及該導線與該連接墊的連接處。
  5. 如申請專利範圍第4項所述的晶片封裝體，其中，該保護層的材料為熱固化樹脂。
  6. 如申請專利範圍第4項所述的晶片封裝體，其中，該晶片封裝體包括黏合於該保護層的封裝玻璃，該晶片包括第一頂面，該第一頂面包括未被保護層覆蓋的暴露區域，該封裝玻璃與該保護層密封該暴露區域。
  7. 如申請專利範圍第4項所述的晶片封裝體，其中，該保護層填充該通孔並覆蓋該晶片。
  8. 如申請專利範圍第1項所述的晶片封裝體，其中，該晶片與該金屬底層相互絕緣。
  9. 如申請專利範圍第1項所述的晶片封裝體，其中，該晶片包括第一頂面，該導電線路層包括第二頂面，該第一頂面比該第二頂面高。
  10. 如申請專利範圍第1項所述的晶片封裝體，其中，該晶片包括第一頂面，該導電線路層包括第二頂面，該第一頂面比該第二頂面低。
TW100123745A 2011-07-05 2011-07-05 晶片封裝體 TWI574363B (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW100123745A TWI574363B (zh) 2011-07-05 2011-07-05 晶片封裝體
US13/220,715 US20130010444A1 (en) 2011-07-05 2011-08-30 Chip package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW100123745A TWI574363B (zh) 2011-07-05 2011-07-05 晶片封裝體

Publications (2)

Publication Number Publication Date
TW201304099A TW201304099A (zh) 2013-01-16
TWI574363B true TWI574363B (zh) 2017-03-11

Family

ID=47438558

Family Applications (1)

Application Number Title Priority Date Filing Date
TW100123745A TWI574363B (zh) 2011-07-05 2011-07-05 晶片封裝體

Country Status (2)

Country Link
US (1) US20130010444A1 (zh)
TW (1) TWI574363B (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102012213916A1 (de) * 2011-11-08 2013-05-08 Robert Bosch Gmbh Elektronikmodul für ein Steuergerät
TW201442290A (zh) * 2013-04-24 2014-11-01 Hon Hai Prec Ind Co Ltd 發光二極體模組

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6301122B1 (en) * 1996-06-13 2001-10-09 Matsushita Electric Industrial Co., Ltd. Radio frequency module with thermally and electrically coupled metal film on insulating substrate
US20040067603A1 (en) * 2002-10-02 2004-04-08 Robert-Christian Hagen Method for producing channels and cavities in semiconductor housings, and an electronic component having such channels and cavities

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60208886A (ja) * 1984-03-31 1985-10-21 株式会社東芝 電子部品の製造方法
US6545227B2 (en) * 2001-07-11 2003-04-08 Mce/Kdi Corporation Pocket mounted chip having microstrip line
US7102240B2 (en) * 2004-06-11 2006-09-05 Samsung Electro-Mechanics Co., Ltd. Embedded integrated circuit packaging structure
KR100907508B1 (ko) * 2007-07-31 2009-07-14 (주)웨이브닉스이에스피 패키지 기판 및 그 제조방법

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6301122B1 (en) * 1996-06-13 2001-10-09 Matsushita Electric Industrial Co., Ltd. Radio frequency module with thermally and electrically coupled metal film on insulating substrate
US20040067603A1 (en) * 2002-10-02 2004-04-08 Robert-Christian Hagen Method for producing channels and cavities in semiconductor housings, and an electronic component having such channels and cavities

Also Published As

Publication number Publication date
US20130010444A1 (en) 2013-01-10
TW201304099A (zh) 2013-01-16

Similar Documents

Publication Publication Date Title
US10204848B2 (en) Semiconductor chip package having heat dissipating structure
TWI529878B (zh) 集成電路封裝件及其裝配方法
TWI484603B (zh) 具有散熱結構及電磁干擾屏蔽之半導體封裝件及其製造方法
TWI523157B (zh) 具有嵌入式基板及引線框之模組封裝
US9484282B2 (en) Resin-sealed semiconductor device
KR20140057979A (ko) 반도체 패키지 및 반도체 패키지의 제조 방법
JP2009105297A5 (zh)
TWI569404B (zh) 晶片封裝體
US20190333850A1 (en) Wiring board having bridging element straddling over interfaces
JP2013236039A (ja) 半導体装置
KR101391089B1 (ko) 반도체 패키지 및 그 제조방법
TWI574363B (zh) 晶片封裝體
TWI468088B (zh) 半導體封裝件及其製法
TW200824067A (en) Stacked chip package structure and fabricating method thereof
TWI613771B (zh) 半導體封裝
TWI388041B (zh) 具散熱結構之半導體封裝件
TWI567883B (zh) 具有複合基材的電子系統
TWI553841B (zh) 晶片封裝及其製造方法
JP4813786B2 (ja) 集積回路および集積回路アセンブリ
KR20120126365A (ko) 유닛 패키지 및 이를 갖는 스택 패키지
TWI472007B (zh) 內埋式電子元件之封裝結構
TWI423405B (zh) 具載板之封裝結構
TWI425886B (zh) 嵌埋有電子元件之封裝結構及其製法
KR20040037561A (ko) 반도체패키지
TWI613729B (zh) 基板結構及其製法

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees