TWI570838B - 碳化矽基板上的溝槽結構以及其製作方法 - Google Patents

碳化矽基板上的溝槽結構以及其製作方法 Download PDF

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TWI570838B
TWI570838B TW104137373A TW104137373A TWI570838B TW I570838 B TWI570838 B TW I570838B TW 104137373 A TW104137373 A TW 104137373A TW 104137373 A TW104137373 A TW 104137373A TW I570838 B TWI570838 B TW I570838B
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carbide substrate
trench structure
tantalum carbide
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朱冠維
蔡銘進
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財團法人工業技術研究院
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Description

碳化矽基板上的溝槽結構以及其製作方法
本發明是有關於一種碳化矽基板上的溝槽結構及其 製作方法,且特別是有關於一種碳化矽基板上具有圓弧狀溝槽底部的溝槽結構及其製作方法。
碳化矽材料具備寬帶隙、高導熱度、低熱膨脹率等 特徵,做為具有補充矽所不足之物性的半導體材料,應用於高頻率.高電力裝置、功率裝置等。
在半導體裝置中高密度集成化更為發展的現代,要 求更為密緻之精細圖型加工,因此一般碳化矽材料的溝槽製程採用乾式蝕刻進行加工,乾式蝕刻雖易於獲得高深寬比的溝槽結構,卻無法產生圓弧狀的溝槽底部,因此通常會在蝕刻完成後,利用鈍氣環境進行回火,使其產生圓弧狀的溝槽底部,但碳化矽材料的表面同樣會因高溫回火製程而粗糙化,進而影響蝕刻結構的精度。
本發明係有關於一種碳化矽基板上的溝槽結構以及 其製作方法,藉由在回火製程中以保護層覆蓋基板表面,進而改善基板表面因回火製程而粗糙化的問題。
根據本發明,提出一種溝槽結構的製作方法,一種溝槽結構的製作方法,包含提供一碳化矽基板;形成一保護層於該碳化矽基板上;形成一阻擋層於該保護層上;圖案化該阻擋層與該保護層,以形成一開口;以圖案化的該阻擋層為硬式罩幕,透過該開口圖案化該碳化矽基板,以形成一溝槽;移除該阻擋層;進行一回火製程,以形成一圓弧狀的溝槽底部;以及移除該保護層。
根據本發明,提出一種碳化矽基板上的溝槽結構,該溝槽結構包含:一溝槽側壁,垂直於該碳化矽基板表面;以及一溝槽底部,連接至該溝槽側壁,該溝槽底部具有圓弧狀的表面。
為了對本發明之上述及其他方面有更佳的瞭解,下文特舉實施例,並配合所附圖式,作詳細說明如下:
10‧‧‧碳化矽基板
11‧‧‧表面
20‧‧‧保護層
30‧‧‧阻擋層
40‧‧‧開口
50‧‧‧溝槽
50a‧‧‧溝槽側壁
50b‧‧‧溝槽底部
第1圖繪示依本發明之溝槽結構製作方法的結構剖面示意圖。
第2圖繪示依本發明之溝槽結構製作方法的結構剖面示意圖。
第3圖繪示依本發明之溝槽結構製作方法的結構剖面示意圖。
第4圖繪示依本發明之溝槽結構製作方法的結構剖面示意圖。
第5圖繪示依本發明之溝槽結構製作方法的結構剖面示意圖。
以下係參照所附圖式詳細敘述本發明之實施例。圖式中相同 的標號係用以標示相同或類似之部分。需注意的是,圖式係已簡化以利清楚說明實施例之內容,圖式上的尺寸比例並非按照實際產品等比例繪製,因此並非作為限縮本發明保護範圍之用。
第1~5圖繪示依本發明之溝槽結構製作方法的結構剖 面示意圖。以下段落針對本發明之第一實施例的一種溝槽結構的製作流程進行說明。請先參照第1圖,提供碳化矽基板10,提供之碳化矽基板10可為已完成活性化處理製程或未完成活性化處理製程的碳化矽基板。 在本實施例中,提供之碳化矽基板10已完成活性化處理製程。活性化處理製程例如在1600℃以上的溫度環境中,通入包含鈍氣的氣體進行高溫回火,但本發明不以此為限。
接著依序在碳化矽基板10上形成保護層20與阻擋層30。 保護層20的材料例如為石墨(graphite)或氮化鋁(AlN)。形成保護層20的方法例如為沉積,當保護層20的材料為石墨時,還可使用如光阻燒結的高溫碳化方式形成。阻擋層30的材料例如為二氧化矽(SiO2)、氮化矽(SiNx)、或金屬,形成阻擋層30的方法例如為沉積。
接著,如圖2所示,圖案化保護層20與阻擋層30,以形 成開口40。圖案化保護層20與阻擋層30的方法例如以光阻為罩幕,對保護層20與阻擋層30進行蝕刻,在蝕刻完成後再行移除光阻或硬式遮罩;或是直接採用雷射直寫的方式對對保護層20與阻擋層30圖案化。
如圖3所示,以圖案化的阻擋層30為硬式罩幕(hard mask),圖案化碳化矽基板10以形成溝槽結構50,溝槽結構50包含與碳化矽基板10的表面11垂直的溝槽側壁50a。圖案化碳化矽基板10的方法為乾式蝕刻,例如以電漿蝕刻方式,通入氣體包含組合如六氟化硫(SF6)和氧氣(O2)、氬氣(Ar)、或三氟化氮(NF3)和溴化氫(HBr)和氧氣(O2)對碳化矽基板10進行蝕刻。
如圖4所示,移除圖案化的阻擋層30,此時的碳化矽基板 10除了溝槽結構50外均被保護層20覆蓋,接著對碳化矽基板10進行回火製程,以在溝槽結構50中形成圓弧狀的溝槽底部50b。在本實施例中,回火製程例如在1450℃到1850℃的溫度環境中,通入包含氫氣、氮氣、或鈍氣等氣體。
如圖5所示,在完成回火製程後,移除保護層20, 以完成包含溝槽側壁50a與溝槽底部50b的溝槽結構50,其中溝槽側壁50a與碳化矽基板10的表面11形成直角,溝槽底部50b具有圓弧狀結構。 由於在回火製程中,碳化矽基板10除溝槽結構50外的表面11均被保護層20所覆蓋,因此可在回火製程中,保護碳化矽基板10的表面11不受高溫影響產生粗糙化,避免溝槽側壁50a與碳化矽基板10的表面11的接觸部位產生圓弧化,進而確保在同時製作多個溝槽結構50時其間的線距。
同樣的,請參照第1~5圖,以下段落針對本發明之第二實 施例的一種溝槽結構的製作流程進行說明。本發明之第二實施例的製作流程與第一實施例大致相同,以下僅針對不同處進行說明,相同之處則不加以贅述。在本發明的第二實施例中,如第1圖所示,提供碳化矽基板10,提供之碳化矽基板10為未完成活性化處理製程的碳化矽基板。且如圖4所示,對碳化矽基板10進行回火製程,以形成圓弧狀的溝槽底部50b。 在本發明之第二實施例中,高溫回火製程例如在1600℃到1850℃的溫度環境中進行,通入包含氮氣或鈍氣等氣體。
值得注意的是,在本發明之第二實施例中,回火製程 加溫至1600℃的高溫,由於碳化矽基板10除了溝槽結構50外均被保護層20所覆蓋,因此可避免碳化矽基板10的表面11因本實施例的高溫回火製程而受損,並在高溫回火製程中同時形成圓弧狀的溝槽底部50b與完成碳化矽基板10的活性化處理製程。
綜上所述,雖然本發明已以實施例揭露如上,然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作各種之更動與潤飾。因此,本發明之保護範圍當視後附之申請專利範圍所界定者為準。
10‧‧‧碳化矽基板
50‧‧‧溝槽
50a‧‧‧溝槽側壁
50b‧‧‧溝槽底面

Claims (8)

  1. 一種溝槽結構的製作方法,包含:提供一碳化矽基板;形成一保護層於該碳化矽基板上;形成一阻擋層於該保護層上;圖案化該阻擋層與該保護層,以形成一開口;以圖案化的該阻擋層為硬式罩幕,透過該開口圖案化該碳化矽基板,以形成一溝槽;移除圖案化的該阻擋層;進行一回火製程,以形成一圓弧狀的溝槽底部;以及移除該保護層。
  2. 如申請專利範圍第1項所述之溝槽結構的製作方法,其中該回火製程溫度介於1450℃到1850℃之間。
  3. 如申請專利範圍第1項所述之溝槽結構的製作方法,其中該回火製程溫度介於1600℃到1850℃之間,該碳化矽基板於該回火製程階段同時完成一活性化處理製程。
  4. 如申請專利範圍第1項所述之溝槽結構的製作方法,其中該保護層的材料為石墨(graphite)或氮化鋁(AlN)。
  5. 如申請專利範圍第1項所述之溝槽結構的製作方法,其中該阻擋層的材料為二氧化矽(SiO2)、氮化矽(SiNx)、或金屬。
  6. 如申請專利範圍第2項所述之溝槽結構的製作方法,其中該回火製程採用氫氣、氮氣、或鈍氣環境。
  7. 如申請專利範圍第3項所述之溝槽結構的製作方法,其中該回火製程採用氮氣或鈍氣環境。
  8. 一種碳化矽基板上的溝槽結構,該溝槽結構包含:一溝槽側壁,垂直於該碳化矽基板表面;以及一溝槽底部,連接至該溝槽側壁,該溝槽底部具有圓弧狀的表面。
TW104137373A 2015-11-12 2015-11-12 碳化矽基板上的溝槽結構以及其製作方法 TWI570838B (zh)

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TW104137373A TWI570838B (zh) 2015-11-12 2015-11-12 碳化矽基板上的溝槽結構以及其製作方法
CN201510888732.3A CN106711035B (zh) 2015-11-12 2015-12-07 碳化硅基板上的沟槽结构以及其制作方法
US14/975,995 US9899222B2 (en) 2015-11-12 2015-12-21 Trench structure on SiC substrate and method for fabricating thereof

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US10343900B2 (en) * 2016-09-07 2019-07-09 The Government Of The United States Of America, As Represented By The Secretary Of The Navy Material structure and method for deep silicon carbide etching
CN111128717B (zh) * 2018-10-30 2022-10-04 株洲中车时代半导体有限公司 一种碳化硅沟槽结构的制造方法
WO2020102990A1 (zh) * 2018-11-20 2020-05-28 长江存储科技有限责任公司 外延层和3d nand存储器的形成方法、退火设备
CN111348821A (zh) * 2018-12-21 2020-06-30 财团法人工业技术研究院 用于玻璃塑形的石墨模具及其制造方法
GB201917734D0 (en) * 2019-12-04 2020-01-15 Spts Technologies Ltd Method, substrate and apparatus
GB202014733D0 (en) * 2020-09-18 2020-11-04 Oxford Instruments Nanotechnology Tools Ltd Method of preparing a silicon carbide wafer

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050009255A1 (en) * 2003-07-10 2005-01-13 International Rectifier Corp. Process for forming thick oxides on Si or SiC for semiconductor devices
US20050042871A1 (en) * 2003-08-19 2005-02-24 Kaan-Lu Tzou Multi-layer hard mask structure for etching deep trench in substrate

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5258332A (en) 1987-08-28 1993-11-02 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor devices including rounding of corner portions by etching
US5571374A (en) * 1995-10-02 1996-11-05 Motorola Method of etching silicon carbide
US6180466B1 (en) 1997-12-18 2001-01-30 Advanced Micro Devices, Inc. Isotropic assisted dual trench etch
US6235643B1 (en) 1999-08-10 2001-05-22 Applied Materials, Inc. Method for etching a trench having rounded top and bottom corners in a silicon substrate
US6825087B1 (en) 1999-11-24 2004-11-30 Fairchild Semiconductor Corporation Hydrogen anneal for creating an enhanced trench for trench MOSFETS
US6406982B2 (en) 2000-06-05 2002-06-18 Denso Corporation Method of improving epitaxially-filled trench by smoothing trench prior to filling
JP3702162B2 (ja) 2000-09-25 2005-10-05 三洋電機株式会社 半導体装置の製造方法
US7439141B2 (en) 2001-12-27 2008-10-21 Spansion, Llc Shallow trench isolation approach for improved STI corner rounding
JP4123961B2 (ja) 2002-03-26 2008-07-23 富士電機デバイステクノロジー株式会社 半導体装置の製造方法
US6670275B2 (en) 2002-05-29 2003-12-30 Macronix International Co., Ltd Method of rounding a topcorner of trench
US7309641B2 (en) 2004-11-24 2007-12-18 United Microelectronics Corp. Method for rounding bottom corners of trench and shallow trench isolation process
US20080085606A1 (en) * 2006-10-06 2008-04-10 Dominik Fischer Method for Fabricating a Structure for a Semiconductor Component, and Semiconductor Component
JP5509520B2 (ja) * 2006-12-21 2014-06-04 富士電機株式会社 炭化珪素半導体装置の製造方法
CN101652835B (zh) * 2007-04-20 2012-03-21 佳能安内华股份有限公司 具有碳化硅基板的半导体器件的退火方法和半导体器件
US7892929B2 (en) 2008-07-15 2011-02-22 Taiwan Semiconductor Manufacturing Company, Ltd. Shallow trench isolation corner rounding
TW201123358A (en) 2009-12-29 2011-07-01 Taiwan Memory Corp Methods for fabricating electronic device
JP5500002B2 (ja) 2010-08-31 2014-05-21 株式会社デンソー 炭化珪素半導体装置の製造方法
CN104241190A (zh) 2014-07-31 2014-12-24 上海华力微电子有限公司 浅沟槽制备方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050009255A1 (en) * 2003-07-10 2005-01-13 International Rectifier Corp. Process for forming thick oxides on Si or SiC for semiconductor devices
US20050042871A1 (en) * 2003-08-19 2005-02-24 Kaan-Lu Tzou Multi-layer hard mask structure for etching deep trench in substrate

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