WO2020102990A1 - 外延层和3d nand存储器的形成方法、退火设备 - Google Patents

外延层和3d nand存储器的形成方法、退火设备

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Publication number
WO2020102990A1
WO2020102990A1 PCT/CN2018/116491 CN2018116491W WO2020102990A1 WO 2020102990 A1 WO2020102990 A1 WO 2020102990A1 CN 2018116491 W CN2018116491 W CN 2018116491W WO 2020102990 A1 WO2020102990 A1 WO 2020102990A1
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Prior art keywords
annealing
silicon
insulating layer
forming
groove
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PCT/CN2018/116491
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English (en)
French (fr)
Inventor
郭海峰
王孝进
朱宏斌
赖琳
程腾
肖莉红
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长江存储科技有限责任公司
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Application filed by 长江存储科技有限责任公司 filed Critical 长江存储科技有限责任公司
Priority to CN201880096615.5A priority Critical patent/CN112997272B/zh
Priority to PCT/CN2018/116491 priority patent/WO2020102990A1/zh
Priority to TW108103911A priority patent/TWI676273B/zh
Priority to TW108128012A priority patent/TWI693628B/zh
Priority to US16/351,532 priority patent/US10741390B2/en
Publication of WO2020102990A1 publication Critical patent/WO2020102990A1/zh

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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
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    • H01L21/02694—Controlling the interface between substrate and epitaxial layer, e.g. by ion implantation followed by annealing
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
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    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
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    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

Definitions

  • the invention relates to the field of semiconductor manufacturing, in particular to an epitaxial layer and 3D NAND memory forming method and annealing equipment.
  • NAND flash memory is a better storage device than hard drives. As people pursue non-volatile storage products with low power consumption, light weight and good performance, they have been widely used in electronic products. At present, the planar structure of 3D NAND flash memory is near the limit of actual expansion. In order to further increase the storage capacity and reduce the storage cost per bit, a 3D structure of 3D NAND memory is proposed.
  • a vertically stacked multi-layer data storage unit is adopted to realize a stacked 3D NAND memory structure.
  • the formation process of the existing 3D NAND memory generally includes: forming a stacked layer of a silicon nitride layer and a silicon oxide layer alternately stacked on a substrate; etching the stacked layer, forming a channel hole in the stacked layer, and forming a channel After the hole, the substrate at the bottom of the channel hole is etched to form a groove in the substrate; in the groove at the bottom of the channel hole, an epitaxial silicon structure is formed by selective epitaxial growth (Selective Epitaxial Growth), usually the epitaxial silicon The structure is also called SEG; a storage region is formed in the channel hole; a silicon nitride layer is removed, and a gate metal is formed where the silicon nitride layer is removed.
  • the technical problem to be solved by the present invention is how to prevent the formation of hole defects in the formed epitaxial layer (SEG) and improve the electrical contact performance between the epitaxial silicon structure (SEG) and the substrate.
  • the present invention provides a method for forming an epitaxial layer, including:
  • a substrate on which a stacked structure in which a first insulating layer and a second insulating layer are alternately stacked is formed; etching the stacked structure to form a plurality of channel holes penetrating the stacked structure; and etching trenches along the channel holes
  • a groove is formed in the substrate; after the groove is formed, a first annealing is performed.
  • a silicon-containing mixture is formed on the sidewall and bottom surface of the groove; After the first annealing, a second annealing is performed to remove the silicon-containing mixture; after the second annealing, a selective epitaxial process is used to form an epitaxial layer in the groove, and the epitaxial layer is filled Scription groove.
  • the silicon-containing mixture contains, in addition to silicon elements, elements contained in the gas used in the first annealing, elements contained in the source gas and / or by-products forming the first insulating layer, and forming One or more of the elements contained in the source gas and / or by-products of the second insulating layer.
  • the gas atmosphere of the first annealing is N 2
  • the gas atmosphere of the second annealing is H 2 .
  • the material of the first insulating layer and the material of the second insulating layer are one of silicon oxide, silicon nitride, silicon oxynitride, and silicon nitride carbide, and the material of the first insulating layer and the first The materials of the two insulating layers are different.
  • the silicon-containing mixture also includes one or more of N element, C element, H element, and O element.
  • the temperature during the second annealing is 800 to 1200 degrees Celsius, the time is 1 to 10 hours, and the pressure of the chamber is less than 100 Torr.
  • the gas used in the second annealing reacts with the silicon-containing mixture to form a gaseous reactant.
  • the crystal plane index of the sidewall of the groove is (111).
  • the invention also provides a method for forming a 3D NAND memory, including:
  • a substrate on which a stacked structure in which a first insulating layer and a second insulating layer are alternately stacked is formed; etching the stacked structure to form a plurality of channel holes penetrating the stacked structure; and etching trenches along the channel holes
  • a groove is formed in the substrate; after the groove is formed, a first annealing is performed.
  • a silicon-containing mixture is formed on the sidewall and bottom surface of the groove;
  • a second annealing is performed to remove the silicon-containing mixture;
  • a selective epitaxial process is used to form an epitaxial layer in the groove, and the epitaxial layer is filled The groove; forming a memory structure in a channel hole on the epitaxial layer; removing the first insulating layer, and forming a metal gate at a corresponding position after the first insulating layer is removed.
  • the silicon-containing mixture contains, in addition to silicon elements, elements contained in the gas used in the first annealing, elements contained in the source gas and / or by-products forming the first insulating layer, and forming One or more of the elements contained in the source gas and / or by-products of the second insulating layer.
  • the gas atmosphere of the first annealing is N 2
  • the gas atmosphere of the second annealing is H 2 .
  • the material of the first insulating layer and the material of the second insulating layer are one of silicon oxide, silicon nitride, silicon oxynitride, and silicon nitride carbide, and the material of the first insulating layer and the first The materials of the two insulating layers are different.
  • the silicon-containing mixture also includes one or more of N element, C element and H element.
  • the temperature during the second annealing is 800 to 1200 degrees Celsius, the time is 1 to 10 hours, and the pressure of the chamber is less than 100 Torr.
  • the gas used in the second annealing reacts with the silicon-containing mixture to form a gaseous reactant.
  • the crystal plane index of the sidewall of the groove is (111).
  • the present invention also provides an annealing device for performing second annealing on the foregoing substrate, including:
  • the crystal boat has an inwardly recessed boat body, and the inner side wall of the boat body has a number of support structures on which wafers are placed, the corners of the boat body of the crystal boat and the support structure The thickness is greater than the thickness of other parts of the boat;
  • the gas supply end is used to supply process gas to the reaction chamber
  • the heater is used to heat the wafer on the wafer boat in the reaction chamber.
  • the thickness of the bend of the boat body and the support structure is 0.5 to 5 cm greater than the thickness of other parts of the boat body.
  • the thickness of the corner of the boat body and the support structure is 1.1-10 cm.
  • the temperature in the reaction chamber when the heater is heated is 800 to 1200 degrees Celsius, and the heating time is 1 to 10 hours.
  • the supplied process gas includes H 2 .
  • the annealing equipment may also be used to perform the first annealing.
  • the supplied process gas includes N 2 .
  • a first annealing is first performed to eliminate the stress generated in the stacked structure.
  • the side walls and bottom of the groove A silicon-containing mixture is formed on the surface, so after the first annealing, a second annealing is performed to remove the silicon-containing mixture from the sidewall and bottom surface of the groove, so that the subsequent growth interface when forming the epitaxial layer is a pure liner
  • the bottom material interface prevents hole defects in the epitaxial layer formed in the groove.
  • the material of the first insulation layer and the material of the second insulation layer are one of silicon oxide, silicon nitride, silicon oxynitride, and silicon nitride carbide.
  • the source gas (gas used in the chemical vapor deposition process) elements such as C, H, N, O
  • by-product elements such as C, H, N
  • the substrate material reacts to form a complex silicon-containing mixture. Therefore, in addition to silicon, the silicon-containing mixture also includes one or more of N, C, H, and O. By containing H 2 The second annealing can remove the silicon-containing mixture.
  • the temperature during the second annealing is 800 to 1200 degrees Celsius, the time is 1 to 10 hours, and the pressure of the chamber is less than 100 Torr.
  • high temperature and long time annealing are used , So that the silicon-containing mixture can be cleaned and removed more efficiently.
  • a second annealing is performed to remove the silicon-containing mixture from the sidewall and bottom surface of the groove, so that the growth interface when forming the epitaxial layer is a pure substrate material interface, preventing concave A hole defect occurs in the epitaxial layer formed in the groove, so the conductivity between the epitaxial layer and the substrate will not be affected, and the performance of the 3D NAND memory is improved.
  • the thickness of the bend and support structure of the boat body of the crystal boat is greater than the thickness of other parts of the boat body, so that the crystal boat can withstand high temperature (greater than 800 degrees Celsius) and long time (greater than 1 hour) Annealing to prevent the boat boat body from generating cracks or cracks at fragile corners (such as the junction of the side wall and bottom of the boat boat) and the support structure, that is, the annealing equipment of this application can achieve high temperature and long time Annealing, and can realize the annealing treatment of batch wafers.
  • the annealing device of the present invention can be used for the second annealing of the wafer (substrate) in the foregoing solution, while improving efficiency, the effect of removing the silicon-containing mixture on the sidewall and bottom surface of the groove is also better.
  • FIG. 1 to 4 are schematic structural diagrams of an exception layer formation process according to an embodiment of the present invention.
  • 5-9 are schematic structural diagrams of another embodiment of the present invention forming an epitaxial layer
  • 10-11 are schematic structural views of a 3D NAND memory according to another embodiment of the invention.
  • FIG. 12 is a schematic structural diagram of an annealing apparatus according to another embodiment of the present invention.
  • the bottom area of the epitaxial silicon structure (SEG) formed by the existing process is prone to hole defects, which makes the electrical contact performance of the epitaxial silicon structure (SEG) and the substrate poor, which affects the 3D NAND memory performance.
  • a stacked layer 104 in which a silicon nitride layer 102 and a silicon oxide layer 103 are alternately stacked is formed on a substrate 100, and an isolation layer 101 may also be formed between the stacked structure 104 and the substrate 100.
  • the stack layer 104 is etched to form a channel hole 105 in the stack layer 104.
  • the substrate 100 at the bottom of the channel hole 105 is etched to form a recess in the substrate 100 ⁇ 106.
  • the stacked structure 104 is annealed in a nitrogen (N 2 ) atmosphere to relieve the stress existing in the stacked structure 104.
  • N 2 nitrogen
  • the silicon nitride layer 102 and the silicon oxide layer 103 are formed by a chemical vapor deposition process, when the silicon nitride layer 102 and the silicon oxide layer 103 are formed, especially the multi-layer stacked silicon nitride layer 102 and the oxide In the silicon layer 103, part of the source gas (gas used in the chemical vapor deposition process) elements (such as C, H, N, O) and by-product elements (such as C, H) will trap or remain in the formed nitrogen In the silicon oxide layer 102 and the silicon oxide layer 103 or the stacked structure 104, these elements will be released from the silicon nitride layer 102 and the silicon oxide layer 103 or the stacked structure 104 during annealing to diffuse to the bottom and side walls of the groove 106
  • the presence of the silicon-containing mixture 107 makes the interface for the subsequent formation of an epitaxial silicon structure by selective epitaxial growth not Pure single crystal silicon interface, so when selective epitaxial growth (Selective Epitaxial Growth) silicon, the growth rate of the surface of the complex silicon-containing mixture 107 and the surface of single crystal silicon are different, making the epitaxial silicon structure 109 ( 4) having a hole defect 108 (see FIG. 4), and the hole defect 108 mainly exists at the interface of the epitaxial silicon structure 109 in contact with the substrate 100 and the contact interface of the epitaxial silicon structure 109 and the silicon-containing mixture 107, or If the groove is deep, the hole defect 108 will still exist in the epitaxial silicon structure 109.
  • a cleaning process is performed before forming the epitaxial silicon structure 109 in the groove 106, neither wet cleaning nor dry cleaning can remove the silicon-containing mixture cleanly, and the wet cleaning and drying The method of cleaning will introduce new impurities, so that the interface used to form the epitaxial silicon structure 109 by selective epitaxial growth cannot be pure single crystal silicon, so the formed epitaxial silicon structure 109 may still have hole defects.
  • another embodiment of the present invention provides a method and an annealing device for forming an epitaxial layer and a 3D NAND memory, wherein the method for forming the epitaxial layer, after forming channel holes and grooves, firstly Annealing to eliminate the stress generated in the stacked structure.
  • the first annealing a silicon-containing mixture is formed on the sidewalls and bottom surface of the groove, so after the first annealing, a second annealing is performed to remove the The silicon-containing mixture on the sidewall and bottom surface of the groove makes the subsequent growth interface during the formation of the epitaxial layer a pure substrate material interface, preventing hole defects in the epitaxial layer formed in the groove.
  • 5-11 are schematic structural views of another embodiment of the process of forming an epitaxial layer.
  • a substrate 200 is provided on which a stacked structure 204 in which a first insulating layer 202 and a second insulating layer 203 are alternately stacked is formed.
  • the material of the substrate 200 may be single crystal silicon (Si), single crystal germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); it may also be silicon on insulator (SOI), germanium on insulator ( GOI); or other materials, such as gallium arsenide and other III-V group compounds.
  • the material of the substrate 200 is single crystal silicon (Si).
  • the first insulating layer 202 serves as a sacrificial layer, and then the first insulating layer 202 is removed to form a metal gate at the location of the first insulating layer 202.
  • the material of the first insulating layer 202 and the material of the second insulating layer 203 are different.
  • the material of the first insulating layer 202 and the material of the second insulating layer 203 are silicon oxide and silicon nitride , One of silicon oxynitride and silicon oxynitride.
  • the material of the first insulating layer 202 is silicon nitride
  • the material of the second insulating layer 203 is silicon oxide
  • the forming process of the first insulating layer 202 and the second insulating layer 203 is chemical vapor deposition Craftsmanship.
  • the process of forming a film layer using a chemical vapor deposition process generally includes: passing a source gas into the chamber, and the source gas reacts to form a film layer on the substrate.
  • the formation of the silicon oxide layer (second insulating layer 203) is specifically described.
  • the process of forming the silicon oxide layer (second insulating layer 203) using a chemical vapor deposition process includes: passing a source into the reaction chamber Gas, the source gas includes silicon source gas and oxygen source gas, the silicon source gas is silane or TEOS, the oxygen source gas is O 2 , CO or ON 2 , the flow rate of the silicon source gas and oxygen source gas It is: 100 standard ml / min ⁇ 8000 standard ml / min, the temperature is: 300 degrees Celsius ⁇ 800 degrees Celsius, the pressure is: 3 Torr ⁇ 200 Torr.
  • the first insulating layer 202 and the second insulating layer 203 are formed by the chemical vapor deposition process, especially when the multilayer stack structure 104 is formed, part of the source gas (gas used in the chemical vapor deposition process) elements (such as C, H, N , O) and by-product elements (such as C, H, N) may trap or remain in the formed first insulating layer 202 and second insulating layer 203.
  • the source gas gas used in the chemical vapor deposition process
  • by-product elements such as C, H, N
  • the first insulating layer 202 of silicon nitride material when the first insulating layer 202 of silicon nitride material is formed, one or several elements of C and H may trap or remain in the first insulating layer 202 to form an oxide
  • the second insulating layer 203 of silicon material when the second insulating layer 203 of silicon material is used, one or more of the elements C, H, N, and O may trap or remain in the second insulating layer 203.
  • the alternating stacking of the first insulating layer 202 and the second insulating layer 203 means that after forming a layer of the first insulating layer 202, a layer of the second insulating layer 203 is correspondingly formed on the surface of the first insulating layer 202.
  • the steps of forming the first insulating layer 202 and the second insulating layer 203 are sequentially performed.
  • the number of layers of the first insulating layer 202 and the second insulating layer 203 or the number of layers of the stacked structure 204 are determined according to the number of memory cells required to be formed in the vertical direction, and the first insulating layer 202 and the second insulating layer
  • the number of layers of the layer 203 or the number of layers of the stacked structure 204 may be 8 layers, 32 layers, 64 layers, etc. The more the number of stacked layers, the higher the degree of integration. In this embodiment, only the number of layers of the first insulating layer 202 and the second insulating layer 203 or the number of layers of the stacked structure 204 is 5 as an example for description.
  • a bottom insulating layer 201 may also be formed between the stacked structure 204 and the substrate 200, and the material of the bottom insulating layer 201 is silicon oxide, which is formed by a thermal oxidation process, and the bottom insulating layer 201 may The stress effect of the stacked structure 204 on the substrate 200 is reduced.
  • the stack structure 204 is etched to form several channel holes 205 penetrating the stack structure 204; the substrate 200 at the bottom of the channel hole 205 is etched along the channel hole 205, and a groove 206 is formed in the substrate 200 .
  • a memory structure is subsequently formed in the channel hole 205, and an epitaxial layer is subsequently formed in the groove 206.
  • a patterned mask layer is formed on the surface of the stacked structure, and when the stacked structure is etched, the patterned mask layer is used as the Mask.
  • an anisotropic dry etching process is used, for example, a plasma etching process or a reactive ion etching process.
  • the gas used for etching includes a gas containing carbon and fluorine elements.
  • the step of etching the substrate 200 to form the groove 206 may be formed by an over-etching process after the step of etching the stacked structure 204 to form the channel hole 205. In other embodiments, the step of etching the substrate 200 to form the groove 206 may also be formed by an additional etching process after the step of etching the stacked structure 204 to form the channel hole 205. The step of etching the stacked structure 204 to form the channel hole 205 and the step of etching the substrate 200 to form the groove 206 may be performed in the same etching chamber or in different etching chambers.
  • the sidewall of the groove 206 is formed in an arc shape, and the farther away from the surface of the substrate 200, the smaller the width of the groove 206. It should be noted that, in other embodiments, the sidewall of the groove 206 may have other shapes.
  • a first annealing 31 is performed. During the first annealing 31, a silicon-containing mixture 207 is formed on the sidewall and bottom surface of the groove 206.
  • the purpose of performing the first annealing 31 is to eliminate the stress in the stacked structure 204 and the stress between the stacked structure 204 and the substrate 200 to prevent the stacked structure from collapsing due to the stress.
  • the gas atmosphere in which the first annealing 31 is performed is an inert gas atmosphere to prevent oxidation of the substrate 200.
  • the gas atmosphere of the first annealing in this embodiment is N 2.
  • N 2 does not cause oxidation on the substrate, and the price is low.
  • a gas inert gas atmosphere such as Ar gas, may be used.
  • the silicon-containing mixture contains, in addition to silicon elements, elements contained in the source gas and / or byproducts forming the first insulating layer, and source gas and / or byproducts forming the second insulating layer One or more of the contained elements.
  • the silicon-containing mixture 207 also includes one or more of N element, C element, H element, and O element.
  • the presence of the silicon-containing mixture 207 makes the interface for the subsequent formation of the epitaxial layer (the sidewall and bottom surface of the groove 206) not a pure substrate material (such as single crystal silicon or single crystal germanium, etc.) interface, if directly in the groove 206
  • the epitaxial layer is formed in the middle, and hole defects are easily formed in the epitaxial layer.
  • a second annealing 32 is performed to remove the silicon-containing mixture 207 on the sidewall and bottom surface of the groove 206.
  • the second annealing 32 is performed in the annealing chamber of the annealing equipment. During the second annealing 32, the gas used in the second annealing 32 reacts with the silicon-containing mixture 207 to form a gaseous reactant, which is directly discharged from the annealing chamber Chamber, thereby removing the silicon-containing mixture 207 on the sidewall and bottom surface of the groove 206, so that the subsequent growth interface when forming the epitaxial layer is a pure substrate material interface.
  • the gas atmosphere of the second annealing is H 2.
  • H 2 can not only remove the silicon-containing mixture 207, but also not damage the substrate 200 exposed by the trench 206.
  • the principle of using H 2 to remove the silicon-containing mixture 207 is as follows:
  • H 2 reacts with Si in the silicon-containing mixture 207 to form Si-H bonds, and the Si-H bonds continue to react with the remaining mixture to form gaseous reactants.
  • the temperature during the second annealing is 800 to 1200 degrees Celsius
  • the time is 1 to 10 hours
  • the pressure in the chamber is less than 100 Torr.
  • high temperature and Long-term annealing allows the silicon-containing mixture 207 to be cleaned and removed more efficiently.
  • the crystal plane index of the sidewalls around the groove 206 is (111), and then a selective epitaxy process is used in the groove 206
  • the formed epitaxial layer and substrate 200 form an integrated structure, so that there is no contact interface between the two, and there is no hole defect in the epitaxial layer.
  • the crystal surface index indices of crystal
  • the crystal surface index is one of the constants of the crystal and is the reciprocal ratio of the intercept coefficient of the crystal plane on the three crystal axes. When converted to an integer ratio, the resulting three The integer is called the Miller index of the crystal plane.
  • the second annealing 32 is directly performed without additional dry cleaning and / or wet cleaning in the middle.
  • the first annealing 31 and the second annealing 32 may be performed in the same annealing equipment, or may be performed in different annealing equipment.
  • an epitaxial layer 210 is formed in the groove 206 using a selective epitaxial process, and the epitaxial layer 210 fills the groove 206.
  • the material of the formed epitaxial layer 210 is the same as the material of the substrate 200, the material of the epitaxial layer is silicon, and the surface of the epitaxial layer 210 is higher than the surface of the substrate 200.
  • the sidewall or bottom surface of the groove 206 is a pure single-crystal silicon interface, the growth rate of silicon on the interface or a distance of the interface is kept uniform or the difference is very small, thereby preventing the formation A hole defect is formed in the epitaxial layer 210 of.
  • the formation process of the epitaxial layer 210 of the silicon material is: the reaction gas includes silicon source gas, HCl and H 2 , wherein the silicon source gas is SiH 4 , SiH 2 Cl 2 , SiHCl 3 and SiH 3 One or more of Cl, the flow rate of silicon source gas is 10 sccm to 900 sccm, the flow rate of HCl is 8 sccm to 950 sccm, the flow rate of H 2 is 150 sccm to 5000 sccm, the temperature of the reaction chamber is 600 degrees to 850 degrees Celsius, and the pressure of the reaction chamber is 1 Torr to 100 Torr.
  • the silicon source gas is SiH 4 , SiH 2 Cl 2 , SiHCl 3 and SiH 3
  • the flow rate of silicon source gas is 10 sccm to 900 sccm
  • the flow rate of HCl is 8 sccm to 950 sccm
  • the flow rate of H 2 is 150 scc
  • the epitaxial layer 210 may use a semiconductor material different from the substrate material.
  • the epitaxial layer 210 material may be silicon or silicon germanium.
  • the height of the epitaxial layer can also be set according to actual needs.
  • FIGS. 10-11 Another embodiment of the present invention also provides a method for forming a 3D NAND memory.
  • FIGS. 10-11 It should be noted that the description or limitation of the same or similar structure in this embodiment as in the previous embodiment will not be repeated in this embodiment. For details, please refer to the description or limitation of the corresponding part in the foregoing embodiment.
  • FIG. 10 is performed on the basis of FIG. 9, that is, after the epitaxial layer 210 is formed in the manner of the foregoing embodiment; a memory structure is formed on the epitaxial layer 210.
  • the memory structure includes at least a charge trap layer and a channel layer.
  • the charge trap layer is an ONO layer, that is, a stack of silicon oxide-silicon nitride-silicon oxide
  • the channel layer is a polysilicon layer.
  • an ONO layer, a polysilicon layer, and a silicon oxide layer may be sequentially deposited in the channel hole 220 to form a memory structure.
  • the first insulating layer 202 is removed (refer to FIG. 10), and a metal gate 211 is formed at a corresponding position after the first insulating layer 202 is removed.
  • the first insulating layer 202 is removed by wet etching, and the etching rate of the solution used in the wet etching on the first insulating layer 202 is much greater than that on the second insulating layer 203 and the epitaxial layer 210.
  • the etching solution used in the wet etching is phosphoric acid.
  • the formed epitaxial layer 210 since the formed epitaxial layer 210 has no hole defects, the conductive performance between the epitaxial layer 210 and the substrate 200 will not be affected, and the performance of the 3D NAND memory is improved.
  • an annealing apparatus for performing second annealing on the foregoing substrate is also provided. Please refer to FIG. 12, including:
  • the boat 403 in the reaction chamber 401 has an inwardly recessed boat body, and the inner side wall of the boat body has a number of supporting structures 404 for placing wafers, and the boat boat 403 turns And the thickness of the support structure 404 is greater than the thickness of other parts of the boat;
  • the gas supply end is used to supply the reaction gas to the reaction chamber
  • the heater 402 is used to heat the wafer 200 on the wafer boat 403 in the reaction chamber 401.
  • the crystal boat 403 has a plurality of support structures 404, and the material of the support structure 404 is the same as the material of the crystal boat, all of which are quartz. Several support structures can simultaneously support several wafers for annealing.
  • the crystal boat may be a cube with an opening on one side, and a plurality of support structures 404 are provided on three sides of the cube or two opposite sides in contact with the opening.
  • the thickness of the corner of the boat body of the crystal boat 403 and the support structure 404 are greater than the thickness of other parts of the boat body, so that the crystal boat 403 can withstand high temperature (greater than 800 degrees Celsius) and long time (greater than 1 hour) ) Annealing to prevent the boat boat body from cracking or chipping at fragile corners (such as the junction between the side wall and bottom of the boat boat) and the support structure.
  • the thickness of the corner of the boat body and the support structure is 0.5 to 5 cm greater than the thickness of other parts of the boat body. In a specific embodiment, the corner of the boat body and the thickness of the support structure are 1.1-10 cm.
  • the temperature in the reaction chamber 401 may be 800 to 1200 degrees Celsius, and the heating time is 1 to 10 hours.
  • the annealing apparatus may further include an internal thermocouple 405 and an external thermocouple 406, the internal thermocouple 405 is used to measure the temperature of the reaction chamber 401, and the external thermocouple 406 is used to measure the temperature of the heater 402.
  • the annealing equipment in this embodiment can perform high-temperature (greater than 800 degrees Celsius) and long-term (greater than 1 hour) annealing. During the annealing, the wafer boat will not produce cracks or chipping, and it can achieve batch wafer annealing. Therefore, when the annealing equipment in this embodiment can be used for the second annealing of the wafer (substrate) in the previous embodiment, while improving efficiency, the effect of removing the silicon-containing mixture on the sidewalls and bottom surface of the groove is also more effective it is good.
  • the supplied process gas includes H 2 .
  • the wafer (substrate) 200 to be annealed is first placed on the support structure 404 on the wafer boat 403; then the wafer boat is sent into the reaction chamber 401; The heater 402 heats the reaction chamber 401 to 800 to 1200 degrees Celsius for 1 to 10 hours, and anneals the wafer (substrate) 200 on the wafer boat 403 in the reaction chamber 401.
  • the foregoing annealing equipment may also be used to perform the first annealing.
  • the supplied process gas includes N 2 . Therefore, after the first annealing, the substrate in the foregoing embodiment can be directly subjected to the second annealing through the annealing equipment without removing the wafer boat from the reaction chamber 401, which saves process steps.
  • the wafer (substrate) 200 to be annealed is first placed on the support structure 404 on the wafer boat 403; then the wafer boat is sent into the reaction chamber 401; the gas supply end is fed into the reaction chamber 401 N 2 , the heater 402 heats the reaction chamber 401 to the first annealing temperature, and performs the first annealing; the gas supply end stops supplying N 2 into the reaction chamber 401, and the gas supply end supplies the reaction chamber 401.
  • the heater 402 continues to heat up, heats the reaction chamber 401 to the second annealing temperature, and performs the second annealing.

Abstract

一种外延层和3D NAND存储器的形成方法、退火设备，其中所述外延层的形成方法，先进行第一退火，以消除堆叠结构中产生的应力，在进行第一退火时，所述凹槽的侧壁和底部表面形成含硅的混合物，因而第一退火后，进行第二退火，进行第二退火，以去除所述凹槽侧壁和底部表面的含硅的混合物，使得后续在形成外延层时的生长界面为纯净的衬底材料界面，防止凹槽中形成的外延层中产生孔洞缺陷。

Description

外延层和3D NAND存储器的形成方法、退火设备 技术领域
本发明涉及半导体制作领域，尤其涉及一种外延层和3D NAND存储器的形成方法、退火设备。
背景技术
NAND闪存是一种比硬盘驱动器更好的存储设备，随着人们追求功耗低、质量轻和性能佳的非易失存储产品，在电子产品中得到了广泛的应用。目前，平面结构的3D NAND闪存已近实际扩展的极限，为了进一步的提高存储容量，降低每比特的存储成本，提出了3D结构的3D NAND存储器。
在3D NAND存储器结构中，采用垂直堆叠多层数据存储单元的方式，实现堆叠式的3D NAND存储器结构。现有3D NAND存储器的形成过程一般包括：在衬底上形成氮化硅层和氧化硅层交替层叠的堆叠层；刻蚀所述堆叠层，在堆叠层中形成沟道孔，在形成沟道孔后，刻蚀沟道孔底部的衬底，在衬底中形成凹槽；在沟道孔底部的凹槽中，通过选择性外延生长(Selective Epitaxial Growth)形成外延硅结构，通常该外延硅结构也称作SEG；在所述沟道孔中形成存储区；去除氮化硅层，在去除氮化硅层的位置形成栅极金属。
现有的工艺形成的外延硅结构(SEG)时，外延硅结构(SEG)的底部区域中容易产生孔洞缺陷，使得外延硅结构(SEG)与衬底的电接触性能较差，影响了3D NAND存储器的性能。
发明内容
本发明所要解决的技术问题是怎样防止形成的外延层(SEG)中形成孔洞缺陷，提高外延硅结构(SEG)与衬底的电接触性能。
为解决前述问题，本发明提供了一种外延层的形成方法，包括：
提供衬底，所述衬底上形成有第一绝缘层和第二绝缘层交替层叠的堆叠结构；刻蚀所述堆叠结构，形成贯穿堆叠结构的若干沟道孔；沿沟道孔刻蚀沟道孔底部的衬底，在衬底中形成凹槽；在形成凹槽后，进行第一退火，在进行第一退火时，所述凹槽的侧壁和底部表面形成含硅的混合物；在进行第一退火后，进行第二退火，以去除所述含硅的混合物；进行所述第二退火后，采用选择性外延工艺在所述凹槽中形成外延层，所述外延层填充满所述凹槽。
可选的，所述含硅的混合物中除了还有硅元素外，还含有第一退火时采用气体的所含元素、形成第一绝缘层的源气体和/或副产物所含的元素、形成第二绝缘层的源气体和/或副产物所含的元素中的一种或几种。
可选的，所述第一退火的气体氛围为N 2，所述第二退火的气体氛围为H 2。
可选的，所述第一绝缘层的材料和第二绝缘层的材料为氧化硅、氮化硅、氮氧化硅、氮碳化硅中的一种，且所述第一绝缘层的材料和第二绝缘层的材料不相同。
可选的，所述含硅的混合物中除了还有硅元素外，还包括N元素、C元素、H元素和O元素中的一种或几种。
可选的，所述第二退火时温度为800～1200摄氏度，时间为1～10小时，腔室的压强小于100托。
可选的，进行第二退火时，所述第二退火采用的气体与含硅的混合物反应，形成气态的反应物。
可选的，进行第二退火后，所述凹槽的侧壁的晶面指数为(111)。
本发明还提供了一种3D NAND存储器的形成方法，包括：
提供衬底，所述衬底上形成有第一绝缘层和第二绝缘层交替层叠的堆叠结构；刻蚀所述堆叠结构，形成贯穿堆叠结构的若干沟道孔；沿沟道孔刻蚀沟道孔底部的衬底，在衬底中形成凹槽；在形成凹槽后，进行第一退火，在进行第一退火时，所述凹槽的侧壁和底部表面形成含硅的混合物；在进行第一退火后，进行第二退火，以去除所述含硅的混合物；进行所述第二退火后，采用选择性外延工艺在所述凹槽中形成外延层，所述外延层填充满所述凹槽；在所述外延层上的沟道孔中形成存储结构；去除所述第一绝缘层，在第一绝缘层被去除后对应的位置形成金属栅极。
可选的，所述含硅的混合物中除了还有硅元素外，还含有第一退火时采用气体的所含元素、形成第一绝缘层的源气体和/或副产物所含的元素、形成第二绝缘层的源气体和/或副产物所含的元素中的一种或几种。
可选的，所述第一退火的气体氛围为N 2，所述第二退火的气体氛围为H 2。
可选的，所述第一绝缘层的材料和第二绝缘层的材料为氧化硅、氮化硅、氮氧化硅、氮碳化硅中的一种，且所述第一绝缘层的材料和第二绝缘层的材料 不相同。
可选的，所述含硅的混合物中除了还有硅元素外，还包括N元素、C元素和H元素中的一种或几种。
可选的，所述第二退火时温度为800～1200摄氏度，时间为1～10小时，腔室的压强小于100托。
可选的，进行第二退火时，所述第二退火采用的气体与含硅的混合物反应，形成气态的反应物。
可选的，进行第二退火后，所述凹槽的侧壁的晶面指数为(111)。
本发明还提供了对前述的衬底进行第二退火的退火设备，包括：
反应腔室；
至于反应腔室中的晶舟，所述晶舟具有向内凹陷的舟体，舟体的内侧壁上具有若干放置晶圆的支撑结构，所述晶舟的舟体的拐弯处以及支撑结构的厚度大于舟体其他部分的厚度；
气体供入端，用于向反应腔室供入工艺气体；
加热器，用于对反应腔室中的晶舟上的晶圆进行加热。
可选的，所述舟体的拐弯处以及支撑结构的厚度比舟体其他部分的厚度大0.5～5厘米。
可选的，所述舟体的拐弯处以及支撑结构的厚度为1.1～10厘米。
可选的，加热器加热时反应腔室中的温度为800～1200摄氏度，加热的时间为1～10小时。可选的，所述供入的工艺气体包括H 2。
可选的，所述退火设备还可以用于进行第一退火。
可选的，进行第一退火时，所述供入的工艺气体包括N 2。
与现有技术相比，本发明技术方案具有以下优点：
本发明的外延层的形成方法，在形成沟道孔和凹槽后，先进行第一退火，以消除堆叠结构中产生的应力，在进行第一退火时，所述凹槽的侧壁和底部表面会形成含硅的混合物，因而第一退火后，进行第二退火，以去除所述凹槽侧壁和底部表面的含硅的混合物，使得后续在形成外延层时的生长界面为纯净的衬底材料界面，防止凹槽中形成的外延层中产生孔洞缺陷。
进一步，所述第一绝缘层的材料和第二绝缘层的材料为氧化硅、氮化硅、 氮氧化硅、氮碳化硅中的一种，形成第一绝缘层和第二绝缘层时，部分源气体(化学气相沉积工艺采用的气体)元素(比如C、H、N、O)和副产物元素(比如C、H、N)会陷在(trap)或残留在形成的第一绝缘层和第二绝缘层，在进行第一退火时，陷入(trap)或残留的元素在高温下会被释放，而扩散到凹槽206底部和侧壁表面，与凹槽底部和侧壁表面的单晶衬底材料反应形成复杂的含硅混合物，因而所述含硅的混合物中除了还有硅元素外，还包括N元素、C元素、H元素O元素中的一种或几种，通过含H 2的第二退火能去除该含硅的混合物。
进一步，采用H 2进行第二退火时，所述第二退火时温度为800～1200摄氏度，时间为1～10小时，腔室的压强小于100托，本实施例中采用高温和长时间的退火，使得含硅的混合物能更干净和更高效的去除。
本发明的3D NAND存储器的形成方法，进行第二退火，去除所述凹槽侧壁和底部表面的含硅的混合物，使得在形成外延层时的生长界面为纯净的衬底材料界面，防止凹槽中形成的外延层中产生孔洞缺陷，因而外延层与衬底之间的导电性能不会受到影响，提高了3D NAND存储器的性能。
本发明的退火设备，所述晶舟的舟体的拐弯处以及支撑结构的厚度大于舟体其他部分的厚度，以使得晶舟能经受高温(大于800摄氏度)、长时间(大于1小时)的退火，防止晶舟舟体在脆弱的拐弯处(比如晶舟舟体的侧壁和底部的交接处)以及支撑结构处产生裂痕或碎裂，即本申请的退火设备能实现高温、长时间的退火，而且可以实现批量晶圆的退火处理。因而采用本发明的退火设备能对前述方案中的晶圆(衬底)进行第二退火时，在提高效率的同时，去除凹槽侧壁和底部表面的含硅混合物的效果也较好。
附图说明
图1-4为本发明一实施例外延层的形成过程的结构示意图；
图5-9为本发明另一实施例外延层形成过程的结构示意图；
图10-11为本发明另一实施例3D NAND存储器的结构示意图；
图12为本发明另一实施例退火设备的结构示意图。
具体实施方式
如背景技术所言，现有的工艺形成的外延硅结构(SEG)的底部区域中容 易产生孔洞缺陷，使得外延硅结构(SEG)与衬底的电接触性能较差，影响了3D NAND存储器的性能。
研究发现，现有外延硅结构(SEG)的底部区域中容易产生孔洞缺陷的原因为：在3D NAND存储器制作过程中，沟道孔底部的凹槽的侧壁和底部表面会形成复杂的含硅混合物，该含硅混合物使得凹槽侧壁和底部不能保持纯单晶硅的状态，当采用选择外延工艺在凹槽中形成外延硅结构(SEG)时，由于含硅混合物表面和单晶硅表面的硅生长速率不同，使得形成外延硅结构(SEG)中容易产生孔洞缺陷。下面结合附图1-4对前述原因产生的具体过程以及孔洞缺陷形成的具体过程进行详细说明。
参考图1，在衬底100上形成氮化硅层102和氧化硅层103交替层叠的堆叠层104，所述堆叠结构104和衬底100之间还可以形成隔离层101。
参考图2，刻蚀所述堆叠层104，在堆叠层104中形成沟道孔105，在形成沟道孔105后，刻蚀沟道孔105底部的衬底100，在衬底100中形成凹槽106。
结合参考图3和图4，在形成凹槽106后，在氮气(N 2)氛围中对堆叠结构104进行退火，以释放堆叠结构104中存在的应力。经过进一步研究发现，由于氮化硅层102和氧化硅层103是通过化学气相沉积工艺形成，在形成氮化硅层102和氧化硅层103时特别是多层堆叠的氮化硅层102和氧化硅层103时，部分源气体(化学气相沉积工艺采用的气体)元素(比如C、H、N、O)和副产物元素(比如C、H)会陷在(trap)或残留在形成的氮化硅层102和氧化硅层103或堆叠结构104中，这些元素在进行退火时会从氮化硅层102和氧化硅层103或堆叠结构104中被释放而扩散到凹槽106底部和侧壁表面，与凹槽106底部和侧壁表面的单晶衬底材料(Si)反应形成复杂的含硅混合物107，含硅混合物107的存在使得后续通过选择性外延生长形成外延硅结构时的界面不是纯净的单晶硅界面，因而选择性外延生长(Selective Epitaxial Growth)硅时，复杂的含硅混合物107表面和单晶硅的表面的生长速率不一样，使得凹槽中形成的外延硅结构109(参考图4)具有孔洞缺陷108(参考图4)，且该孔洞缺陷108主要存在于外延硅结构109于衬底100接触的界面上以及外延硅结构109与含硅混合物107的接触界面上，或者如果凹槽很深，所述孔洞缺陷108还会存在于外延硅结构109中。
虽然在一些实施例中，在凹槽106中形成外延硅结构109结构之前会进行清洗工艺，但是无论是湿法清洗还是干法清洗都不能干净的去除含硅的混合物，并且湿法清洗和干法清洗均会引入新的杂质，使得采用选择性外延生长形成外延硅结构109的界面仍不能为纯净的单晶硅，因而形成的外延硅结构109中仍会存在孔洞缺陷。
为此，本发明另一实施例中提供了一种外延层和3D NAND存储器的形成方法、退火设备，其中所述外延层的形成方法，在形成沟道孔和凹槽后，先进行第一退火，以消除堆叠结构中产生的应力，在进行第一退火时，所述凹槽的侧壁和底部表面会形成含硅的混合物，因而第一退火后，进行第二退火，以去除所述凹槽侧壁和底部表面的含硅的混合物，使得后续在形成外延层时的生长界面为纯净的衬底材料界面，防止凹槽中形成的外延层中产生孔洞缺陷。
为使本发明实施例的上述目的、特征和优点能够更加明显易懂，下面结合附图对本发明的具体实施方式做详细的说明。在详述本发明实施例时，为便于说明，示意图会不依一般比例作局部放大，而且所述示意图只是示例，其在此不应限制本发明的保护范围。此外，在实际制作中应包含长度、宽度及深度的三维空间尺寸。
图5-11为本发明另一实施例外延层的形成过程的结构示意图。
参考图5，提供衬底200，所述衬底200上形成有第一绝缘层202和第二绝缘层203交替层叠的堆叠结构204。
所述衬底200的材料可以为单晶硅(Si)、单晶锗(Ge)、或硅锗(GeSi)、碳化硅(SiC)；也可以是绝缘体上硅(SOI)，绝缘体上锗(GOI)；或者还可以为其它的材料，例如砷化镓等Ⅲ-Ⅴ族化合物。本实施例中，所述衬底200的材料为单晶硅(Si)。
本实施例中，所述第一绝缘层202作为牺牲层，后续通过去除第一绝缘层202，在第一绝缘层202所在的位置形成金属栅极。
所述第一绝缘层202的材料和第二绝缘层203的材料不相同，在一实施例中，所述第一绝缘层202的材料和第二绝缘层203的材料为氧化硅、氮化硅、氮氧化硅、氮碳化硅中的一种。本实施例中，所述第一绝缘层202的材料为氮化硅，第二绝缘层203的材料为氧化硅，所述第一绝缘层202和第二绝缘层203 的形成工艺为化学气相沉积工艺。
采用化学气相沉积工艺形成膜层的过程一般包括：向腔室中通入源气体，源气体反应在衬底上形成膜层。以形成氧化硅层(第二绝缘层203)进行具体说明，在一实施例中，采用化学气相沉积工艺形成氧化硅层(第二绝缘层203)的过程包括：向反应腔室中通入源气体，所述源气体包括硅源气体和氧源气体，所述硅源气体为硅烷或TEOS，所述氧源气体为O 2、CO或ON 2，所述硅源气体和氧源气体的流量为：100标准毫升/分钟～8000标准毫升/分钟，温度为：300摄氏度～800摄氏度，压强为：3托～200托。
化学气相沉积工艺形成所述第一绝缘层202和第二绝缘层203时特别时形成多层的堆叠结构104时，部分源气体(化学气相沉积工艺采用的气体)元素(比如C、H、N、O)和副产物元素(比如C、H、N)会陷在(trap)或残留在形成的第一绝缘层202和第二绝缘层203。具体到本实施例中，在形成氮化硅材料的第一绝缘层202时，C、H中的一种或几种元素可能陷在(trap)或残留第一绝缘层202中，在形成氧化硅材料的第二绝缘层203时，C、H、N、O元素中的一种或几种可能会陷在(trap)或残留第二绝缘层203中。
需要说明的是，第一绝缘层202和第二绝缘层203交替层叠是指在形成一层第一绝缘层202后，相应的在第一绝缘层202表面形成一层第二绝缘层203，后续依次进行形成第一绝缘层202和第二绝缘层203的步骤。
所述第一绝缘层202和第二绝缘层203的层数或者堆叠结构204的层数，根据垂直方向所需形成的存储单元的个数来确定，所述第一绝缘层202和第二绝缘层203的层数或者堆叠结构204的层数可以为8层、32层、64层等，堆叠层的层数越多，越能提高集成度。本实施例中，仅以所述第一绝缘层202和第二绝缘层203的层数或者堆叠结构204的层数为5层作为示例进行说明。
在一实施例中，所述堆叠结构204和衬底200之间还可以形成底层绝缘层201，所述底层绝缘层201的材料为氧化硅，通过热氧化工艺形成，所述底层绝缘层201可以降低堆叠结构204对衬底200的应力作用。
参考图6，刻蚀所述堆叠结构204，形成贯穿堆叠结构204的若干沟道孔205；沿沟道孔205刻蚀沟道孔205底部的衬底200，在衬底200中形成凹槽206。
所述沟道孔205中后续形成存储结构，所述凹槽206中后续形成外延层。
在一实施例中，在刻蚀所述堆叠结构204之前，在所述堆叠结构的表面形成图形化的掩膜层，在刻蚀所述堆叠结构时，以所述图形化的掩膜层作为掩膜。
刻蚀所述堆叠结构204采用各向异性的干法刻蚀工艺，比如可以为等离子刻蚀工艺或反应离子刻蚀工艺，刻蚀时采用的气体包括含碳氟元素的气体。
在一实施例中，所述刻蚀衬底200形成凹槽206的步骤可以是在刻蚀堆叠结构204形成沟道孔205步骤后通过过刻蚀工艺形成。在其他实施例中，所述刻蚀衬底200形成凹槽206的步骤也可以在刻蚀堆叠结构204形成沟道孔205步骤后采用额外的刻蚀工艺形成。刻蚀堆叠结构204形成沟道孔205步骤和刻蚀衬底200形成凹槽206的步骤可以在同一刻蚀腔室中完成也可以在不同刻蚀腔室中完成。
本实施例中，形成的凹槽206侧壁呈弧状，且离衬底200的表面越远，凹槽206的宽度越小。需要说的是，在其他实施例中，所述凹槽206的侧壁可以为其他的形状。
参考图7，在形成凹槽206后，进行第一退火31，在进行第一退火31时，所述凹槽206的侧壁和底部表面形成含硅的混合物207。
进行第一退火31的目的是：消除堆叠结构204中的应力以及堆叠结构204与衬底200之间的应力，以防止堆叠结构由于应力的作用而倒塌。
进行第一退火31的气体氛围为惰性气体氛围，以防止对衬底200造成氧化。本实施例中所述第一退火的气体氛围为N 2，N 2的不会对衬底造成氧化，并且价格低廉。在其他实施例中，可以采用气体的惰性气体氛围，比如Ar气。
研究发现，在进行第一退火31时，第一绝缘层202和第二绝缘层203或堆叠结构204中陷入(trap)或残留的元素在高温下会被释放，而扩散到凹槽206底部和侧壁表面，与凹槽206底部和侧壁表面的单晶衬底材料反应形成复杂的含硅混合物207。因而，所述含硅的混合物中除了还有硅元素外，还含有形成第一绝缘层的源气体和/或副产物所含的元素、形成第二绝缘层的源气体和/或副产物所含的元素中的一种或几种。
本实施例中，所述含硅的混合物207中除了还有硅元素外，还包括N元素、C元素、H元素和O元素中的一种或几种。
含硅的混合物207的存在使得后续形成外延层的界面(凹槽206的侧壁和底部表面)不是纯净的衬底材料(如单晶硅或单晶锗等)界面，如果直接在凹槽206中形成外延层，外延层中容易形成孔洞缺陷。
结合参考图7和图8，在进行所述第一退火31后，进行第二退火32，以去除所述凹槽206侧壁和底部表面的含硅的混合物207。
所述第二退火32在退火设备的退火腔室中进行，在进行第二退火32时，第二退火32采用的气体与含硅的混合物207反应，形成气态的反应物，被直接排出退火腔室，从而去除凹槽206侧壁和底部表面的含硅的混合物207，使得后续在形成外延层时的生长界面为纯净的衬底材料界面。
本实施例中，所述第二退火的气体氛围为H 2，采用H 2不仅能去除含硅的混合物207，而且不会对沟槽206暴露的衬底200造成损伤。采用H 2去除含硅的混合物207的原理请参考下面的公式：
Si-+H°→Si-H
在进行第二退火时，H 2与含硅混合物207中的Si反应形成Si-H键，Si-H键继续与剩余的混合物反应形成气态的反应物。
本实施例中，采用H 2进行第二退火32时，所述第二退火时温度为800～1200摄氏度，时间为1～10小时，腔室的压强小于100托，本实施例中采用高温和长时间的退火，使得含硅的混合物207能更干净和更高效的去除。
在一实施例中，在进行前述参数下的第二退火32后，所述凹槽206的四周侧壁的晶面指数为(111)，后续在采用选择性外延工艺在所述凹槽206中形成外延层时，使得形成的外延层与衬底200构成一体的结构，使得两者之间没有接触界面，并且外延层中没有孔洞缺陷。需要说明的是，晶面指数(indices of crystal face)是晶体的常数之一，是晶面在3个结晶轴上的截距系数的倒数比，当化为整数比后，所得出的3个整数称为该晶面的米勒指数(Miller index)。
本发明实施例中，在进行第一退火31后，直接进行第二退火32，中间不进行额外的干法清洗和/或湿法清洗。
所述第一退火31和第二退火32可以在同一退火设备进行，也可以在不同的退火设备中进行。
结合参考图9和图10，进行第二退火32后，采用选择性外延工艺在所述凹槽206中形成外延层210，所述外延层210填充满所述凹槽206。
本实施例中，所述形成的外延层210的材料与衬底200的材料相同，所述外延层的材料为硅，外延层210的表面高于衬底200的表面。在形成外延层210时，由于凹槽206侧壁或底部表面为纯净的单晶硅界面，因而使得该界面上或者该界面一段距离上的硅的成长速率保持一致或相差很小，从而防止形成的外延层210中形成孔洞缺陷。
在一实施例中，所述硅材料的外延层210的形成工艺为：反应气体包括硅源气体、HCl和H 2，其中，硅源气体为SiH 4、SiH 2Cl 2、SiHCl 3和SiH 3Cl中的一种或几种，硅源气体的流量为10sccm至900sccm，HCl流量为8sccm至950sccm，H 2流量为150sccm至5000sccm，反应腔室温度为600度至850摄氏度，反应腔室压强为1托至100托。
在其他实施例中，所述外延层可210可以采用与衬底材料不同的半导体材料，比如衬底200材料为单晶硅时，所述外延层210的材料可以为硅或锗硅。所述外延层的高度也可以根据实际需要进行设定。
本发明另一实施例还提供了一种3D NAND存储器的形成方法，具体请参考图10-11。需要说明的是，本实施例中与前述实施例中相同或相似结构的描述或限定，在本实施例中不再赘述，具体请参考前述实施例中相应部分的描述或限定。
参考图10，图10在图9的基础上进行，即采用前述实施例中的方式在形成外延层210后；在所述外延层210上形成存储结构。
所述存储结构至少包括电荷捕获层和沟道层，在本实施例中，电荷捕获层为ONO层，即氧化硅-氮化硅-氧化硅的叠层，沟道层为多晶硅层。在一具体的实施例中，可以在沟道孔220中依次淀积ONO层、多晶硅层以及氧化硅层，来形成存储结构。
参考图11，去除所述第一绝缘层202(参考图10)，在第一绝缘层202被去除后对应的位置形成金属栅极211。
去除所述第一绝缘层202采用湿法刻蚀，湿法刻蚀采用的溶液对第一绝缘层202的刻蚀速率远大于对第二绝缘层203和外延层210的刻蚀速率。本实施 例中，所述湿法刻蚀采用的刻蚀溶液为磷酸。
本实施例3D NAND存储器的形成方法，由于形成的外延层210中没有孔洞缺陷，因而外延层210与衬底200之间的导电性能不会受到影响，提高了3D NAND存储器的性能。
本发明另一实施例中还提供了一种对前述衬底进行第二退火的退火设备，请参考图12，包括：
反应腔室401；
至于反应腔室401中的晶舟403，所述晶舟403具有向内凹陷的舟体，舟体的内侧壁上具有若干放置晶圆的支撑结构404，所述晶舟403的舟体的拐弯处以及支撑结构404的厚度大于舟体其他部分的厚度；
气体供入端，用于向反应腔室供入反应气体；
加热器402，用于对反应腔室401中的晶舟403上的晶圆200进行加热。
所述晶舟403上具有若干支撑结构404，支撑结构404的材料与晶舟的材料相同，均为石英。若干支撑结构能够同时支撑若干晶圆进行退火。
在一实施例中，所述晶舟可以为一面具有开口的立方体，立方体的三个侧面或者与开口接触的两个相对的侧面上设置有若干支撑结构404。
本实施例中，所述晶舟403的舟体的拐弯处以及支撑结构404的厚度大于舟体其他部分的厚度，以使得晶舟403能经受高温(大于800摄氏度)、长时间(大于1小时)的退火，防止晶舟舟体在脆弱的拐弯处(比如晶舟舟体的侧壁和底部的交接处)以及支撑结构处产生裂痕或碎裂。
在一实施例中，所述舟体的拐弯处以及支撑结构的厚度比舟体其他部分的厚度大0.5～5厘米。在具体的实施例中，所述舟体的拐弯处以及支撑结构的厚度为1.1～10厘米。
所述加热器402加热时反应腔室401中的温度可以为800～1200摄氏度，加热的时间为1～10小时。
所述退火设备还可以包括内部热电偶405和外部热电偶406，内部热电偶405用于测量反应腔室401的温度，外部热电偶406用于测量加热器402的温度。
本实施例中的退火设备可以进行高温(大于800摄氏度)、长时间(大于1 小时)的退火，在退火时晶舟不会产生裂痕或碎裂，而且可以实现批量晶圆的退火处理。因而采用本实施例中的退火设备能对前述实施例中的晶圆(衬底)进行第二退火时，在提高效率的同时，去除凹槽侧壁和底部表面的含硅混合物的效果也较好。
采用前述的退火设备进行第二退火时，所述供入的工艺气体包括H 2。
采用本实施例中的退火设备在进行第二退火时，先将需要退火的晶圆(衬底)200置于晶舟403上的支撑结构404上；然后将晶舟送入反应腔室401；加热器402对反应腔室401加热到800～1200摄氏度，加热的时间为1～10小时，对反应腔室401中晶舟403上的晶圆(衬底)200进行退火。
在另一实施例中，采用前述的退火设备还可以进行第一退火，进行第一退火时，所述供入的工艺气体包括N 2。因而通过所述退火设备可以对前述实施例中的所述衬底在进行第一退火后，直接进行第二退火，无需将晶舟移出反应腔室401，节省了工艺步骤。具体的，先将需要退火的晶圆(衬底)200置于晶舟403上的支撑结构404上；然后将晶舟送入反应腔室401；气体供入端向反应腔室401中供入N 2，加热器402对反应腔室401加热到第一退火温度，进行第一退火；气体供入端停止向反应腔室401中供入N 2，气体供入端向反应腔室401中供入H 2，加热器402继续升温，对反应腔室401加热到第二退火温度，进行第二退火。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (23)

  1. 一种外延层的形成方法，其特征在于，包括：
    提供衬底，所述衬底上形成有第一绝缘层和第二绝缘层交替层叠的堆叠结构；
    刻蚀所述堆叠结构，形成贯穿堆叠结构的若干沟道孔；
    沿沟道孔刻蚀沟道孔底部的衬底，在衬底中形成凹槽；
    在形成凹槽后，进行第一退火，在进行第一退火时，所述凹槽的侧壁和底部表面形成含硅的混合物；
    在进行第一退火后，进行第二退火，以去除所述含硅的混合物；
    进行所述第二退火后，采用选择性外延工艺在所述凹槽中形成外延层，所述外延层填充满所述凹槽。
  2. 如权利要求1所述的外延层的形成方法，其特征在于，所述含硅的混合物中除了还有硅元素外，还含有第一退火时采用气体的所含元素、形成第一绝缘层的源气体和/或副产物所含的元素、形成第二绝缘层的源气体和/或副产物所含的元素中的一种或几种。
  3. 如权利要求1或2所述的外延层的形成方法，其特征在于，所述第一退火的气体氛围为N 2，所述第二退火的气体氛围为H 2。
  4. 如权利要求1所述的外延层的形成方法，其特征在于，所述第一绝缘层的材料和第二绝缘层的材料为氧化硅、氮化硅、氮氧化硅、氮碳化硅中的一种，且所述第一绝缘层的材料和第二绝缘层的材料不相同。
  5. 如权利要求4所述的外延层的形成方法，其特征在于，所述含硅的混合物中除了还有硅元素外，还包括N元素、C元素、H元素和O元素中的一种或几种。
  6. 如权利要求1所述的外延层的形成方法，其特征在于，所述第二退火时温度为800～1200摄氏度，时间为1～10小时，腔室的压强小于100托。
  7. 如权利要求1或2所述的外延层的形成方法，其特征在于，进行第二退火时，所述第二退火采用的气体与含硅的混合物反应，形成气态的反应物。
  8. 如权利要求1所述的外延层的形成方法，其特征在于，进行第二退火后，所述凹槽的侧壁的晶面指数为(111)。
  9. 一种3D NAND存储器的形成方法，其特征在于，包括：
    提供衬底，所述衬底上形成有第一绝缘层和第二绝缘层交替层叠的堆叠结构；
    刻蚀所述堆叠结构，形成贯穿堆叠结构的若干沟道孔；
    沿沟道孔刻蚀沟道孔底部的衬底，在衬底中形成凹槽；
    在形成凹槽后，进行第一退火，在进行第一退火时，所述凹槽的侧壁和底部表面形成含硅的混合物；
    在进行第一退火后，进行第二退火，以去除所述含硅的混合物；
    进行所述第二退火后，采用选择性外延工艺在所述凹槽中形成外延层，所述外延层填充满所述凹槽；
    在所述外延层上的沟道孔中形成存储结构；
    去除所述第一绝缘层，在第一绝缘层被去除后对应的位置形成金属栅极。
  10. 如权利要求9所述的3D NAND存储器的形成方法，其特征在于，所述含硅的混合物中除了还有硅元素外，还含有第一退火时采用气体的所含元素、形成第一绝缘层的源气体和/或副产物所含的元素、形成第二绝缘层的源气体和/或副产物所含的元素中的一种或几种。
  11. 如权利要求9或10所述的3D NAND存储器的形成方法，其特征在于，所述第一退火的气体氛围为N 2，所述第二退火的气体氛围为H 2。
  12. 如权利要求9所述的3D NAND存储器的形成方法，其特征在于，所述第一绝缘层的材料和第二绝缘层的材料为氧化硅、氮化硅、氮氧化硅、氮碳化硅中的一种，且所述第一绝缘层的材料和第二绝缘层的材料不相同。
  13. 如权利要求12所述的外延层的形成方法，其特征在于，所述含硅的混合物中除了还有硅元素外，还包括N元素、C元素和H元素中的一种或几种。
  14. 如权利要求9所述的3D NAND存储器的形成方法，其特征在于，所述第二退火时温度为800～1200摄氏度，时间为1～10小时，腔室的压强小于100托。
  15. 如权利要求9或10所述的3D NAND存储器的形成方法，其特征在于，进行第二退火时，所述第二退火采用的气体与含硅的混合物反应，形成气态 的反应物。
  16. 如权利要求9所述的3D NAND存储器的形成方法，其特征在于，进行第二退火后，所述凹槽的侧壁的晶面指数为(111)。
  17. 一种对权利要求1或9中的衬底进行第二退火的退火设备，其特征在于，包括：
    反应腔室；
    至于反应腔室中的晶舟，所述晶舟具有向内凹陷的舟体，舟体的内侧壁上具有若干放置晶圆的支撑结构，所述晶舟的舟体的拐弯处以及支撑结构的厚度大于舟体其他部分的厚度；
    气体供入端，用于向反应腔室供入工艺气体；
    加热器，用于对反应腔室中的晶舟上的晶圆进行加热。
  18. 如权利要求17所述的退火设备，其特征在于，所述舟体的拐弯处以及支撑结构的厚度比舟体其他部分的厚度大0.5～5厘米。
  19. 如权利要求18所述的退火设备，其特征在于，所述舟体的拐弯处以及支撑结构的厚度为1.1～10厘米。
  20. 如权利要求17所述的退火设备，其特征在于，加热器加热时反应腔室中的温度为800～1200摄氏度，加热的时间为1～10小时。
  21. 如权利要求17所述的退火设备，其特征在于，所述供入的工艺气体包括H 2。
  22. 如权利要求18所述的退火设备，其特征在于，所述退火设备还可以用于进行第一退火。
  23. 如权利要求22所述的退火设备，其特征在于，进行第一退火时，所述供入的工艺气体包括N 2。
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