TWI563618B - - Google Patents
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- Publication number
- TWI563618B TWI563618B TW101111894A TW101111894A TWI563618B TW I563618 B TWI563618 B TW I563618B TW 101111894 A TW101111894 A TW 101111894A TW 101111894 A TW101111894 A TW 101111894A TW I563618 B TWI563618 B TW I563618B
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- Taiwan
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- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
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US9806045B2 (en) * | 2013-08-29 | 2017-10-31 | Taiwan Semiconductor Manufacturing Company Ltd. | Interconnection structure including a metal post encapsulated by solder joint having a concave outer surface |
JP6238121B2 (ja) | 2013-10-01 | 2017-11-29 | ローム株式会社 | 半導体装置 |
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JP7214966B2 (ja) * | 2018-03-16 | 2023-01-31 | 富士電機株式会社 | 半導体装置及び半導体装置の製造方法 |
US11094862B2 (en) * | 2018-06-13 | 2021-08-17 | Prilit Optronics, Inc. | Semiconductor device with through holes on bonding parts and bonding method thereof |
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DE102019104334A1 (de) * | 2019-02-20 | 2020-08-20 | Infineon Technologies Ag | Halbleiteranordnung und verfahren zum herstellen einer hableiteranordnung |
CN111885826B (zh) * | 2020-07-23 | 2022-07-26 | 东莞市豪顺精密科技有限公司 | 一种单层印刷线路板的覆铜层结构 |
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