TWI563540B - Semiconductor device manufacturing method - Google Patents

Semiconductor device manufacturing method

Info

Publication number
TWI563540B
TWI563540B TW102136511A TW102136511A TWI563540B TW I563540 B TWI563540 B TW I563540B TW 102136511 A TW102136511 A TW 102136511A TW 102136511 A TW102136511 A TW 102136511A TW I563540 B TWI563540 B TW I563540B
Authority
TW
Taiwan
Prior art keywords
semiconductor device
device manufacturing
manufacturing
semiconductor
Prior art date
Application number
TW102136511A
Other languages
English (en)
Other versions
TW201423840A (zh
Inventor
Kazuya Yamaguchi
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Publication of TW201423840A publication Critical patent/TW201423840A/zh
Application granted granted Critical
Publication of TWI563540B publication Critical patent/TWI563540B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02441—Group 14 semiconducting materials
    • H01L21/0245—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/5442—Marks applied to semiconductor devices or parts comprising non digital, non alphanumeric information, e.g. symbols
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0878—Impurity concentration or distribution
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Power Engineering (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Composite Materials (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Recrystallisation Techniques (AREA)
TW102136511A 2012-10-12 2013-10-09 Semiconductor device manufacturing method TWI563540B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2012227526A JP6142496B2 (ja) 2012-10-12 2012-10-12 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
TW201423840A TW201423840A (zh) 2014-06-16
TWI563540B true TWI563540B (en) 2016-12-21

Family

ID=50454361

Family Applications (1)

Application Number Title Priority Date Filing Date
TW102136511A TWI563540B (en) 2012-10-12 2013-10-09 Semiconductor device manufacturing method

Country Status (4)

Country Link
US (1) US9111759B2 (zh)
JP (1) JP6142496B2 (zh)
CN (1) CN103730338B (zh)
TW (1) TWI563540B (zh)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201430957A (zh) * 2013-01-25 2014-08-01 Anpec Electronics Corp 半導體功率元件的製作方法
CN105453250A (zh) * 2013-08-08 2016-03-30 夏普株式会社 半导体元件衬底及其制造方法
JP2016131179A (ja) * 2015-01-13 2016-07-21 ソニー株式会社 半導体装置、および半導体装置の製造方法、固体撮像素子、撮像装置、並びに電子機器
CN104658889B (zh) * 2015-02-10 2017-10-24 上海华虹宏力半导体制造有限公司 两次沟槽型超级结器件的对准标记制造方法
DE102015120510A1 (de) 2015-11-26 2017-06-01 Infineon Technologies Austria Ag Verfahren zum Herstellen von Superjunction-Halbleitervorrichtungen mit einer Superstruktur in Ausrichtung mit einer Grundlage
DE102015122828A1 (de) * 2015-12-23 2017-06-29 Infineon Technologies Austria Ag Verfahren zum Herstellen einer Halbleitervorrichtung mit epitaktischen Schichten und einer Ausrichtungsmarkierung
US9711357B1 (en) 2016-03-21 2017-07-18 Infineon Technologies Austria Ag Method of manufacturing a semiconductor device with epitaxial layers and an alignment structure
JP6372709B2 (ja) 2016-04-20 2018-08-15 信越半導体株式会社 エピタキシャルウェーハの製造方法
CN105914233B (zh) * 2016-05-26 2018-09-18 东南大学 一种高鲁棒性快恢复超结功率半导体晶体管及其制备方法
CN106876469B (zh) * 2017-02-22 2020-01-03 江苏华弗半导体有限公司 一种超结器件的制造方法及超结器件
US10833021B2 (en) * 2017-06-29 2020-11-10 Alpha And Omega Semiconductor (Cayman) Ltd. Method for precisely aligning backside pattern to frontside pattern of a semiconductor wafer
CN107706148B (zh) * 2017-10-17 2020-09-08 吉林华微电子股份有限公司 改善光刻标记对准精度的方法、超级结产品的制备方法及超级结产品
JP7135422B2 (ja) * 2018-05-11 2022-09-13 富士電機株式会社 半導体装置の製造方法
CN110634897B (zh) * 2019-09-05 2021-09-14 成都微光集电科技有限公司 一种背照式近红外像素单元及其制备方法
CN117393586B (zh) * 2023-12-13 2024-04-05 合肥晶合集成电路股份有限公司 一种功率半导体器件及其制作方法
CN117894820A (zh) * 2024-03-15 2024-04-16 芯联越州集成电路制造（绍兴）有限公司 超结半导体器件及其制造方法

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TW444286B (en) * 2000-03-03 2001-07-01 United Microelectronics Corp Direct-aligned word line forming method for ROM
US20070082455A1 (en) * 2005-10-06 2007-04-12 Syouji Nogami Manufacturing method of semiconductor substrate
US20090273102A1 (en) * 2005-10-06 2009-11-05 Syouji Nogami Semiconductor Substrate and Method for Manufacturing the Same
TW201140761A (en) * 2010-04-06 2011-11-16 Soitec Silicon On Insulator Method for manufacturing a semiconductor substrate
JP2012004173A (ja) * 2010-06-14 2012-01-05 Fuji Electric Co Ltd 超接合半導体装置の製造方法

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US7195934B2 (en) * 2005-07-11 2007-03-27 Applied Materials, Inc. Method and system for deposition tuning in an epitaxial film growth apparatus
JP5150048B2 (ja) 2005-09-29 2013-02-20 株式会社デンソー 半導体基板の製造方法
JP4743611B2 (ja) 2006-02-16 2011-08-10 信越半導体株式会社 シリコンエピタキシャルウェーハの製造方法
JP2009176784A (ja) 2008-01-22 2009-08-06 Covalent Materials Tokuyama Corp 薄膜エピタキシャルウェーハの製造方法
US7902075B2 (en) * 2008-09-08 2011-03-08 Semiconductor Components Industries, L.L.C. Semiconductor trench structure having a sealing plug and method
CN101630637A (zh) * 2009-08-04 2010-01-20 上海集成电路研发中心有限公司 防止外延工艺中标记发生畸变的方法
CN102376531A (zh) * 2010-08-12 2012-03-14 上海华虹Nec电子有限公司 提高外延填充和cmp研磨后光刻标记信号的方法
JP5699526B2 (ja) 2010-10-21 2015-04-15 富士電機株式会社 半導体装置の製造方法

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW444286B (en) * 2000-03-03 2001-07-01 United Microelectronics Corp Direct-aligned word line forming method for ROM
US20070082455A1 (en) * 2005-10-06 2007-04-12 Syouji Nogami Manufacturing method of semiconductor substrate
US20090273102A1 (en) * 2005-10-06 2009-11-05 Syouji Nogami Semiconductor Substrate and Method for Manufacturing the Same
TW201140761A (en) * 2010-04-06 2011-11-16 Soitec Silicon On Insulator Method for manufacturing a semiconductor substrate
JP2012004173A (ja) * 2010-06-14 2012-01-05 Fuji Electric Co Ltd 超接合半導体装置の製造方法

Also Published As

Publication number Publication date
US20140106520A1 (en) 2014-04-17
TW201423840A (zh) 2014-06-16
JP6142496B2 (ja) 2017-06-07
JP2014082242A (ja) 2014-05-08
US9111759B2 (en) 2015-08-18
CN103730338A (zh) 2014-04-16
CN103730338B (zh) 2018-01-09

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