TWI552434B - 具有天線之半導體結構 - Google Patents
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q1/00—Details of, or arrangements associated with, antennas
- H01Q1/12—Supports; Mounting means
- H01Q1/22—Supports; Mounting means by structural association with other equipment or articles
- H01Q1/2283—Supports; Mounting means by structural association with other equipment or articles mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q21/00—Antenna arrays or systems
- H01Q21/0087—Apparatus or processes specially adapted for manufacturing antenna arrays
- H01Q21/0093—Monolithic arrays
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q21/00—Antenna arrays or systems
- H01Q21/06—Arrays of individually energised antenna units similarly polarised and spaced apart
- H01Q21/061—Two dimensional planar arrays
- H01Q21/065—Patch antenna array
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q9/00—Electrically-short antennas having dimensions not more than twice the operating wavelength and consisting of conductive active radiating elements
- H01Q9/04—Resonant antennas
- H01Q9/0407—Substantially flat resonant element parallel to ground plane, e.g. patch antenna
- H01Q9/045—Substantially flat resonant element parallel to ground plane, e.g. patch antenna with particular feeding means
- H01Q9/0457—Substantially flat resonant element parallel to ground plane, e.g. patch antenna with particular feeding means electromagnetically coupled to the feed line
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
- H01L2223/64—Impedance arrangements
- H01L2223/66—High-frequency adaptations
- H01L2223/6661—High-frequency adaptations for passive devices
- H01L2223/6677—High-frequency adaptations for passive devices for antenna, e.g. antenna included within housing of semiconductor device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
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Description
本發明是有關於一種半導體結構,且特別是有關於一種具有天線之半導體結構。
無線通訊裝置例如是手機(cell phone),需要天線已傳送及接收訊號。傳統上,無線通訊裝置包括天線及通訊模組(例如是具有無線射頻(Radio frequency,RF)通訊能力之一半導體封裝件),其各設於一電路板的不同部位。在傳統方式中,天線及通訊模組係分別製造且於放置在電路板後進行電性連接,因此導致高製造成本且難以完成輕薄短小的設計。
此外,隨著感測器、雷達、高資料率連結及聚束功率(focused power),毫米波(millimeter-wave)頻率的應用變成更多臨界點。短波長工作的優點係取決於尺寸及解析度。亦即,物理上小尺寸天線結構係必須的。
根據本發明之一實施例,提出一種半導體結構。半導體結構包括一基板、一電路部、一晶片及一天線。基板具有相
對之一第一表面及一第二表面。電路部形成於基板之第一表面上且包括一波導槽及一微帶線,微帶線與波導槽重疊。晶片設於電路部上。天線形成於基板之第二表面且與波導槽重疊。
根據本發明之另一實施例,提出一種半導體結構。半導體結構包括一基板、一整合被動元件層、一晶片及數個天線。基板具有相對之一第一表面及一第二表面。整合被動元件層形成於基板之第一表面,且包括數個波導槽及數個微帶線,微帶線重疊於波導槽,其中波導槽及微帶線排列成陣列型。晶片設於整合被動元件層上。天線形成於基板之第二表面且與波導槽重疊。
為了對本發明之上述及其他方面有更佳的瞭解,下文特舉較佳實施例,並配合所附圖式,作詳細說明如下:
100、200‧‧‧半導體結構
110‧‧‧基板
110b‧‧‧第一表面
110s、130s、131s‧‧‧外側面
110u‧‧‧第二表面
120‧‧‧晶片
121‧‧‧銲球
125‧‧‧底膠
130‧‧‧電路部
131‧‧‧接地層
1311‧‧‧屏蔽部
131a‧‧‧波導槽
132‧‧‧第一介電層
133‧‧‧微帶線
134‧‧‧第二介電層
135‧‧‧相位位移器
136‧‧‧圖案化導電層
137‧‧‧饋入電路
138‧‧‧導通孔
140‧‧‧天線
145‧‧‧天線介電層
150、150g‧‧‧銲球
L1‧‧‧長度
L2‧‧‧間距
第1A圖繪示依照本發明一實施例之半導體結構的剖視圖。
第1B圖,其繪示第1A圖之俯視圖。
第1C圖繪示第1A圖之底視圖。
第2圖繪示第1A圖中天線的X-Z平面的場形圖。
第3圖繪示第1A圖中天線的反射損失示意圖。
第4圖繪示依照本發明另一實施例之半導體結構的剖視圖。
請參照第1A圖,其繪示依照本發明一實施例之半導體結構的剖視圖。半導體結構100包括基板110、晶片120、電路部130、數個天線140、天線介電層145及數個銲球150。
基板110具有相對之第一表面110b及第二表面110u。若基板110過厚,則無線訊號難以從電路部130輻射至天線140;若基板110過薄,則電磁共振耦合(electromagnetic resonance coupling)難以產生。基板110可由玻璃製成,使無線訊號可從電路部130透過基板110輻射至天線140。玻璃具有高阻抗(electrical resistance)特性,使由天線140傳輸的無線訊號損失降低,因而提升由天線140傳輸的無線訊號的效率。此外,因為玻璃具有低K值(低介電常數),使天線140的效率更佳提昇。在一些例子中,基板110的厚度大約天線140之無線訊號波長的一半。例如,當操作頻率為60GHz,基板110的厚度大約是300微米。
電路部130形成於基板110的第一表面110b且可以是一多層結構。電路部130包括一接地層131、一第一介電層132、數個微帶線(microstrip line)133、一第二介電層134、數個內埋相位位移器135、一圖案化導電層136、一饋入電路137及數個導通孔138。
接地層131形成於基板110的第一表面110b且包括一屏蔽部(shielding portion)1311及數個波導槽131a。接地層131中未包含波導槽131a的部分被定義成屏蔽部1311,其中屏蔽部1311與晶片120重疊,如垂直方位所示。如第1A圖所示,接地層131透過導通孔138及圖案化導電層136電性連接於一接地銲球150g,其中接地銲球150g可電性連接於一外部接地,使接地層131接地。因為屏蔽部1311係電性連接於外部接地之
部分接地層131,屏蔽部1311因此接地且能提供屏蔽效果。屏蔽部1311的區域大於晶片120的區域,可避免晶片120受到電磁干擾(electromagnetic interference,EMI)。此外,屏蔽部1311可避免電路部130受到從微帶線133射向天線140之無線訊號的干擾。波導槽131a與微帶線133重疊,如產生耦合效應之垂直方位所示。
第一介電層132覆蓋接地層131、波導槽131a及屏蔽部1311。一些實施例中,第一介電層132可由例如是封膠(molding compound)、介電材料(如環氧樹脂(eposy))或預浸漬壓合層(prepreg lamination)製成。
微帶線133形成於第一介電層132下方,且透過第一介電層132與波導槽131a分離。當電流傳輸經微帶線133,產生於微帶線133與波導槽131a之間的第一耦合共振導致無線訊號從波導槽131a的邊緣輻射至基板110,然後產生於基板110與天線140之間的第二耦合共振導致無線訊透過天線140輻射至半導體結構100外。由於二耦合共振,故可增加從天線140輻射的無線訊號的頻寬。
第二介電層134覆蓋微帶線133且可由相似第一介電層132的材料製成。相位位移器135內埋於第二介電層134且透過導通孔138及圖案化導電層136電性連接於微帶線133及饋入電路137。相位位移器135例如是二極體,其可調整從天線140發射或被天線140接收之無線訊號的相位。另一例中,相位位移器135可以是功率放大器(power amplifier),以調變無線訊號的振幅。饋入電路137可把訊號從晶片120傳輸至天線140。
在一些例子中,電路部130可以是整合被動元件層。亦即,
電路部130包括至少一被動元件,例如是電阻、電容或電感,使電路部130及半導體結構100形成一具有無線功能之整合被動元件層(Integrated Passive Device,IPD)。接地層131、微帶線133、相位位移器135、圖案化導電層136、饋入電路137及天線140的形成可整合於整合被動元件層的製程中。此外,被動元件可形成於圖案化導電層136或其它層結構中。
電路部130、接地層131與基板110分別具有外側面130s、131s及110s,其中電路部130之外側面130s、接地層131之外側面131s與基板110之外側面110s實質上齊平。接地層131延伸至半導體結構100的邊界以提供電磁干擾屏蔽功能。
晶片120可以是收發晶片(transceiver chip),其設於電路部130上,以處理天線140的無線訊號。一些實施例中,晶片120可以是覆晶(flip chip),其以朝下方位設於電路部130上,且透過數個銲球121電性連接於電路部130。銲球121被底膠(under-fill)125包覆。另一例中,晶片120可以朝上方位設於設於電路部130上,且透過數個銲線(未繪示)電性連接於電路部130。形成於晶片與電路部130之間的底膠125包覆且保護銲球121。
天線140被天線介電層145覆蓋且形成於基板110之第二表面110u上。天線140與波導槽131a重疊,如產生於基板110與天線140之間的第二耦合共振的垂直方位所示。天線介電層145可由相似於第一介電層132的材料製成。
請參照第1B圖,其繪示第1A圖之俯視圖。本例中,波導槽131a形成2×2陣列型。另一例中,波導槽131a可形成n×m陣列型,以
改變天線140之無線訊號的場形,其中n及m可以是任意正整數。另一例中,波導槽131a可以排列成任意形式,且波導槽131a的數量可以是單個。實務上,波導槽131a的排列形式及數量可視天線140的阻抗匹配而定。
如第1B圖所示,微帶線133實質上垂直於波導槽131a延伸,使微帶線133及波導槽131a共同形成交叉結構,其導致近等振幅(near-equal amplitudes)的二簡併正交模態(near-degenerate orthogonal mode)的激態及90度相位差。天線140平行於微帶線133的長度L1愈長,共振頻率愈低。一例中,長度L1小於1000毫米,以獲得大頻寬之無線訊號及60GHz的天線。
相鄰二微帶線133之間距L2大約是天線140之無線訊號波長的一半,使輻射至相鄰二微帶線133的中間位置的無線訊號產生破壞性干涉(訊號強度抵消),因此,更多無線訊號強度從微帶線133朝上輻射。此外,天線140、波導槽131a及微帶線133彼此重疊,以更提升天線140的增益。
請參照第1C圖,其繪示第1A圖之底視圖。銲球150形成於電路部130(繪示於第1A圖)且環繞晶片120。半導體結構100透過銲球150電性連接於一印刷電路板(printed circuit board,PCB)。銲球150突出於晶片120的下表面,因此,可確保半導體結構100與印刷電路板電性連接。此外,波導槽131a環繞晶片120,但未與晶片120重疊,使晶片120可重疊於接地層131(斜線區域)之屏蔽部1311(不包括波導槽131a)且可降低電磁干擾。
請參照第2圖,其繪示第1A圖中天線的X-Z平面的場形
圖。由於波導槽131a及微帶線133排列成陣列形式,故天線140的介電性係優良且-Z方向的增益可達10dBi。
請參照第3圖,其繪示第1A圖中天線的反射損失(return loss)示意圖。因為二耦合共振,故天線140的頻寬(反射損失在-10dBi以下)介於例如是56GHz與64GHz之間。
請參照第4圖,其繪示依照本發明另一實施例之半導體結構200的剖視圖。半導體結構200包括基板110、晶片120、電路部130、數個天線140、天線介電層145及數個銲球150。
電路部130包括接地層131、第一介電層132及微帶線133。接地層131包括屏蔽部1311及單個波導槽131a覆蓋微帶線133。第一介電層132與接地層131重疊,使微帶線133透過第一介電層132與波導槽131a隔離。晶片120設於電路部130上且透過數個銲球121電性連接於電路部130。晶片120與接地層131之屏蔽部1311(不具波導槽131a的完整部分)重疊,以達到電磁干擾防護作用。
綜上所述,雖然本發明已以較佳實施例揭露如上,然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作各種之更動與潤飾。因此,本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100‧‧‧半導體結構
110‧‧‧基板
110b‧‧‧第一表面
110s、130s、131s‧‧‧外側面
110u‧‧‧第二表面
120‧‧‧晶片
121‧‧‧銲球
125‧‧‧底膠
130‧‧‧電路部
131‧‧‧接地層
1311‧‧‧屏蔽部
131a‧‧‧波導槽
132‧‧‧第一介電層
133‧‧‧微帶線
134‧‧‧第二介電層
135‧‧‧相位位移器
136‧‧‧圖案化導電層
137‧‧‧饋入電路
138‧‧‧導通孔
140‧‧‧天線
145‧‧‧天線介電層
150、150g‧‧‧銲球
Claims (13)
- 一種半導體結構,包括:一基板,具有相對之一第一表面及一第二表面;一電路部,形成於該基板之該第一表面上且包括一波導槽及一微帶線,該微帶線與該波導槽重疊;一晶片,設於該電路部上,其中該微帶線位於該電路部且位於該晶片之一覆蓋區之外;以及一天線,形成於該基板之該第二表面且與該波導槽重疊。
- 如申請專利範圍第1項所述之半導體結構,其中該電路部包括一接地層,該接地層覆蓋該晶片。
- 如申請專利範圍第2項所述之半導體結構,其中該波導槽形成於該接地層。
- 如申請專利範圍第1項所述之半導體結構,其中該電路部具有複數個該波導槽,該些波導槽未與該晶片重疊。
- 如申請專利範圍第1項所述之半導體結構,其中該微帶線的延伸方向實質上垂直於該波導槽的延伸方向。
- 如申請專利範圍第1項所述之半導體結構,其中該天線與該波導槽重疊。
- 如申請專利範圍第1項所述之半導體結構,更包括:一天線介電層,形成於該基板之該第二表面且覆蓋該天線。
- 一種半導體結構,包括:一基板,具有相對之一第一表面及一第二表面;一整合被動元件層,形成於該基板之該第一表面且包括複數個波導槽及複數個微帶線,該些微帶線重疊於該些波導槽,其中該些波導槽及該些微帶線排列成陣列型; 一晶片,設於該整合被動元件層上,其中該微帶線位於該整合被動元件層且位於該晶片之一覆蓋區之外;以及複數個天線,形成於該基板之該第二表面且與該些波導槽重疊。
- 如申請專利範圍第8項所述之半導體結構,其中該整合被動元件層包括一接地層,該接地層覆蓋該晶片。
- 如申請專利範圍第8項所述之半導體結構,其中各該微帶線的延伸方向實質上垂直於對應之該波導槽的延伸方向。
- 如申請專利範圍第8項所述之半導體結構,其中該些天線與該些波導槽重疊。
- 如申請專利範圍第8項所述之半導體結構,其中該基板由玻璃製成。
- 如申請專利範圍第8項所述之半導體結構,其中該整合被動元件層包括:一第一介電層,形成於該接地層與該些微帶線之間。
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