TWI552269B - 操作為空間變換器之設備、具有空間變換器之設備及用於半導體封裝之方法 - Google Patents

操作為空間變換器之設備、具有空間變換器之設備及用於半導體封裝之方法 Download PDF

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TWI552269B
TWI552269B TW104103468A TW104103468A TWI552269B TW I552269 B TWI552269 B TW I552269B TW 104103468 A TW104103468 A TW 104103468A TW 104103468 A TW104103468 A TW 104103468A TW I552269 B TWI552269 B TW I552269B
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semiconductor substrate
contact pattern
electrical contact
layer
pitch
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TW104103468A
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TW201543615A (zh
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亞歷山大 亞歷克索夫
喬安娜Ｍ 史旺
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英特爾公司
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/206—Length ranges
    • H01L2924/2064—Length ranges larger or equal to 1 micron less than 100 microns

Description

操作為空間變換器之設備、具有空間變換器之設備及用於半導體封裝 之方法
本發明係有關於晶粒封裝技術。
系統晶片(需要較多I/O個數)的繁增，單位矽面積的增加製程成本以及致能電腦連續統之小形狀因數晶片的需要要求較細的間距及較小封裝件。同時，行動及無處不在的環節要求低成本的解決辦法。較細凸塊間距一般要求昂貴的封裝件，因為FLS加工同時提供互連件及封裝跡線的電遷移能力及可靠性。替代昂貴的封裝技術是使用中介層(interposer，例如，矽或玻璃中介層)用於細小間距扇出於較粗的間距及LS，以及使用直通矽穿孔(TSV)於封裝件或寬互連件。不過，TSV傾向大幅增加成本，限制或減低功率處理及訊號完整性而且增加厚度。
依據本發明之一實施例，係特地提出一種設備，其包含：一平面半導體基板，其包含多個裝置以及形成於該半導體基板之第一表面上的一第一電接點圖案；以及多個導電材料層，其係於該半導體基板之第一表面上於介電 材料之間交替，該等多個導電材料層包含一接線層，該接線層包含一第二電接點圖案，其中該半導體基板之第二表面包含至該第一電接點圖案的數個開孔。
100‧‧‧總成
110‧‧‧空間變換器
120‧‧‧半導體基板
125‧‧‧裝置面
130‧‧‧背面
132‧‧‧阻障層
134‧‧‧介電層
135‧‧‧主動裝置或電路區
137‧‧‧開孔
140‧‧‧接點圖案
145‧‧‧增層部份
153‧‧‧傳導穿孔
154‧‧‧傳導穿孔
155‧‧‧接點
157至159‧‧‧導電材料層
161至164‧‧‧介電層
180‧‧‧晶粒
182‧‧‧接點
185‧‧‧焊點
190‧‧‧焊球
193‧‧‧基板
195‧‧‧製模材料
200‧‧‧總成
210‧‧‧空間變換器
220‧‧‧半導體基板
225‧‧‧裝置面
230‧‧‧背面
235‧‧‧主動裝置/電路區
237‧‧‧開孔
240‧‧‧接點
245‧‧‧增層
253、254‧‧‧傳導穿孔
255‧‧‧電接點
280‧‧‧晶粒
290‧‧‧焊球
293‧‧‧基板
295‧‧‧製模材料
300‧‧‧總成
310‧‧‧空間變換器
320‧‧‧半導體基板
325‧‧‧裝置面
330‧‧‧背面
335‧‧‧主動裝置/電路區
337‧‧‧開孔
340‧‧‧接點圖案
345‧‧‧增層
355‧‧‧接點
381A、381B、382A、382B、382C、383A、383B、383C、383D‧‧‧晶粒
395‧‧‧製模化合物
420‧‧‧基板
435‧‧‧主動裝置/電路區
440‧‧‧接觸墊
445‧‧‧增層
453‧‧‧傳導穿孔
455‧‧‧裝置/電路區
480‧‧‧晶粒
495‧‧‧造模材料
505‧‧‧遮罩層
510‧‧‧開孔
515‧‧‧阻障層
520‧‧‧焊點
600‧‧‧計算裝置
602‧‧‧板子
604‧‧‧處理器
606‧‧‧通訊晶片
圖1的側視圖圖示包含空間變換器的一總成具體實施例。
圖2的剖面側視圖圖示包含空間變換器的另一總成具體實施例。
圖3的側視圖圖示包含空間變換器及多晶片封裝總成的另一總成具體實施例。
圖4為圖3之結構的上視圖且圖示各自為I/O晶片/模組、繪圖晶片/模組、及邏輯(核心)晶片/模組的晶粒。
圖5圖示根據一實作的計算裝置。
圖6圖示圖5結構加上增層之後的結構。
圖7圖示減薄半導體基板的圖6結構。
圖8圖示圖7結構加上造模材料之後的結構。
圖9圖示在蝕刻穿過半導體基板至接觸墊之開孔或空腔之後的圖8結構。
圖10圖示在半導體基板背面加上視需要阻障層之後的圖9結構。
圖11圖示在形成穿過阻障層材料至接觸墊之開孔之後的圖10結構。
圖12圖示在加入至接觸墊之焊點之後的圖11結構。
圖13圖示根據一實作的計算裝置。
揭示一種設備。在一具體實施例中，設備可當作空間變換器操作以及含有平面半導體基板，其包括多個裝置形成於半導體基板的裝置面中及/或上，以及也形成第一電接點圖案於該半導體基板的裝置面上。在該半導體基板的裝置面上，該設備也包括交替於介電材料之間的多個導電材料層。該等多個導電材料層包括包含第二電接點圖案的一接線層(wiring layer)。該半導體基板的背面包括數個開孔穿過該基板至該第一電接點圖案。在一具體實施例中，作為空間變換器的一晶粒或晶粒例如通過焊點(solder connection)連接至該第一電接點圖案及該第二電接點圖案中之一者。該第一電接點圖案及該第二電接點圖案中之另一者例如通過焊點可連接至一基板，例如封裝基板或印刷電路板。也揭示形成空間變換器與包含封裝件之晶粒的方法。
圖1的側視圖包含空間變換器的一總成具體實施例。請參考圖1，總成100包括含有半導體基板120的空間變換器110。半導體基板120包括裝置面125與在裝置面125反面的背面130。裝置面125包括主動裝置或電路區135含有例如數個組件，例如針對任務定做的電晶體及互連件，例如高速輸入/輸出(I/O)、射頻(RF)及/或電力輸送，或用於晶粒對晶粒生產率的中繼器(repeater)。裝置面125也包括互連堆疊含有至少一佈線層(routing layer，或扇出金屬層)，穿孔層(via layer)及在半導體基板120之一表面上的接點圖 案140。
連接至半導體基板120之裝置面125上的是，在一具體實施例中，由交替於介電材料之間的多個導電材料層組成的增層部份(build-up portion)145。圖1圖示導電材料層含有導電材料層157、導電材料層158及導電材料層159。增層部份145之一表面包括一接點圖案連接至導電材料層157、導電材料層158及導電材料層159中之一或更多者以及通過數個傳導穿孔(conductive via)連接至接點140。圖1圖示在導電材料層159、接點155之間的代表傳導穿孔154。主動裝置/電路區135及裝置/電路最終用傳導穿孔(例如，傳導穿孔154)和導電材料層(金屬層)157至159中之一或更多連接至晶粒180。至晶粒180的該等接點及穿孔中也可有一部份穿過與圖示於增層部份145之導電材料層不同的導電材料層(或數個)。圖1示意圖示在主動裝置/電路區135及此類其他導電材料層(或數個)之間的傳導穿孔153。在一具體實施例中，例如，導電材料層157至159各自為導電材料，同時傳導穿孔可為銅、鎢、金或適合例如直接接觸半導體元件的其他金屬。圖1的結構100中，設置於接點155、導電材料層、半導體基板120之間的是介電材料層(分別為介電層161、介電層162、介電層163及介電層164)。
圖1圖示半導體基板120有從背面130穿過基板厚度到接點140的數個開孔137。圖1圖示穿過開孔137到接點140的焊球190。該等焊點(焊球190)可操作以使總 成100連接至基板193的接點，例如封裝基板或印刷電路板。圖1也圖示在空間變換器110之反面上連接至晶粒180(例如，微處理器或其他晶粒)的接點155。在一具體實施例中，晶粒180至接點155的連接係通過焊點185。如圖示，接點155有與晶粒180之接點182類似的間距。空間變換器110的接點140有間距與基板193的間距對應。在一具體實施例中，接點140的間距大於接點155的間距(接點155的間距小於接點140的間距)。包圍空間變換器110上之晶粒180的是例如由有機電介質組成的製模材料195。
請參考空間變換器110的半導體基板120，在一具體實施例中，基板120或基板120的裝置層或數層為單晶矽、矽-鍺或窄帶隙半導體材料，例如砷化銦(InAs)或銦銻(InSb)(其帶隙比較小於矽的帶隙)。主動裝置/電路區135可包含積體電路允許供應一些或所有必要I/O功能給晶粒180、RF/無線電功能、電力輸送及中繼器或晶粒對晶粒通訊。主動裝置/電路區135中的裝置及電路不必與例如晶粒180(例如，邏輯晶粒)在同一個製程中製造。因此，可定做該等裝置層及尺寸以配合特定的功能需要。例如，主動裝置/電路區135中的功率電晶體可具有與習知邏輯製程不相容的特定閘極電介質厚度。再者，可增加電力輸送所需的額外電容。在另一實施例中，RF電晶體可具有尺寸及結構(例如，多重指狀閘極(multi-gate-finger)場效電晶體)經定做成對於預期RF頻率及功能有最佳特性。
在一具體實施例中，在半導體基板120由矽或矽-鍺製成的情形下，半導體基板的裝置面125包括由例如氮化鉭(TaN)及/或介電層134(例如，二氧化矽)製成的阻障層132。在一方面，加上有一厚度的阻障層132及/或介電層134(例如，經由化學氣相沉積)以抑制金屬(例如，銅)由接點140擴散到半導體材料和凸塊對凸塊的電絕緣體中。在其中半導體基板為無法得到絕緣或半絕緣之窄帶隙半導體(例如，一些III-V族材料，例如InAs及InSB)的實施例中，可省略阻障層132以及在基板上可以只形成介電層134。
圖2的剖面側視圖圖示包含空間變換器的另一總成具體實施例。總成200包括含有半導體基板220的空間變換器210，半導體基板220有裝置面225及背面230。裝置面225包括主動裝置/電路區235及接點240。連接至半導體基板之裝置面225的是交替於介電材料層之間的多個導電材料層的增層(build-up layer)245。該等多個導電材料層包括接線層，其包括在增層245之一表面(空間變換器210中與半導體基板220相反的表面)上的電接點255圖案。主動裝置/電路區235及與半導體基板220關連的裝置最終用傳導穿孔(例如，在接點255與增層245中之一層導電材料之間的傳導穿孔254)連接至晶粒180。至晶粒280的該等接點及穿孔中也可有一部份穿過與圖示於增層245之導電材料層不同的導電材料層(或數個)。圖2示意圖示在主動裝置/電路區235及此類其他導電材料層(或數個)之間的傳導穿孔253。
圖2圖示穿過半導體基板220至接點240的數個開孔237。該等焊點(焊球290)設置於至接點240的開孔237中。該等焊點可操作以使空間變換器210連接至基板293，例如封裝基板或印刷電路板。接點255可操作以使空間變換器210例如通過焊點連接至晶粒(微處理器晶粒)或晶粒，例如晶粒280。如圖2所示，接點255有小於接點240的間距。圖2圖示設置於空間變換器210上包圍晶粒280的製模材料295。
圖2圖示一具體實施例，其中半導體基板220或半導體基板220之裝置層(或數個)為寬帶隙半導體材料，例如氮化鎵或其他III-V族氮化物材料，或窄帶隙材料例如可藉由適當摻雜做成半絕緣體，或絕緣體，例如砷化鎵、砷化鋁或磷化鎵。由於這些半導體材料在寬帶隙材料的情形下絕緣或完全絕緣，因此如圖2所示，可能不需要半導體基板上的阻障及/或絕緣層。
圖3的側視圖圖示包含空間變換器及多晶片封裝總成的另一總成具體實施例。總成300包括空間變換器310，其含有半導體基板320及設置於半導體基板320之裝置面上的增層345。半導體基板320包括含有主動裝置區335及接點圖案340的裝置面325和背面330。做成穿過半導體基板320至接點340的數個開孔337。由數個導電材料、介電材料之交替層組成的增層345設置於半導體基板320的裝置面325上。增層345的反面含有接點355。接點340可操作以使空間變換器310連接至基板，例如封裝基板或 印刷電路板。在此具體實施例中，接點355可操作以使空間變換器310連接至多個晶粒。圖3圖示各自例如通過焊點連接至接點355的晶粒381A、382A及383A。晶粒381A例如為I/O晶片/模組；晶粒382A例如為繪圖晶片/模組；以及晶粒383A例如為邏輯(核心)晶片/模組。該等個別晶片嵌入由例如有機材料組成的製模化合物395。圖4的上視圖圖示圖3的結構以及圖示晶粒381A及381B各為例如I/O晶片/模組；晶粒382A、382B及382C各為例如繪圖晶片/模組；以及晶粒383A、383B、383C及383D各為邏輯(核心)晶片/模組。
圖3及圖4圖示一具體實施例，在此可與空間變換器中之主動電路無關地實現後期連結(late binding)。在一具體實施例中，空間變換器310的主動裝置/電路區335可提供額外機能，例如電力輸送、RF電路、無線電給裝在空間變換器上的各個晶粒。
圖5至圖12用於組裝如圖1所示之結構的方法實施例。圖5圖示半導體基板(例如，晶圓)之一部份。基板420例如為矽晶圓。在基板420的裝置面上，積體電路裝置及電路根據半導體加工技術形成於主動裝置/電路區435中。該等裝置及電路(例如，互連件)可延伸超出基板的表面。例如，閘極及接面區(源極區/漏極區)敷金屬(metallization)可形成於基板表面中。半導體基板裝置面上的附加敷金屬可包括一互連堆疊含有至少一佈線層及與主動裝置/電路區435關連的導穿孔層。基板420上的另一互連件包括至少一 佈線層及數個關連傳導穿孔用於包含接觸墊440圖案的墊層(pad layer)。
在形成主動裝置/電路區435或接觸墊440於基板420中或上之前，基板可加上替代半導體材料。例如，在想要基板裝置層具有與矽不同的帶隙時，例如可用漸變方式(graded fashion)加入此類替代材料(例如，鍺，III-V族半導體等等)。
圖6圖示在結構加上增層之後的圖5結構。具體言之，圖6的增層在半導體基板420裝置面上包含交替於介電材料之間的導電材料層。在一具體實施例中，此類增層係根據半導體製造技術形成。有代表性的適當介電材料包括化學氣相沉積(CVD)沉積的二氧化矽(SiO2)，氮化矽(Si3N4)以及電介質常數小於SiO2(低k介電材料)的介電材料。代表性的導電材料及傳導穿孔材料為用雙重或單一鑲嵌製程(damascene process)沉積的銅材料。儘管揭示用於傳導穿孔材料的銅料導電材料，然而應瞭解此類穿孔材料，特別是與裝置/電路區455中之裝置接觸的穿孔材料，可為例如通過單一鑲嵌製程加入的另一種材料，例如鈦、鎳、金或鎢。導電材料在增層445中的層數可按需要改變。上等導電材料層包括其間距對應至晶粒之接點間距的接觸墊455圖案。圖6圖示例如通過焊點連接至接觸墊455的晶粒480。圖6也圖示在主動裝置/電路區435與增層445之導電材料層之間的數個傳導穿孔453。
圖7圖示在半導體基板420減薄之後的圖6結構。 在一具體實施例中，基板420的減薄，例如，透過機械研磨製程，可藉由研磨基板減到合適厚度。基板420的一代表性厚度是25皮米或更小。其他的技術有化學機械研磨、濕蝕刻及電漿乾化學蝕刻法。
圖8圖示在結構加上造模材料之後的圖7結構。具體言之，圖8圖示在增層445之表面上及包圍晶粒480由例如有機聚合物組成的造模材料495。圖8也圖示在對應至接觸墊440之區域中形成穿過半導體基板420之數個開孔510之後的結構。具體言之，圖8圖示由例如光阻劑組成的遮罩層505，其具有通到與在半導體基板420反面上之接觸墊440位置對應之區域的數個開孔510。
圖9圖示在蝕刻穿過半導體基板420至接觸墊440的開孔或空腔之後的圖8結構。在一具體實施例中，由例如矽組成的半導體基板可用反應性離子蝕刻法蝕刻以形成該等空腔。圖9也圖示遮罩層移除之後的結構。
圖10圖示在半導體基板背面加上視需要阻障層之後的圖9結構。圖10圖示沉積於半導體基板背面上面作為毯覆層(blanket)的阻障層515。在一具體實施例中，阻障層515的適當材料為氮化鉭(TaN)。沉積技術之一為化學氣相沉積，另一為原子層沉積。
圖11圖示在形成穿過阻障層515材料至接觸墊440之開孔之後的圖10結構。在一具體實施例中，形成該等開孔的製程包括：有通到在接觸墊上方之區域之數個開孔的阻障層加上遮罩材料，接著用反應性穿孔蝕刻(reactive via etch)穿過該阻障材料至該等接觸墊，且隨後移除該遮罩材料。在一具體實施例中，在圖案化該阻障層及移除該遮罩層之後，基板上可共形地加上作為毯覆層的介電層以及與阻障層類似地加以圖案化。
圖12圖示在加入至接觸墊之焊點之後的圖11結構。圖12圖示由加至接觸墊440之例如錫基焊料組成的焊點520。在加上焊點後，可從例如形成於基板基底上的其他結構切下該結構(例如，從晶圓切下)。在加上焊點520後，該結構可連接至基板，例如封裝基板。
圖13圖示根據一實作的計算裝置600。計算裝置600容納板子602。板子602可包含許多組件，包括但不限於：處理器604以及至少一通訊晶片606。處理器604實體及電氣耦合至板子602。在一些實作中，至少一通訊晶片606也實體及電氣耦合至板子602。在其他實作中，通訊晶片606為處理器604之一部份。
取決於它的應用，計算裝置600可包含可能或不實體及電氣耦合至板子602的其他組件。這些其他組件包括但不限於：揮發性記憶體(例如，DRAM)，非揮發性記憶體(例如，ROM)，快閃記憶體，繪圖處理器，數位訊號處理器，加解密處理器(crypto processor)，晶片組，天線，顯示器，觸控螢幕顯示器，觸控螢幕控制器，電池，聲頻編碼解碼器，視頻編碼解碼器，功率放大器，全球定位系統(GPS)裝置，羅盤，加速計，陀螺儀，揚聲器，相機、以及大量儲存裝置(例如，硬碟驅動器，光碟(CD)，數位光碟 (DVD)等等)。
通訊晶片606致能進出計算裝置600之資料傳輸的無線通訊。用語「無線」及其衍生詞可用來描述通過非固體媒介可利用調變電磁輻射來傳達資料的電路、裝置、系統、方法、技術、通訊通道等等。該用語不意謂相關裝置不包含任何配線，然而在一些具體實施例中，它們可能沒有。通訊晶片606可實現許多無線標準或協定中之任一，包括但不限於：Wi-Fi(IEEE 802.11家族)，WiMAX(IEEE 802.16家族)，IEEE 802.20，長程演進技術(LTE)，Ev-DO，HSPA+，HSDPA+，HSUPA+，EDGE，GSM，GPRS，CDMA，TDMA，DECT，藍芽，彼等之衍生物，以及指定作為3G、4G、5G及以上的任何其他無線協定。計算裝置600可包含多個通訊晶片606。例如，第一通訊晶片606可專用於較短程的無線通訊，例如Wi-Fi及藍芽，以及第二通訊晶片606可專用於較長程的無線通訊，例如GPS，EDGE，GPRS，CDMA，WiMAX，LTE，Ev-DO及其他。
計算裝置600的處理器604包括封裝於處理器604內的積體電路晶粒。在一些實作中，該封裝件包括連接至空間變換器的積體電路晶粒，在此該空間變換器有如上文所述之主動裝置/電路區。用語「處理器」可指任何裝置或裝置之一部份用以處理來自暫存器及/或記憶體的電子資料以將該電子資料轉換成可存入暫存器及/或記憶體的其他電子資料。
通訊晶片606也包括封裝於通訊晶片606內的積 體電路晶粒。根據另一實作，該封裝件包括連接至空間變換器的積體電路晶粒，在此該空間變換器如上文所述之主動裝置/電路區。
在不同實作中，計算裝置600可為膝上電腦，連網電腦(netbook)，筆記型電腦，超輕薄筆電(ultrabook)，智慧型手機，平板電腦，個人數位助理(PDA)，迷你行動型個人電腦(ultra mobile PC)，行動電話，桌上電腦，伺服器，列表機，掃描器，監視器，機上盒，娛樂控制單元，數位相機，可攜式音樂播放器，或數位錄影機。在其他實作中，計算裝置600可為處理資料的任何其他電子裝置。
實施例
實施例1為一種設備，其係包括：一平面半導體基板含有多個裝置以及形成於該半導體基板之第一表面上的一第一電接點圖案；以及在該半導體基板之第一表面上交替於介電材料之間的多個導電材料層，該等多個導電材料層包括包含一第二電接點圖案的一接線層，其中該半導體基板的第二表面包括至該第一電接點圖案的數個開孔。
在實施例2，實施例1之設備中的第一電接點圖案包括第一間距，以及第二多個接點包括第二間距，以及該第一間距大於第二間距。
在實施例3，實施例1之設備中的該等多個裝置可操作以完成與下列中之至少一者有關的一任務：高速輸入/輸出、射頻、或電力輸送。
在實施例4，實施例1之設備中的該半導體基板 的厚度包括約25微米以下。
在實施例5，實施例1之設備更包括設置於該半導體基板之第二表面上的一擴散阻障層與一絕緣層中之至少一者。
在實施例6，實施例1之設備中的該半導體基板包括含有矽的一窄帶隙半導體材料。
在實施例7，實施例1之設備中的該半導體基板包括一寬帶隙半導體材料。
在實施例8，實施例1之設備更包括耦合至該第一電接點圖案與該第二電接點圖案中之一者的一晶粒。
實施例9為一種設備，其係包括：包含一半導體基板的一空間變換器，該半導體基板包含在該半導體基板之第一面上的多個裝置及一第一電接點圖案，以及在該半導體基板之第一面上交替於介電材料之間的多個導電材料層，該等多個導電材料層包括包含一第二電接點圖案的一第一接線層；以及裝在該半導體基板之該第一面及該第二面中之一者上的至少一積體電路晶片。
在實施例10，實施例9之設備中的該半導體基板之第二面包括至該第一電接點圖案的數個開孔。
在實施例11，實施例9之設備中的第一電接點圖案包括一第一間距，以及該第二接點圖案包括一第二間距，以及該第一間距大於第二間距。
在實施例12，實施例9之設備中的該等多個裝置可操作以完成與下列中之至少一者有關的一任務：高速 輸入/輸出、射頻、或電力輸送。
在實施例13，實施例9之設備的該半導體基板的厚度包括約25微米以下。
在實施例14，實施例9之設備更包括設置於該半導體基板之第二表面上的一擴散阻障層與一絕緣層中之至少一者。
在實施例15，實施例9之設備中的該半導體基板包括含有矽的一窄帶隙半導體材料。
在實施例16，實施例9之設備中的該半導體基板包括一寬帶隙半導體材料。
在實施例17，實施例9之設備更包括耦合至該半導體基板之該第一面及該第二面中之另一者的一封裝基板。
實施例18為一種方法，其係包括：形成數個開孔穿過一空間變換器的一半導體基板至該半導體基板上的一第一電接點圖案，該空間變換器包括在該半導體基板上的一互連堆疊，該互連堆疊包含至少一佈線層與包含一第二電接點圖案的一墊層；以及使一積體電路晶片耦合至該第一電接點圖案及該第二電接點圖案中之一者。
在實施例19，實施例18的方法更包括在該半導體基板上形成一阻障層。
在實施例20，實施例18的方法更包括在該第一電接點圖案上形成數個銲錫凸塊。
在實施例21，實施例20的方法更包括使該等銲 錫凸塊耦合至一封裝件的數個接點。
在以上說明中，為了便於解釋，提出許多特定細節供讀者徹底瞭解該等具體實施例。不過，熟諳此藝者應刃而解，在沒有該等特定細節中之一些下仍可實施一或更多其他具體實施例。所述特定具體實施例並非用來限制本發明而是圖解說明。本發明的範疇不取決於以上所提供的特定實施例而只受限於下列請求項。在其他情況下，眾所周知的結構、裝置及操作用方塊圖的形式圖示或沒有細節以免混淆本說明的理解。在認為適當的情形下，元件符號或元件符號的尾部重覆用於諸圖以表示對應或類似的元件，視需要它們可具有類似的特性。
也應瞭解，例如，本專利說明書通篇提及之「一具體實施例」、「具體實施例」、「一或多個具體實施例」、「不同具體實施例」意指在實施本發明時可包括特定特徵。同樣，應瞭解，在本說明中，為了使本揭示內容流暢和協助理解本發明的不同方面，不同特徵有時群聚於單一實施例、圖、或彼等之說明。然而，這種揭示方法不應被解譯成要反映本發明需要比明示於各個請求項之中者還多的特徵。反而，如下列請求項反映，本發明方面可少於單一所揭露之實施例的所有特徵。因此，在本【實施方式】之後的申請專利範圍在此明確併入本【實施方式】，而且各個請求項本身足以作為本發明的個別實施例。
100‧‧‧總成
110‧‧‧空間變換器
120‧‧‧半導體基板
125‧‧‧裝置面
130‧‧‧背面
132‧‧‧阻障層
134‧‧‧介電層
135‧‧‧主動裝置或電路區
137‧‧‧開孔
140‧‧‧接點圖案
145‧‧‧增層部份
153‧‧‧傳導穿孔
154‧‧‧傳導穿孔
155‧‧‧接點
157至159‧‧‧導電材料層
161至164‧‧‧介電層
180‧‧‧晶粒
182‧‧‧接點
185‧‧‧焊點
190‧‧‧焊球
193‧‧‧基板
195‧‧‧製模材料

Claims (22)

  1. 一種操作為空間變換器之設備，其包含：一平面半導體基板，其包含多個裝置以及形成於該半導體基板之第一表面上的一第一電接點圖案；以及多個導電材料層，其係於該半導體基板之第一表面上於介電材料之間交替，該等多個導電材料層包含一接線層，該接線層包含一第二電接點圖案，其中該半導體基板之一第二表面包含至該第一電接點圖案的數個開孔。
  2. 如請求項1所述之設備，其中該第一電接點圖案包含一第一間距，該等第二多個接點包含一第二間距，且該第一間距大於該第二間距。
  3. 如請求項1所述之設備，其中該等多個裝置可操作以執行與高速輸入/輸出、射頻、或電力輸送其中至少一者有關的一任務。
  4. 如請求項1所述之設備，其中該半導體基板的厚度包含小於約25微米。
  5. 如請求項1所述之設備，其更包含設置於該半導體基板之第二表面上的一擴散阻障層與一絕緣層之中的至少一者。
  6. 如請求項1所述之設備，其中該半導體基板包含一包括矽的窄帶隙半導體材料。
  7. 如請求項1所述之設備，其中該半導體基板包含一寬帶 隙半導體材料。
  8. 如請求項1所述之設備，其更包含耦合至該第一電接點圖案與該第二電接點圖案其中一者的一晶粒。
  9. 一種具有空間變換器之設備，其包含：包含一半導體基板的一空間變換器，該半導體基板於其之一第一面上包含：多個裝置，一第一電接點圖案，以及交替於介電材料之間的多個導電材料層，該等多個導電材料層包含一接線層，該接線層包含一第二電接點圖案；以及安裝在該半導體基板之該第一面與一第二面中之一者上的至少一積體電路晶片。
  10. 如請求項9所述之設備，其中該半導體基板的該第二面包含至該第一電接點圖案的數個開孔。
  11. 如請求項9所述之設備，其中該第一電接點圖案包含一第一間距，該第二接點圖案包含一第二間距，且該第一間距大於該第二間距。
  12. 如請求項9所述之設備，其中該等多個裝置可操作以執行與高速輸入/輸出、射頻、或電力輸送其中至少一者有關的一任務。
  13. 如請求項9所述之設備，其中該半導體基板的厚度包含小於約25微米。
  14. 如請求項9所述之設備，其更包含設置於該半導體基板 之第二表面上的一擴散阻障層與一絕緣層中之至少一者。
  15. 如請求項9所述之設備，其中該半導體基板包含一包括矽的窄帶隙半導體材料。
  16. 如請求項9所述之設備，其中該半導體基板包含一寬帶隙半導體材料。
  17. 如請求項9所述之設備，其更包含耦合至該半導體基板之該第一面及該第二面中之另一者的一封裝基板。
  18. 一種用於半導體封裝之方法，其包含：形成包含一半導體基板的一空間變換器，該半導體基板在一裝置面上包含一裝置區、一第一電接點圖案、以及至少一佈線層與包含一第二電接點圖案的一墊層；以及在該半導體基板上形成穿過該空間變換器至該第一電接點圖案的數個開孔。
  19. 如請求項18所述之方法，其更包含在該半導體基板上形成一阻障層。
  20. 如請求項18所述之方法，其更包含在該第一電接點圖案上形成數個銲錫凸塊。
  21. 如請求項20所述之方法，其更包含使該等銲錫凸塊耦合至一封裝件的數個接點。
  22. 如請求項18所述之方法，其更包含使一積體電路晶片耦合至該第一電接點圖案及該第二電接點圖案中之一者。
TW104103468A 2014-03-28 2015-02-02 操作為空間變換器之設備、具有空間變換器之設備及用於半導體封裝之方法 TWI552269B (zh)

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