TWI546924B - 用以製造包含具有開口之覆蓋層之電子裝置之方法及相關裝置 - Google Patents

用以製造包含具有開口之覆蓋層之電子裝置之方法及相關裝置 Download PDF

Info

Publication number
TWI546924B
TWI546924B TW103121266A TW103121266A TWI546924B TW I546924 B TWI546924 B TW I546924B TW 103121266 A TW103121266 A TW 103121266A TW 103121266 A TW103121266 A TW 103121266A TW I546924 B TWI546924 B TW I546924B
Authority
TW
Taiwan
Prior art keywords
forming
cover layer
openings
lcp
substrate
Prior art date
Application number
TW103121266A
Other languages
English (en)
Other versions
TW201513287A (zh
Inventor
路易斯 喬瑟夫 二世 倫狄克
凱賽 菲利浦 羅迪古茲
崔維斯Ｌ 克拜
麥克 雷蒙 維斯朋
Original Assignee
賀利實公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 賀利實公司 filed Critical 賀利實公司
Publication of TW201513287A publication Critical patent/TW201513287A/zh
Application granted granted Critical
Publication of TWI546924B publication Critical patent/TWI546924B/zh

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0313—Organic insulating material
    • H05K1/032—Organic insulating material consisting of one material
    • H05K1/0346—Organic insulating material consisting of one material containing N
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/09—Use of materials for the conductive, e.g. metallic pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H05K3/285—Permanent coating compositions
    • H05K3/287—Photosensitive compositions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13199—Material of the matrix
    • H01L2224/1329—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13199—Material of the matrix
    • H01L2224/13294—Material of the matrix with a principal constituent of the material being a liquid not provided for in groups H01L2224/132 - H01L2224/13291
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13298—Fillers
    • H01L2224/13299—Base material
    • H01L2224/133—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/2901—Shape
    • H01L2224/29011—Shape comprising apertures or cavities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7525—Means for applying energy, e.g. heating means
    • H01L2224/75251—Means for applying energy, e.g. heating means in the lower part of the bonding apparatus, e.g. in the apparatus chuck
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7525—Means for applying energy, e.g. heating means
    • H01L2224/75252—Means for applying energy, e.g. heating means in the upper part of the bonding apparatus, e.g. in the bonding head
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/8185—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/81855—Hardening the adhesive by curing, i.e. thermosetting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/832—Applying energy for connecting
    • H01L2224/83201—Compression bonding
    • H01L2224/83203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/832—Applying energy for connecting
    • H01L2224/83201—Compression bonding
    • H01L2224/83203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H01L2224/83204—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding with a graded temperature profile
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8334—Bonding interfaces of the layer connector
    • H01L2224/83359—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/8388—Hardening the adhesive by cooling, e.g. for thermoplastics or hot-melt adhesives
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9211—Parallel connecting processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985—Flexible insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49894—Materials of the insulating layers or coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/38—Effects and problems related to the device integration
    • H01L2924/381—Pitch distance
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0137—Materials
    • H05K2201/0141—Liquid crystal polymer [LCP]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10098—Components for radio transmission, e.g. radio frequency identification [RFID] tag, printed or non-printed antennas
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10151—Sensor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10166—Transistor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10212—Programmable component
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3452—Solder masks
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457—Solder materials or compositions; Methods of application thereof
    • H05K3/3485—Applying solder paste, slurry or powder

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Description

用以製造包含具有開口之覆蓋層之電子裝置之方法及相關裝置
本發明係關於電子裝置之場，且更特定而言，係關於電子裝置之液晶聚合物封裝及相關方法。
隨著半導體及積體電路(IC)技術得以進展，一直存在朝向具有眾多輸入及輸出(IO)接腳之高功能性IC組件之一趨勢連同對經減小晶片大小、重量及電力消耗之一需求。因此，隨著(IO)密度增加，接腳大小及接腳之間的間隔必須減小。
為匹配此等IC之接腳間隔，存在對因而將具有小的緊密配置之焊料墊之印刷電路板之一需求。然而，IC接腳之間的間隔之減小當前正以大於印刷電路板上之對應焊料墊之一速率發生。因此，可存在用於某些現代裝置之一互連技術間隙。
為使此等裝置發揮作用，印刷電路板可具有額外繞線層以處置IC之接腳，或利用扇出封裝。此導致IC之封裝大小大於IC自身，從而可限制系統微型化。除對微型化裝置之期望之外，在某些情形中亦期望由一撓性而非剛性基板構造此等裝置。
由其構造薄且撓性印刷電路板之現在用作一基板之一種材料係液晶聚合物(LCP)。LCP中之分子具有剛性、棒狀形狀，且在呈一液相時或在經加熱及熔化時維持一結晶規則。T.Zhang、W.Johnson、 B.Farrell及M.St.Lawrence在其論文「The processing and assembly of liquid crystalline polymer printed circuits」(關於微電子學之2002年國際討論會，2002年)中揭示使用LCP作為一基板構造一印刷電路板。一光阻劑首先施加至一包銅壓層、經曝露且經顯影以界定一所要電路圖案。然後藉由將經曝露銅蝕刻掉而界定實際電路。經由機械鑽孔在基板中形成孔或導通孔。然後執行一除污步驟以自該等導通孔或孔移除碎屑，藉此使LCP材料準備用於金屬沈積。接下來執行一金屬化步驟，且將一典型焊料遮罩施加至LCP基板。然後透過典型焊料遮罩施加焊料以完成LCP印刷電路板之構造。
儘管此設計不允許形成薄撓性印刷電路板，但其仍具有與上文關於具有緊密間隔之接腳之IC附接至其所闡述的相同之缺點。照此，需要將IC連接至印刷電路板之額外方法。
亦可在將一覆晶IC安裝至印刷電路板上時存在上文所闡述之封裝問題。與線接合IC一樣，一覆晶裝置之板層級互連件可由於有限特徵解析度而包括扇出連接器。此外，在此等應用中，在覆晶IC下方形成底填充黏合劑以提供對IC之機械及環境保護。不論使用覆晶還是線接合IC，當封裝變得更微型化時，控制黏合劑之放置及固化存在更大困難。舉例而言，黏合劑可流動至敏感區域(諸如以光微影方式界定之焊料遮罩開口及互連墊)中。
此外，隨著當前技術水平IC中之經減小接腳大小，發生覆晶IC與基板之間的一經減小支座高度。此可使毛細管底填充技術變得更困難。Chen等人在第7,820,233號美國專利中揭示製造覆晶基板之一種方法。該方法包括：在一載體之一表面上形成一圖案化抗蝕劑層；順序地形成一第一金屬層、一蝕刻停止層及一第二金屬層；移除該抗蝕劑層；及形成一圖案化第一焊料遮罩；及然後在其上形成至少一個第一電路堆積結構。該方法亦包含：在該電路堆積結構上形成一圖案化 第二焊料遮罩；移除該載體、該第一金屬層及該蝕刻停止層；及在該電路堆積結構之兩側上形成焊料凸塊。此一方法之一缺點可係增加之成本，此歸因於製造程序中之高數目個步驟。
鑒於上述背景，因此本發明之一目標係提供一種用於製造具有經減小大小連接器墊之一電子裝置之方法。
藉由製造一電子裝置之一方法提供根據本發明之此及其他目標、特徵及優點，該方法包括：在一基板(例如，LCP)上形成一導電圖案；在該基板及該導電圖案上形成一覆蓋層(例如，LCP)；及形成在該覆蓋層中且與該導電圖案對準之複數個開口。該方法亦包含：將一IC定位在該覆蓋層上以使得該IC之接合墊與該複數個開口對準；及在壓力下加熱該覆蓋層以機械固定且又電互連該IC。有利地，該電子裝置可形成有高解析度及經減小支座高度接合墊連接。
另一態樣針對一種電子裝置，該電子裝置包括：一基板；一導電圖案，其在該基板上且包括複數個跡線；及一覆蓋層，其在該基板及該導電圖案上。該覆蓋層具有在其中與該導電圖案對準之複數個開口，每一開口具有小於該導電圖案中之一各別跡線之寬度之一各別寬度。該電子裝置包括在該覆蓋層上具有在其一表面上之複數個接合墊之一IC。
10‧‧‧電子裝置
11‧‧‧基板/下伏印刷電路板基板
12‧‧‧導電圖案
13‧‧‧覆蓋層/液晶聚合物覆蓋層
14‧‧‧導電材料/導電填充材料
16a‧‧‧開口
16b‧‧‧開口
16c‧‧‧開口
17‧‧‧積體電路
18a‧‧‧接合墊
18b‧‧‧接合墊
18c‧‧‧接合墊
19a‧‧‧導電跡線/跡線/下伏跡線
19b‧‧‧導電跡線/跡線/下伏跡線
19c‧‧‧導電跡線/跡線/下伏跡線
50‧‧‧影像
55‧‧‧經放大影像部分
2-2‧‧‧線
圖1係根據本發明之製造一電子裝置之一方法之一流程圖。
圖2A至圖2D係圖1之方法中之步驟之沿著線2-2之剖面圖之示意圖。
圖3係不具有IC之基板之一實例性實施例之一俯視平面圖。
圖4係來自圖3之基板之一經放大部分。
現在下文將參考其中展示本發明之較佳實施例之附圖來更全面地闡述本發明。然而，本發明可以諸多不同形式體現，且不應被視為限於本文所闡明之實施例。而是，提供此等實施例以使得本發明將係全面及完整的，且將要將本發明之範疇完全傳達給熟習此項技術者。通篇中相同編號係指相同元件。
現在參考圖1至圖2D且參考一流程圖30，現在闡述根據本發明之製造一電子裝置10之一方法。(方塊31)。該方法包括在一基板11上形成一導電圖案12(方塊33)。舉例而言，導電圖案12可包括銅或鋁。而且，基板31可包括一剛性半導體基板(例如，矽、砷化鎵、陶瓷、玻璃)或一有機剛性或撓性基板(例如，LCP、樹脂玻璃壓層、聚醯亞胺、聚四氟乙烯(PTFE))。此步驟亦可包含形成導電圖案12以包含一中間墊(未展示)。
該方法亦包含在基板11及導電圖案12上形成一覆蓋層(覆蓋膜)13(方塊35)。舉例而言，覆蓋層13之形成可包括形成一LCP覆蓋層。在包含LCP覆蓋層實施例之某些實施例中，該方法包含藉由施加熱及壓力而將覆蓋層13層壓至基板11上之步驟。
該方法亦包含在覆蓋層13中形成複數個開口16a至16c(方塊37)。覆蓋層13中之該複數個開口16a至16c之形成可包括雷射銑削該複數個開口。如也許在圖2C中最佳所見，開口16a至16c與導電圖案12之導電跡線19a至19c對準。
在一項實施例中，使用雷射銑削形成開口16a至16c，2012年7月19日發行之第2012/0182702號美國專利申請公開案之揭示內容亦受讓於本申請案之受讓人，該美國專利申請公開案據此以其全文引用方式併入。有利地，該方法利用雷射銑削之經增強解析度以在覆蓋層13中形成開口16a至16c。特定而言，開口16a至16c可形成為與0.001至0.002英吋(25.4至50.8微米)一樣小。舉例而言，雷射銑削步驟可使用 一皮秒脈衝之雷射鑽孔。此外，可在0.0005至0.001英吋範圍(12.7至25.4微米)內達成開口16a至16c之位置準確度。有利地，經增加位置準確度可允許孔隙大小之減小，除墊互連橋接之風險之減小之外此繼而又允許經簡化覆晶組件附接。
覆蓋層13中之該複數個開口16a至16c之形成包括將該複數個開口形成為各自具有小於導電圖案12之一毗鄰部分(即跡線19a至19c)之一各別寬度之一寬度。舉例而言，開口16a至16c可具有小於跡線19a至19c之寬度之各別寬度值，25微米。有利地，此方法可減小橋接毗鄰互連墊之可能性。
該方法進一步包括在IC 17之定位之前在該複數個開口16a至16c中填充導電材料14(方塊39)。在覆蓋層13中形成之開口16a至16c之大小之限制並非藉由雷射而是藉由將導電填充材料14插入至高縱橫比開口中之能力來界定。導電材料14可包括一焊料膏或另一選擇係導電環氧樹脂、金柱凸塊或焊料蓋帽銅柱。
該方法亦包含將一IC17定位在覆蓋層13上以使得IC之接合墊18a至18c與該複數個開口16a至16c對準(方塊41、43)。IC 17可包括任何數目個裝置，諸如一光學感測器、微控制器、場可程式化閘陣列(FPGA)、射頻單片微波積體電路(RF MMIC)、電壓調節器、類比至數位轉換器等。
如也許在圖2C至圖2D中最佳所見，覆蓋層13之形成包括將該覆蓋層形成為具有毗鄰導電圖案12之一較大厚度。覆蓋層13具有毗鄰導電圖案12之一較大厚度以使得其一上表面接觸且密封住IC17之一底側。
實際上，導電圖案12之前述中間墊提供覆蓋層13將具有一一致厚度，藉此達成至IC 17之底側之牢固機械連接。該方法包含在壓力下加熱覆蓋層13以機械固定且又電互連IC17。更具體而言，該方法可 包含加熱基板11，此繼而加熱覆蓋層13。該加熱亦可包含透過一覆晶接合頭部加熱IC 17，此繼而加熱覆蓋層13。
特定而言，該方法可包含使用一覆晶接合頭部工具來局部地加熱覆蓋層13(特定而言其經增加厚度部分)及將IC 17附接至該覆蓋層。IC 17之定位將包括一簡單壓扣就位技術(例如，使用拾放機器)。取決於IC17之接合墊18a至18c之尺寸，覆蓋層13之經增加厚度可經匹配以提供一適當且穩固機械連接。
有利地，覆蓋層13滿足與IC 17之底側接合之典型裝置中之底填充材料之要求。此覆蓋層13提供減小電子裝置10之總體高度之一薄底填充物，然而移除對現有方法之壩狀物及高準確度毛細管作用囊封材料之需要。
另一態樣針對一電子裝置10，該電子裝置包括：一基板11；一導電圖案12，其在該基板上且包括複數個跡線19a至19c；及一覆蓋層13，其在該基板及該導電圖案上。覆蓋層13具有在其中與導電圖案12對準之複數個開口16a至16c，每一開口具有小於該導電圖案中之一各別跡線之寬度之一各別寬度。電子裝置10包括在覆蓋層13上具有在其一表面上之複數個接合墊18a至18c之一IC17。
現在另外參考圖3至圖4，電子裝置10之一實例性實施例之一影像50說明性地包含具有用於耦合其他電子設備之複數個連接器墊之導電圖案12(在基板11之側向邊緣處)。如也許在經放大影像部分55中最佳所見，導電圖案12包含界定IC接合點之跡線19a至19c。有利地，藉由利用前述雷射銑削技術之解析度，觸點具有116.5μm之顯著寬度。
本文中所揭示之方法提供數個技術問題之一方法。特定而言，當對微型電子器件之期望繼續驅動主動組件及被動組件(包含覆晶、表面安裝(SMT)及球形/平臺柵格陣列封裝裝置(BGA、LGA等))之大小之減小時，此等組件之微型化可在其安裝至印刷電路板(PCB)方面提 出一挑戰。此歸因於墊大小及墊之間的間距之一減小，從而需要昂貴設備以用於組件之精確放置。而且，PCB工業中之焊料遮罩及覆蓋層能力當前不可支援覆晶組件之壓扣就位安裝，通常留下墊之間的在製作程序期間存在眾多挑戰之開放區域。
此外，本文中所揭示之方法包含數個額外優點。覆蓋層13中之開口16a至16c藉由雷射銑削之產生可移除對典型成像步驟之要求，此產生一高孔隙位置準確度位準且允許孔隙大小之減小。具有金柱凸塊或習用受控崩潰晶片連接(C4)凸塊之覆晶組件可容易地對準且壓扣就位，而不使用昂貴對準設備。此技術可提供互連方法之靈活性，從而允許導電黏合劑及習用焊料。開口16a至16c大小之此減小繼而允許保護具有較高可靠性之更加稠密之基板。
此外，個別LCP膜層之撓性及其堆疊能力可為眾多柱凸塊高度提供機會同時仍維持晶粒之底側與覆蓋層13之頂部之間的接觸。LCP材料在層壓時形成一近氣密密封，從而當在一非理想工作環境中時保護下伏跡線19a至19c及墊免受氧化。
而且，LCP擁有此一薄膜之一極高抗拉強度，此可提供大於習用焊料遮罩材料(特別係液態光可成像焊料遮罩)之耐磨損及損壞性。在其中覆蓋層13包括LCP之實施例中，其電匹配(介電常數、損耗正切等)至下伏PCB基板11(當使用LCP基板或習用撓性凱通(Kapton)時)。LCP覆蓋層13係匹配至習用PCB材料之熱膨脹係數(CTE)。LCP覆蓋層13可容易地覆蓋及保護下伏導通孔，此在使用當前技術水平液態光可成像焊料遮罩時可係困難的，且LCP覆蓋層可提供與習用焊料遮罩相比較佳之電隔離(典型焊料遮罩必須以500V/mil最小值滿足IPC-SM-840C，LCP係3500V/mil)。
在以其全文引用方式併入本文中之標題為「METHOD FOR MAKING ELECTRONIC DEVICE WITH LIQUID CRYSTAL POLYMER AND RELATED DEVICES」(代理人檔案號為GCSD-2653(62016))之同在申請中之申請案中揭示與電子裝置有關之其他特徵。
受益於前述說明及相關聯圖式中所呈現之教示，熟習此項技術者將聯想到本發明之諸多修改及其他實施例。因此，應理解，本發明不限於所揭示之特定實施例且意欲將修改及實施例包含在隨附申請專利範圍之範疇內。

Claims (10)

  1. 一種製造一電子裝置之方法，其包括：在一基板之一上表面上形成一導電圖案；在該基板及該導電圖案上形成一覆蓋層，該覆蓋層具有與該基板之該上表面直接接觸的一下表面及一上表面；在該覆蓋層中形成與該導電圖案對準之複數個開口；將一積體電路(IC)定位在該覆蓋層上以使得該IC之接合墊與該複數個開口對準及使得該IC之一下表面與該覆蓋層之該上表面直接接觸；及在壓力下加熱該覆蓋層以機械固定且電互連該IC。
  2. 如請求項1之方法，其中該覆蓋層之該形成包括形成一液晶聚合物(LCP)覆蓋層。
  3. 如請求項1之方法，其中該覆蓋層中之該複數個開口之該形成包括雷射銑削該複數個開口。
  4. 如請求項1之方法，其中該覆蓋層中之該複數個開口之該形成包括將該複數個開口形成為每一開口具有一寬度，其小於該導電圖案之一毗鄰部分之一各別寬度。
  5. 如請求項1之方法，其中該覆蓋層之該形成包括將該覆蓋層形成為具有毗鄰該導電圖案之一較大厚度，其較該覆蓋層之其他厚度大。
  6. 如請求項1之方法，其進一步包括在該IC之該定位之前在該複數個開口中填充導電材料。
  7. 如請求項6之方法，其中該導電材料之該填充包括使用焊料膏、導電環氧樹脂、一金柱凸塊及一焊料蓋帽銅柱中之至少一者。
  8. 如請求項1之方法，其中該基板之該形成包括形成一LCP層。
  9. 一種製造一電子裝置之方法，其包括：在一基板之一上表面上形成一導電圖案；在該基板及該導電圖案上形成一液晶聚合物(LCP)覆蓋層，該LCP覆蓋層具有與該基板之該上表面直接接觸的一下表面及一上表面；層壓該LCP覆蓋層至該基板及該導電圖案上；在該LCP覆蓋層中形成與該導電圖案對準之複數個開口；將一積體電路(IC)定位在該LCP覆蓋層上以使得該IC之接合墊與該複數個開口對準及使得該IC之一下表面與該LCP覆蓋層之該上表面直接接觸；及在壓力下加熱該LCP覆蓋層以機械固定且電互連該IC。
  10. 如請求項9之方法，其中該LCP覆蓋層中之該複數個開口之該形成包括雷射銑削該複數個開口。
TW103121266A 2013-07-03 2014-06-19 用以製造包含具有開口之覆蓋層之電子裝置之方法及相關裝置 TWI546924B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US13/934,465 US9293438B2 (en) 2013-07-03 2013-07-03 Method for making electronic device with cover layer with openings and related devices

Publications (2)

Publication Number Publication Date
TW201513287A TW201513287A (zh) 2015-04-01
TWI546924B true TWI546924B (zh) 2016-08-21

Family

ID=51211903

Family Applications (1)

Application Number Title Priority Date Filing Date
TW103121266A TWI546924B (zh) 2013-07-03 2014-06-19 用以製造包含具有開口之覆蓋層之電子裝置之方法及相關裝置

Country Status (3)

Country Link
US (2) US9293438B2 (zh)
TW (1) TWI546924B (zh)
WO (1) WO2015002921A1 (zh)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10159154B2 (en) 2010-06-03 2018-12-18 Hsio Technologies, Llc Fusion bonded liquid crystal polymer circuit structure
US10667410B2 (en) 2013-07-11 2020-05-26 Hsio Technologies, Llc Method of making a fusion bonded circuit structure
US10506722B2 (en) 2013-07-11 2019-12-10 Hsio Technologies, Llc Fusion bonded liquid crystal polymer electrical circuit structure
KR101654801B1 (ko) * 2014-08-08 2016-09-07 서울대학교산학협력단 액정 폴리머 기반의 신경 임플란트용 전극 어레이와 패키지 및 그 제조 방법
US9521752B2 (en) * 2014-09-19 2016-12-13 Harris Corporation Method of making an electronic device having a thin film resistor formed on an LCP solder mask and related devices
EP3076772A3 (en) * 2015-03-30 2016-10-19 HSIO Technologies, LLC Fusion bonded liquid crystal polymer electrical circuit structure
CN107660066B (zh) * 2017-10-31 2024-05-14 北京京东方显示技术有限公司 一种柔性电路板、其制作方法及显示装置
EP3799114A1 (de) * 2019-09-27 2021-03-31 Dyconex AG Thermokompression-bonding von elektronischen komponenten
TWI708536B (zh) * 2019-11-25 2020-10-21 欣興電子股份有限公司 移除局部蓋體的裝置及移除局部蓋體的方法
DE102021210067A1 (de) 2021-09-13 2023-03-16 E.G.O. Elektro-Gerätebau GmbH Elektrisches Schaltungsbauteil und Verfahren zur Herstellung eines elektrischen Schaltungsbauteils
CN115881655A (zh) * 2023-02-16 2023-03-31 成都频岢微电子有限公司 一种射频前端模组封装工艺结构

Family Cites Families (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5258236A (en) 1991-05-03 1993-11-02 Ibm Corporation Multi-layer thin film structure and parallel processing method for fabricating same
DE1025587T1 (de) * 1997-07-21 2001-02-08 Aguila Technologies, Inc. Halbleiter-flipchippackung und herstellungsverfahren dafür
US6265776B1 (en) 1998-04-27 2001-07-24 Fry's Metals, Inc. Flip chip with integrated flux and underfill
JP3346320B2 (ja) * 1999-02-03 2002-11-18 カシオ計算機株式会社 半導体装置及びその製造方法
US6036809A (en) 1999-02-16 2000-03-14 International Business Machines Corporation Process for releasing a thin-film structure from a substrate
US6372992B1 (en) 2000-10-05 2002-04-16 3M Innovative Properties Company Circuit protective composites
JP2002141370A (ja) 2000-11-02 2002-05-17 Matsushita Electric Ind Co Ltd 半導体装置とその製造方法及び製造装置ならびに半導体装置の実装方法
JP3407737B2 (ja) 2000-12-14 2003-05-19 株式会社デンソー 多層基板の製造方法およびその製造方法によって形成される多層基板
US20020180029A1 (en) 2001-04-25 2002-12-05 Hideki Higashitani Semiconductor device with intermediate connector
JP2003124251A (ja) 2001-10-10 2003-04-25 Matsushita Electric Ind Co Ltd 半導体装置と実装構造及びその製造方法
US6627844B2 (en) * 2001-11-30 2003-09-30 Matsushita Electric Industrial Co., Ltd. Method of laser milling
US7485489B2 (en) 2002-06-19 2009-02-03 Bjoersell Sten Electronics circuit manufacture
JP3575478B2 (ja) 2002-07-03 2004-10-13 ソニー株式会社 モジュール基板装置の製造方法、高周波モジュール及びその製造方法
US6998327B2 (en) 2002-11-19 2006-02-14 International Business Machines Corporation Thin film transfer join process and multilevel thin film module
US8129841B2 (en) * 2006-12-14 2012-03-06 Stats Chippac, Ltd. Solder joint flip chip interconnection
JP2005203646A (ja) 2004-01-19 2005-07-28 Nec Kansai Ltd 半導体実装体
KR101183272B1 (ko) 2004-02-23 2012-09-14 조지아 테크 리서치 코오포레이션 Ｒｆ/무선 다중 대역 응용들을 위한 액정 폴리머 및 다층폴리머 기반 수동 신호 처리 부품들
US20060068576A1 (en) 2004-09-30 2006-03-30 Burdick William E Jr Lithography transfer for high density interconnect circuits
WO2006044739A2 (en) 2004-10-18 2006-04-27 Intraglobal Corporation Microelectronics package and method
US7343675B2 (en) 2004-11-12 2008-03-18 Harris Corporation Method of constructing a structural circuit
US7226821B2 (en) 2005-06-24 2007-06-05 Cardiac Pacemakers, Inc. Flip chip die assembly using thin flexible substrates
DE102005032489B3 (de) 2005-07-04 2006-11-16 Schweizer Electronic Ag Leiterplatten-Mehrschichtaufbau mit integriertem elektrischem Bauteil und Herstellungsverfahren
US7845954B2 (en) 2005-07-14 2010-12-07 Panasonic Corporation Interconnecting board and three-dimensional wiring structure using it
US8335084B2 (en) 2005-08-01 2012-12-18 Georgia Tech Research Corporation Embedded actives and discrete passives in a cavity within build-up layers
KR101134168B1 (ko) * 2005-08-24 2012-04-09 삼성전자주식회사 반도체 칩 및 그 제조 방법과, 그를 이용한 표시 패널 및그 제조 방법
US7820233B2 (en) 2006-09-27 2010-10-26 Unimicron Technology Corp. Method for fabricating a flip chip substrate structure
US8161633B2 (en) 2007-04-03 2012-04-24 Harris Corporation Method of fabricating non-planar circuit board
US7936567B2 (en) 2007-05-07 2011-05-03 Ngk Spark Plug Co., Ltd. Wiring board with built-in component and method for manufacturing the same
KR100867148B1 (ko) 2007-09-28 2008-11-06 삼성전기주식회사 인쇄회로기판 및 그 제조방법
JP5436774B2 (ja) 2007-12-25 2014-03-05 古河電気工業株式会社 多層プリント基板およびその製造方法
JP4876272B2 (ja) * 2008-04-02 2012-02-15 サムソン エレクトロ−メカニックス カンパニーリミテッド． 印刷回路基板及びその製造方法
US20090289360A1 (en) * 2008-05-23 2009-11-26 Texas Instruments Inc Workpiece contact pads with elevated ring for restricting horizontal movement of terminals of ic during pressing
JP4557186B2 (ja) 2008-06-25 2010-10-06 株式会社村田製作所 無線ｉｃデバイスとその製造方法
US20100066683A1 (en) 2008-09-17 2010-03-18 Shih-Chang Chang Method for Transferring Thin Film to Substrate
US7898074B2 (en) 2008-12-12 2011-03-01 Helmut Eckhardt Electronic devices including flexible electrical circuits and related methods
FI124221B (fi) 2009-04-24 2014-05-15 Valtion Teknillinen Käyttäjäsyötejärjestely ja siihen liittyvä valmistusmenetelmä
US8987886B2 (en) 2009-06-02 2015-03-24 Hsio Technologies, Llc Copper pillar full metal via electrical circuit structure
US20120098129A1 (en) 2010-10-22 2012-04-26 Harris Corporation Method of making a multi-chip module having a reduced thickness and related devices
US8867219B2 (en) 2011-01-14 2014-10-21 Harris Corporation Method of transferring and electrically joining a high density multilevel thin film to a circuitized and flexible organic substrate and associated devices
US8844125B2 (en) 2011-01-14 2014-09-30 Harris Corporation Method of making an electronic device having a liquid crystal polymer solder mask and related devices
US8877558B2 (en) 2013-02-07 2014-11-04 Harris Corporation Method for making electronic device with liquid crystal polymer and related devices

Also Published As

Publication number Publication date
US9681543B2 (en) 2017-06-13
US9293438B2 (en) 2016-03-22
TW201513287A (zh) 2015-04-01
WO2015002921A1 (en) 2015-01-08
US20160174371A1 (en) 2016-06-16
US20150009644A1 (en) 2015-01-08

Similar Documents

Publication Publication Date Title
TWI546924B (zh) 用以製造包含具有開口之覆蓋層之電子裝置之方法及相關裝置
US10515918B2 (en) Methods of fluxless micro-piercing of solder balls, and resulting devices
US8410614B2 (en) Semiconductor device having a semiconductor element buried in an insulating layer and method of manufacturing the same
TWI415542B (zh) A printed wiring board, and a printed wiring board
TWI496259B (zh) 封裝裝置及其製造方法
EP2664226B1 (en) Method of making an electronic device having a liquid crystal polymer solder mask laminated to an interconnect layer stack
KR20080069712A (ko) 회로 장치 및 회로 장치의 제조 방법
KR20090048362A (ko) 반도체 장치의 제조 방법 및 반도체 장치
JPWO2020090601A1 (ja) 半導体パッケージ用配線基板及び半導体パッケージ用配線基板の製造方法
JP2008270362A (ja) 積層配線基板及びその製造方法
US10103121B2 (en) Tall and fine pitch interconnects
US8877558B2 (en) Method for making electronic device with liquid crystal polymer and related devices
US8168525B2 (en) Electronic part mounting board and method of mounting the same
JP5285385B2 (ja) 積層配線基板の製造方法
JP4593444B2 (ja) 電子部品実装構造体の製造方法
TWI418276B (zh) 導電凸塊無翼部的封裝基板之製法
US20050094383A1 (en) Substrate for use in forming electronic package
JP2004063890A (ja) 半導体装置の製造方法
KR101376765B1 (ko) 인터포저가 필요없는 몰딩 패키지 제조 방법
JP2009064879A (ja) 半導体装置およびその製造方法
KR20110129506A (ko) 플립칩 패키지 기판의 범프 제조방법
JP2013141042A (ja) バンプ構造およびその製造方法