TWI541872B - 形成於半導體基板上的整合晶片及其製造方法 - Google Patents

形成於半導體基板上的整合晶片及其製造方法 Download PDF

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TWI541872B
TWI541872B TW103146197A TW103146197A TWI541872B TW I541872 B TWI541872 B TW I541872B TW 103146197 A TW103146197 A TW 103146197A TW 103146197 A TW103146197 A TW 103146197A TW I541872 B TWI541872 B TW I541872B
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channel
implant
regions
transistor
substrate
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TW201539549A (zh
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余宗興
黃士軒
後藤賢一
許義明
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台灣積體電路製造股份有限公司
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Description

形成於半導體基板上的整合晶片及其製造方法
本發明係有關於半導體,且更特別是有關於具有反向環形佈植的磊晶通道。
電晶體高度地被使用於現今的積體電路(ICs)以放大或切換電子訊號。現今的半導體IC在單一的IC上包括了數百萬或甚至數十億的電晶體。為了保證適當的良率,電晶體元件的各種成分和組成都必須在準確及精確的位置被製造。這種要素之一為摻雜物雜質(dopant impurities),其被導入至電晶體的通道區域中。摻雜物雜質直接地影響電晶體的功能性和性能。摻雜物雜質的特色和位置,或“摻雜輪廓”,必須被小心地控制。半導體製程中的變數可造成電晶體元件中的變數,性能下降,及可能的良率損失。
根據一實施例,本發明提供一種方法,包括:形成複數個第一閘極結構於一基板上,其中第一閘極結構具有一垂直尺寸(h)且被一第一水平間隔(s1)隔離;形成複數個第二閘極結構於基板上,其中第二閘極結構具有垂直尺寸(h)且被一第二水平間隔(s2)隔離,其大於第一水平間隔(s1); 以及以一垂直角度實施一佈植以將摻雜物雜質導入基板中,其中此角度大於一第一閾值以使得佈植被第一閘極結構阻擋以免到達基板。
根據另一實施例,本發明提供一種方法,包括:將一第一雜質類型的摻雜物雜質導入一基板的第一和第二電晶體區域中,其中第一和第二電晶體區域分別包括第一和第二通道區域及第一和第二源極/汲極區域;凹陷基板至第一和第二電晶體區域之上;形成第一和第二含碳材料層於第一和第二電晶體區域之上;形成第一和第二基板材料層於第一和第二含碳材料層之上;形成第一和第二閘極介電質於第一和第二基板材料層之上;形成第一和第二閘極結構於第一和第二通道區域中的第一和第二閘極介電質之上,其中第一閘極結構被一第一水平間隔(s1)自一第三閘極結構隔離,其中第二閘極結構被一第二水平間隔(s2)自一第四閘極結構隔離,且其中s2大於s1;以一第一角度實施一第一佈植以將更多第一雜質類型的摻雜物雜質導入基板的第一和第二通道區域的邊緣中;以及以一第二垂直角度實施一第二佈植以導入一第二雜質類型的摻雜物雜質,其與第一雜質類型相反,其中第二角度大於一第一閾值以使得第二佈植被第三閘極結構阻擋以免到達第一通道區域。
又根據另一實施例,本發明提供一種形成於一半導體基板上的整合晶片,包括:一第一電晶體,其包括一第一閘極電極和具有第一通道長度L1的一第一通道區域;一第二電晶體,包括一第二閘極電極和具有第二通道長度L2的一第二通 道區域;其中第一和第二通道區域已被摻雜物雜質摻雜以使得第一和第二通道區域的一摻雜物濃度於第一和第二通道區域的邊緣高於第一和第二通道區域的中央;以及其中摻雜物濃度於第一通道區域的邊緣高於第二通道區域的邊緣。
為讓本發明之上述和其他目的、特徵、和優點能更明顯易懂,下文特舉出較佳實施例,並配合所附圖式,作詳細說明如下:
100A‧‧‧短通道電晶體
102、302‧‧‧基板
104A、104B‧‧‧閘極結構
106‧‧‧閘極電極
108‧‧‧硬罩幕(HM)
110‧‧‧源極/汲極區域
112A、112B、402A、402B‧‧‧通道區域
200、600‧‧‧方法
202-206、602-616‧‧‧步驟
400A‧‧‧短通道電機體
400B‧‧‧長通道電機體
304‧‧‧Vth佈植
306‧‧‧含碳材料
308‧‧‧基板材料
310‧‧‧閘極介電質
312、314‧‧‧閘極結構
316‧‧‧環形佈植
318‧‧‧LDD區域
320‧‧‧高度摻雜區域
322‧‧‧反向環形佈植
324‧‧‧間隔
326‧‧‧源極/汲極佈植
328‧‧‧源極/汲極區域
500A、500B‧‧‧圖
h‧‧‧高度
L1、L2‧‧‧長度
S1、S2‧‧‧間隔
θ1、θ2‧‧‧角度
d‧‧‧深度
A-A’‧‧‧線
第1A-1B圖顯示在長通道電晶體中施行反向環形佈植並同時在短通道電晶體中遮蔽(shadowing)反向環形佈植的一些實施例的剖面圖。
第2圖顯示在複數個長通道電晶體中施行反向環形佈植並同時在複數個短通道電晶體中遮蔽反向環形佈植的方法的一些實施例。
第3A-3J圖顯示形成具有反向環形佈植的電晶體的一些實施例的剖面圖。
第4圖顯示利用第3A-3J圖的實施例形成於相同的基板上的短通道電晶體和長通道電晶體的一些實施例之剖面圖。
第5A-5B圖顯示給予接收反向環形佈植的長通道電晶體和因為遮蔽(shadowing)而未接收反向環形佈植的短通道電晶體的摻雜物濃度的一些實施例的圖。
第6圖顯示形成具有反向環形佈植的長通道電晶體且同時避免短通道電晶體接收反向環形佈植的方法的一些實施例。
此處的描述參照圖式進行,其中全文中相似的參考符號一般用來代表相似的元件,且其中各結構未必按照比例繪製。在以下的描述中,為了解釋的目的,列舉眾多具體細節以便於理解。然而,顯而易見的,對於本技術領域具有通常知識者來說,可藉由比這些具體細節較少的程度來實施此處描述的一個或多個方面。在其他實例中,已知的結構及裝置以方框圖的形式顯示以便於理解。
由短通道長度電晶體形成的半導體基板相對長通道電晶體受到汲極-誘導的位障降低(drain-induced barrier lowing;DIBL),是因為低通道摻雜或過深的源極/汲極界面。DIBL導致電晶體的源極和汲極之間的漏損(leakage),其可導致閘極控制損耗。為了抵抗這種影響,一種局部的(localized)環形(halo)佈植被用來增加靠近通道的源極/汲極區域的通道摻雜物濃度。在這些區域中,較高的摻雜降低了源極和汲極之間的交互作用而不影響元件的閾值電壓(Vth)。然而,雖然環形佈植可改良性能並降低短通道電晶體中的漏損,它可降低長通道電晶體的源極-至-汲極跨導(transconductance;Gds)。
因此,本發明的一些實施例係有關於一佈植技術,此技術能改善長通道電晶體性能但對於短通道電晶體性能卻只有很小的影響,甚至沒有任何影響。為了減少DIBL,基板上的長通道和短通道電晶體都必須實施環形佈植(halo implant)。雖然環形佈植改良短通道電晶體的性能,它卻降低了長通道電晶體的性能。因此,反向環形佈植(counter-halo implant)必 須進一步被施行在長通道電晶體上使能恢復它們的性能。為了達到此目的,反向環形佈植以一角度被施行,其將摻雜物雜質(dopant impurities)導入靠近長通道電晶體的源極/汲極區域中以抵消環形佈植的影響,在實施反向環形佈植的同時,短通道電晶體的通道必須被遮蔽以避免受到影響。在此揭露的實施例可改良長通道電晶體的DIBL,Gds,並對短通道電晶體性能上造成很小的影響至沒有影響,且沒有額外的光罩花費。
第1A圖顯示形成於基板102上的一對短通道電晶體100A的一些實施例的剖面圖,包括具有通道長度L1的第一和第二通道區域112A、112B,位於複數個源極/汲極區域110之間。該對短通道電晶體也包括第一和第二閘極結構104A、104B,每一個是由位於一閘極電極106上的硬罩幕(HM)108所組成。對於短通道電晶體100A,第一和第二閘極結構104A、104B具有一垂直尺寸(h)且被一第一水平間隔(s1)隔離。第1B圖顯示一對長通道電晶體100B的一些實施例的剖面圖,其與該對短通道電晶體100A由相同的元件和成分所組成,但有具有通道長度L2的第一和第二通道區域112A、112B,其中L2>L1。此外,此對長通道電晶體100B被一第二水平間隔(s2)隔離。
短通道電晶體100A和長通道電晶體100B都實施環形佈植以緩和短通道電晶體100A中的DIBL。為了抵消長通道電晶體100B中Gds降低的影響,反向環形佈植被實施在此對長通道電晶體100B上使能恢復它們的性能。為了達到此目的,一佈植角度被選擇以使得被佈植的摻雜物雜質到達長通道電晶體100B的第一和第二通道區域112A、112B,但被阻擋以防到 達短通道電晶體100A的第一和第二通道區域112A、112B。
對於短通道電晶體100A,大於反正切(s1/h)的第一角度(θ1)將不允許反向環形佈植到達短通道電晶體100A的第一和第二通道區域112A、112B,因為遮蔽相鄰閘極結構的佈植。相反的,對於長通道電晶體100B,小於反正切(s2/h)的第二角度(θ2)將使反向環形佈植到達長通道電晶體100B的第一和第二通道區域112A、112B。因此,θ2>θ>θ1的反向環形佈植角度將使反向環形佈植僅到達長通道電晶體100B的第一和第二通道區域112A、112B,而不影響短通道區域100A。如此避免產生專用的罩幕所需的額外的成本和製造費用以只在長通道電晶體100B上實施反向環形佈植。
第2圖顯示在複數個長通道電晶體上實施反向環形佈植並同時在複數個短通道電晶體上遮蔽反向環形佈植的方法200之一些實施例。雖然方法200,及隨後的方法400,是以一系列的動作或事件被描述,應當理解的是,所示的這些動作或事件的順序不應被解讀為一種限制。例如,一些動作可以不同的順序發生及/或與所示及/或此處描述之外的其他動作或事件同時發生。此外,未必需要所有顯示的動作以實施在此描述的一個或多個方面或實施例。再者,在此描述的一個或多個動作可透過一個或多個分開的動作及/或階段被實施。
於202,複數個第一閘極結構形成於一基板上。第一閘極結構具有垂直尺寸(h)且被一第一水平間隔(s1)隔離。
於204,複數個第二閘極結構形成於一基板上。第 二閘極結構具有垂直尺寸(h)且被一第二水平間隔(s2)隔離,其大於第一水平間隔(s1)。
於206,以一垂直角度(angle with vertical)實施反向環形佈植以將摻雜物雜質導入基板中。此角度大於第一閾值反正切(s1/h)以使得佈植被第一閘極結構阻擋以免到達基板。並且,此角度小於一第二閾值反正切(s2/h)以使得佈植不被第二閘極結構阻擋而無法到達基板。
第3A-3J圖顯示形成具有反向環形佈植的電晶體的一些實施例之剖面圖。
第3A圖顯示基板302的一些實施例的剖面圖,其中一井(well)和Vth佈植304被用來將第一雜質類型的摻雜物雜質導入基板302的電晶體區域中。Vth佈植將第一雜質類型的摻雜物雜質導入基板302的電晶體區域中以校正形成於後續製程步驟中形成的電晶體的Vth。在一些實施例中,摻雜物雜質包括p-型摻雜物雜質,像是硼、碳、銦、等。在一些實施例中,摻雜物雜質包括n-型摻雜物雜質,像是磷、銻、或砷等。在各實施例中,Vth佈植使用一佈植能量,其範圍介於約5keV至約150keV。
第3B圖顯示基板302的一些實施例的剖面圖,其中退火操作係用以活化植入的雜質,或用以消除於井(well)和Vth佈植304期間導入的晶體缺陷(crystalline defects),並促進摻雜物雜質的擴散和重分佈。各種傳統的退火操作可被使用且退火操作可驅使植入的摻雜物雜質更深入半導體基板302中,如第3B圖中基板302的黑色梯度所示。
第3C圖顯示基板302的一些實施例的剖面圖,其在電晶體區域中凹陷至一深度(d)。在一些實施例中,凹陷的形成包括一個或多個蝕刻製程,包括但不限於乾蝕刻像是電漿蝕刻製程、濕蝕刻製程、或兩者的組合。在一些實施例中,濕蝕刻被用來形成凹陷。例如,蝕刻劑像是四氟化碳(CF4)、HF、四甲基氫氧化銨(TMAH)、或前述之組合、或其類似物可被用來實施濕蝕刻並形成凹陷。
第3D圖顯示基板302的一些實施例的剖面圖,其中一含碳材料306層位於電晶體區域之上。在一些實施例中,含碳材料306包括碳化矽(SiC)。
第3E圖顯示基板302的一些實施例的剖面圖,其中一基板材料308層位於含碳材料306層之上。在一些實施例中,基板材料308層包括矽(Si)。在各實施例中,含碳材料306層和基板材料308層透過合適的磊晶法被配置,像是化學氣相沉積(CVD)、低壓CVD(LPCVD)、原子層CVD(ALCVD)、超高真空CVD(UHCVD)、減壓CVD(RPCVD)、任何合適的CVD;分子束磊晶(MBE)製程、或任何合適的前述組合。在一些實施例中,含碳材料306層具有一厚度,其範圍介於約2奈米(nm)至約15nm。在一些實施例中,基板材料308層具有一厚度,其範圍介於約5nm至約30nm。
第3F圖顯示基板302的一些實施例的剖面圖,其中閘極介電質310位於基板材料308層之上。在各實施例中,閘極介電質310的配置是透過前述的磊晶法,或透過各種合適的介電質沉積製程完成的。在一些實施例中,閘極介電質310包括 一高介電常數(high-k)層像是二氧化鉿(HfO)。其他實施例可使用其他合適的高介電常數介電材料。其他實施例可使用一氧化層像是二氧化矽(SiO2)。在一些實施例中,閘極介電質310具有一厚度,其範圍介於約1nm至約30nm。
第3G圖顯示基板302的一些實施例的剖面圖,其中閘極結構(312、314)位於基板302的通道區域中的閘極介電質310之上。對於第3G圖的實施例,閘極結構包括一閘極電極312(例如:多晶矽),其位於閘極介電質310之上,及一硬罩幕314形成於閘極電極312之上。在各實施例中,閘極結構是透過一合適的微影方法形成的,包括但於,光學微影、多重圖案化(MP)光學微影(例如:雙重-圖案化)、深紫外光(UV)微影、極紫外光(EUV)微影、或其他合適的圖案化技術。
第3H圖顯示基板302的一些實施例的剖面圖,其中輕-摻雜-汲極(LDD)佈植(未顯示)和環形佈植316在圖案化閘極結構以形成LDD區域318之後被實施。LDD佈植使用一第二雜質類型(亦即,n-型或p-型)的摻雜物,與第3A圖所示第一雜質類型的井和Vth佈植相反。對於第3A-3J圖的實施例,LDD區域318使用n-型摻雜物(例如:磷、銻、或砷、等)且井和Vth佈植304使用P-型摻雜物(例如:硼、碳、銦、等)。
在各實施例中,環形佈植316以相對於垂直為20度或更小的第一傾角(θ1)被實施。環形佈植316將第一雜質類型(亦即,與井和Vth佈植304相同)的摻雜物雜質導入形成於閘極結構下的通道區域的相反邊緣的高度摻雜區域320中,以減緩DIBL效應。在一實施例中,環形佈植316被用來導入銦和碳 的混合物。在另一個實施例中,環形佈植316被用來將銦、硼、或BF2導入高度摻雜區域320。
第3I圖顯示基板302的一些實施例的剖面圖,其中反向環形佈植322被實施以沉積第二雜質類型(亦即,與井和Vth佈植304相反)的摻雜物雜質。反向環形佈植322補償位於通道區域的相反邊緣的高度摻雜區域320。對於基板302包括具有多個通道長度的電晶體的實施例,反向環形佈植322以第二垂直傾角(θ2)(second tilt angle with vertical)被實施。第二傾角(θ2)被選擇以使得相對地長通道電晶體接收到佈植,而相對短通道電晶體因為鄰近的閘極結構所造成的短通道電晶體的通道區域的遮蔽(shadowing)而不接收佈植,如第1A-1B圖的實施例所示。反向環形佈植322導致的結果為,長通道電晶體的DIBL、Gds和增益被改善,而短通道電晶體保持不被影響。
在一些實施例中,由基板材料308層和含碳材料306層形成的磊晶通道受到額外的“大劑量(heavy dose)”Vth佈植。此額外的Vth佈植提升了短通道元件的磊晶通道中的源極-至-汲極的電流控制。然而,此額外的Vth佈植也可增加長通道電晶體的Vth約30mV至約100mV。因此,用來僅曝露長通道電晶體至反向環形佈植322的遮蔽方法也可以用來抵抗(counter-act)大劑量Vth佈植的效應。長通道電晶體的磊晶通道可為了“長通道Vth還原”佈植而透過遮蔽方法被隔離。長通道Vth還原佈植以第二傾角(θ2)被實施,以使得相對地長通道電晶體再一次接收佈植,而相對地短通道電晶體再一次因為 遮蔽而不接收佈植。長通道Vth還原佈植的條件(例如:劑量、能量等)可被調整以降低長通道元件的閾值電壓,降低的量與大劑量Vth佈植所增加的量相同(例如:約30mV至約100mV)。因此,包括基板材料308層和含碳材料306層的磊晶通道的長通道電晶體的Vth可大約等於具有直接形成於基板302中的通道(亦即,沒有磊晶通道)的長通道電晶體的Vth
第3J圖顯示基板302的一些實施例的剖面圖,其中間隔324被形成。在各實施例中,間隔324包括氧化物、矽化物、和氮化物的結合。間隔形成後,基板302接著實施源極/汲極佈植326、或嵌入式源極/汲極磊晶(未顯示),以形成源極/汲極區域328。源極/汲極區域328包括第二摻雜物雜質類型(亦即,與LDD區域318相同)。
第4圖顯示透過第3A-3J圖的實施例形成於相同基板302上的短通道電機體400A和長通道電晶體400B的一些實施例的剖面圖。短通道電晶體400A不接收反向環形佈植322,而長通道電晶體400B接收反向環形佈植322。短通道電晶體400A具有第一通道區域,其具有通道長度L1,且長通道電晶體400B具有第二通道區域,其具有通道長度L2,其中L2>L1。對於第4圖的實施例,短通道和長通道電晶體400A、400B包括形成於矽基板302上的n-型金氧半場效電晶體(MOSFETs)。短通道和長通道電晶體400A、400B更包括第一和第二通道區域402A、402B,其已被比第一和第二通道區域402A、402B的其他部分更高濃度水平的p-型摻雜物雜質(例如:硼、碳、銦等)所摻雜。LDD和源極/汲極區域318、328係以n-型摻雜物雜質(例如: 磷、銻、或砷)所形成。
第5A-5B圖顯示沿著第4圖線AA’的短通道電晶體400A和長通道電晶體400B的摻雜濃度的一些實施例的圖500A、500B。第5A-5B圖顯示在反向環形佈植322之前和之後,在第一和第二通道區域402A、402B邊緣的摻雜濃度都較高。然而,可觀察到第二通道區域402B的每一個端點上的摻雜濃度在反向環形佈植322之後被降低了△的量。在長通道電晶體400B中,由環形佈植316所創造出的摻雜濃度可被反向環形佈植322所補償,相對於短通道電晶體400A,使得長通道電晶體400B沿著通道方向AA’具有更平坦的通道輪廓。
應注意的是,雖然以上的實施例描述的是n-型MOSFET,所揭露的實施例也可透過與此述相反的摻雜類型而應用於p-型MOSFET。
第6圖顯示形成具有反向環形佈植的長通道電晶體,同時避免短通道電晶體接收反向環形佈植的方法600的一些實施例。
於602,第一雜質類型的摻雜物雜質被導入基板的第一和第二電晶體區域中,其中第一和第二電晶體區域分別包括第一和第二通道區域及第一和第二源極/汲極區域。在一些實施例中,退火在將第一雜質類型的摻雜物雜質導入基板的第一和第二電晶體區域中之後被實施。
於604,凹陷基板至第一和第二電晶體區域之上。
於606,第一和第二含碳材料(例如:碳化矽)層被形成在第一和第二電晶體區域之上。
於608,第一和第二基板材料(例如:矽)層被形成在第一和第二含碳材料層之上。
於610,第一和第二閘極介電質(例如:HfO)被形成在第一和第二基板材料層之上。
於612,第一和第二閘極結構被形成在第一和第二通道區域中的第一和第二介電質之上。第一閘極結構被第一水平間隔(s1)自第三閘極結構隔離。且,第二閘極結構被第二水平間隔(s2)自第四閘極結構隔離,其中s2>s1。第一到第四閘極結構都具有垂直尺寸(h)。
於614,第一佈植(亦即,環形佈植)以第一角度被實施以將更多第一雜質類型的摻雜物雜質導入基板的第一和第二通道區域的邊緣中。
於616,第二佈植(亦即,反向環形佈植)以一第二垂直角度被實施以將第二雜質類型的摻雜物雜質,其與第一雜質類型相反,導入第一和第二通道區域中。第二角度大於第一閾值反正切(s1/h),以使得第二佈植被第三閘極結構阻擋以免到達第一通道區域。第二角度也小於第二閾值反正切(s2/h),以使得佈植不被第四閘極結構阻擋而無法到達第二通道區域。
在一些實施例中,第三佈植(例如:“大劑量”Vth佈植)被實施以將第一額外摻雜物雜質導入第一和第二通道區域中。第三佈植提升第一通道區域中源極-至-汲極的電流控制,但增加第二通道區域中的閾值電壓一△(delta)值(例如:介於一範圍約30mV至約100mV)。在這樣的實施例中, 第四佈植(例如:“長通道Vth還原”佈植)可以第二垂直角度被實施以將第二額外摻雜物雜質導入第二通道區域中。第二額外摻雜物雜質再次被第三閘極結構阻擋以免到達第一通道區域。第四佈植降低第二通道區域中的閾值電壓約△(delta)值。因此,具有包括磊晶通道的第二通道區域的電晶體的Vth可約等於具有直接襲成在基板302中的第二通道區域的電晶體的Vth
應理解的是,本技術領域具有通常知識者基於閱讀及/或瞭解本說明書和附圖,可進行相等的置換及/或修飾。本揭露包括所有的這種修飾及置換且一般不限於此。此外,雖特定元件或方面僅以數個實施例之一揭露,這種特徵或方面可因應需求而與其他實施例的一或多個其他特徵及/或方面結合。此外,此處“包括(includes)”、“具有(having)”、“具有(has)”、“具有(with)”、及/或其變化被使用的範圍中,這樣的用語被用來代表與“包括(comprising)”類似的包容性意義。並且,“實施例(exemplary)”僅意味著代表一個範例,而不是最好的。也應理解的是,此處所描述的特徵、層及/或元件係以相對於彼此的特定尺寸及/或方位顯示以達到簡化及易於了解的目的,其實際尺寸及/或方位可大致上不同於此處所示。
因此,本發明的一些實施例係有關於一佈植技術,此技術能改善長通道電晶體性能但對於短通道電晶體性能卻只有很小的影響,甚至沒有任何影響。為了減少DIBL,基板上的長通道和短通道電晶體都必須實施環形佈植(halo implant)。雖然環形佈植改良短通道電晶體的性能,它卻降低了長通道電 晶體的性能。因此,反向環形(counter-halo implant)佈植必須進一步被實施在長通道電晶體上使能恢復它們的性能。為了達到此目的,反向環形佈植以一角度被實施,其將摻雜物雜質導入靠近長通道電晶體的源極/汲極區域中以抵消環形佈植的影響,在實施反向環形佈植的同時,短通道電晶體的通道必須被遮蔽以避免受到影響。在此揭露的實施例可改善長通道電晶體的DIBL、Gds、增益,並對短通道電晶體性能上造成很小的影響至沒有影響,且沒有額外的光罩花費。
在一些實施例中,本揭露係關於一種方法,包括形成複數個第一閘極結構於一基板上,其中這些第一閘極結構具有一垂直尺寸(h)且被一第一水平間隔(s1)隔離。這種方法更包括形成複數個第二閘極結構於基板上,其中第二閘極結構具有垂直尺寸(h)且被一第二水平間隔(s2)隔離,其大於第一水平間隔(s1)。這種方法更包括以一垂直角度實施一佈植以將摻雜物雜質導入基板中,其中此角度大於一第一閾值以使得此佈植被第一閘極結構阻擋以免到達基板。
在一些實施例中,本揭露係關於一種方法,包括將一第一雜質類型的摻雜物雜質導入一基板的第一和第二電晶體區域中,其中第一和第二電晶體區域分別包括第一和第二通道區域及第一和第二源極/汲極區域。這種方法更包括凹陷基板至第一和第二電晶體區域之上,並形成第一和第二含碳材料層於第一和第二電晶體區域之上。這種方法更包括形成第一和第二基板材料層於第一和第二含碳材料層之上,且形成第一和第二閘極介電質於第一和第二基板材料層之上。這種方法更 包括形成第一和第二閘極結構於第一和第二通道區域中的第一和第二閘極介電質之上。第一閘極結構被一第一水平間隔(s1)自一第三閘極結構隔離,且第二閘極結構被一第二水平間隔(s2)自一第四閘極結構隔離(s2>s1)。這種方法更包括以一第一角度實施一第一佈植以將更多第一雜質類型的摻雜物雜質導入基板的第一和第二通道區域的邊緣中。這種方法更包括以一第二垂直角度實施一第二佈植以將一第二雜質類型的摻雜物雜質導入第一和第二通道區域中。第二雜質類型的摻雜物雜質與第一雜質類型相反。第二角度大於第一閾值以使得第二佈植被第三閘極結構阻擋以免到達第一通道區域。
在一些實施例中,本揭露係關於一種形成於一半導體基板上的整合晶片,包括一第一電晶體,其包括一第一閘極電極和具有第一通道長度L1的一第一通道區域;且一第二電晶體包括一第二閘極電極和具有第二通道長度L2的一第二通道區域。第一和第二通道區域已被摻雜物雜質摻雜以使得摻雜物濃度在第一和第二通道區域的邊緣高於第一和第二通道區域的中央。並且,摻雜物濃度於第一通道區域的邊緣高於第二通道區域的邊緣。
600‧‧‧方法
602-616‧‧‧步驟

Claims (10)

  1. 一種形成於半導體基板上的整合晶片之製造方法,包括:將一第一雜質類型的摻雜物雜質導入一基板的第一和第二電晶體區域中,其中該第一和第二電晶體區域分別包括第一和第二通道區域及第一和第二源極/汲極區域;凹陷該基板至該第一和第二電晶體區域之上;形成第一和第二含碳材料層於該第一和第二電晶體區域之上;形成第一和第二基板材料層於該第一和第二含碳材料層之上;形成第一和第二閘極介電質於該第一和第二基板材料層之上;形成第一和第二閘極結構於該第一和第二通道區域中的該第一和第二閘極介電質之上,其中該第一閘極結構被一第一水平間隔(s1)自一第三閘極結構隔離,其中該第二閘極結構被一第二水平間隔(s2)自一第四閘極結構隔離,且其中s2大於s1;以一第一角度實施一第一佈植以將更多該第一雜質類型的摻雜物雜質導入該基板的該第一和第二通道區域的邊緣中;以及以一第二垂直角度實施一第二佈植以導入一第二雜質類型的摻雜物雜質,其與該第一雜質類型相反,其中該第二角度大於一第一閾值以使得該第二佈植被該第三閘極結構阻擋以免到達該第一通道區域。
  2. 如申請專利範圍第1項所述之製造方法,其中該第二角度小於一第二閾值以使得該佈植不被該第四閘極結構阻擋而無法到達該第二通道區域,其中該第一到第四閘極結構具有垂直尺寸(h)。
  3. 如申請專利範圍第2項所述之製造方法,其中該第二閾值大約等於反正切(arctangent)(s2/h)。
  4. 如申請專利範圍第2項所述之製造方法,其中該第一閾值大約等於反正切(arctangent)(s1/h)。
  5. 如申請專利範圍第1項所述之製造方法,其中該第一雜質類型的該摻雜物雜質包括硼、碳、銦(indium)、或前述之組合。
  6. 如申請專利範圍第1項所述之製造方法,其中該第二雜質類型的該摻雜物雜質包括磷、銻、砷、或前述之組合。
  7. 如申請專利範圍第1項所述之製造方法,尚包括:實施一第三佈植以將第一額外摻雜物雜質導入該第一和第二通道區域中,其中該第三佈植提高該第一通道區域中的源極-至-汲極的電流控制,但增加該第二通道區域中的一閾值電壓一△(delta)值;以及以該第二垂直角度實施一第四佈植以將第二額外摻雜物雜質導入該第二通道區域中,以該第三閘極結構阻擋該第二額外摻雜物雜質以免到達該第一通道區域,其中該第四佈植降低該第二通道區域中的該閾值電壓約該△(delta)值。
  8. 一種形成於一半導體基板上的整合晶片,包括:一第一電晶體,包括一第一閘極電極和具有第一通道長度 L1的一第一通道區域;一第二電晶體,包括一第二閘極電極和具有第二通道長度L2的一第二通道區域;其中該第一和第二通道區域已被摻雜物雜質摻雜以使得該第一和第二通道區域的一摻雜物濃度於該第一和第二通道區域的邊緣高於該第一和第二通道區域的中央;以及其中該摻雜物濃度於該第一通道區域的邊緣高於該第二通道區域的邊緣。
  9. 如申請專利範圍第8項所述之整合晶片,其中該半導體基板包括一碳化矽層,其位於一矽層之下。
  10. 如申請專利範圍第8項所述之整合晶片,其中該第一和第二閘極電極位於包括一高介電常數(high-k)介電質的第一和第二閘極介電質之上。
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