TWI522912B - 利用原生分散旗標架構仿真客戶集中旗標架構的方法 - Google Patents

利用原生分散旗標架構仿真客戶集中旗標架構的方法 Download PDF

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TWI522912B
TWI522912B TW103109493A TW103109493A TWI522912B TW I522912 B TWI522912 B TW I522912B TW 103109493 A TW103109493 A TW 103109493A TW 103109493 A TW103109493 A TW 103109493A TW I522912 B TWI522912 B TW I522912B
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摩翰麥德 艾伯戴爾拉
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軟體機器公司
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858—Result writeback, i.e. updating the architectural state or memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30094—Condition code generation, e.g. Carry, Zero flag
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/3017—Runtime instruction translation, e.g. macros
    • G06F9/30174—Runtime instruction translation, e.g. macros for non-native instruction set, e.g. Javabyte, legacy code
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3814—Implementation provisions of instruction buffers, e.g. prefetch buffer; banks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G06F9/384—Register renaming
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G06F9/3863—Recovery, e.g. branch miss-prediction, exception handling using multiple copies of the architectural state, e.g. shadow registers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
    • G06F9/3893—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs

Description

利用原生分散旗標架構仿真客戶集中旗標架構的方法
本發明一般係關於數位電腦系統，尤其係關於一種包含一指令序列的指令選擇之系統及方法。
處理器必須處理互相依附或完全獨立任一者的多重任務。這種處理器之內部狀態通常由在程式執行之每個特定瞬間皆可能維持不同數值的寄存器構成。在程式執行之每個瞬間，該內部狀態圖像(state image)稱為該處理器之架構狀態。
碼執行切換成運行另一函數(例如另一執行緒、程序或程式)時，機器/處理器之狀態必須儲存使得新功能可利用該等內部寄存器以建立其新狀態。一旦該新功能終止，則其狀態可丟棄且先前脈絡(context)之狀態將會恢復並繼續執行。這種切換程序稱為脈絡切換(context switch)且通常包括數十或幾百個循環(cycles)，尤其具有採用大量寄存器(例如64、128、256)及/或無序執行的現代架構時。
在執行緒感知(thread aware)硬體架構中，對於硬體而言，為數量有限的硬體支援執行緒支援多重脈絡狀態很正常。在此例中，硬體為每個所支援執行緒皆複製所有的架構狀態元件。這排除執行新執行緒時， 對於脈絡切換的需要。然而，這仍有多個缺點，亦即為了硬體中所支援的每個額外執行緒而皆複本所有架構狀態元件(亦即寄存器)之面積、功率及複雜度。此外，若軟體執行緒之數量超過明確所支援的硬體執行緒之數量，則該脈絡切換仍必須進行。
由於在需求大量執行緒的精細粒度基礎上需要平行處理(parallelism)，因此這變得普遍。具有複本脈絡狀態硬體儲存體的硬體執行緒感知架構無助於非執行緒軟體碼，並僅為經執行緒軟體減縮脈絡切換之數量。然而，那些執行緒通常為粗粒平行處理而建構，並為初始化及同步化而導致沉重軟體負載，使得諸如函式呼叫及迴圈平行執行的細粒平行處理沒有有效的執行緒初始化/自動產生。這種所描述的負載伴隨著為了非明確(non-explicitly)/容易平行化(easily parallelized)/執行緒(threaded)軟體碼而使用最先進的編譯器或使用者平行化處理技術對這些碼之自動平行化處理之困難。
在一個具體實施例中，本發明實現為一種利用原生分散旗標架構仿真客戶集中旗標架構的方法。該方法包括使用全域前端接收輸入的指令序列；群組該等指令以排列指令區塊，其中該等指令區塊之每個皆包含兩個半區塊；排程該指令區塊之該等指令，以根據排程器執行；以及為了客戶指令執行之該仿真而利用分散旗標架構仿真集中旗標架構。
前述為總結，因此必然包含對細節之簡化、歸納及省略；所以，熟習此項技術者應可瞭解該總結僅為例示性且不欲以任何方式限制。如僅由諸申請專利範圍界定出的本發明之其他態樣、創造性特徵、與優勢，將會在以下所闡述的非限制性實施方式中變得顯而易見。
R0-R63‧‧‧寄存器
T0-T4‧‧‧寄存器樣板
20‧‧‧區塊
S1-S8‧‧‧來源
P1-P4‧‧‧連接埠
本發明在所附圖式之圖示中藉著範例而非限制進行例示，且其中同樣的參考號碼指稱類似的元件。
圖1顯示將指令群組於區塊中並藉著使用寄存器樣板追蹤指令之間依附的程序之概觀圖。
圖2根據本發明之一個具體實施例顯示寄存器觀點、來源觀點、與指令觀點之概觀圖。
圖3根據本發明之一個具體實施例所顯示的圖示例示示範寄存器樣板，以及來源觀點如何藉著來自寄存器樣板的資訊而填充。
圖4所顯示的圖示例示來源觀點內的廣播依附的第一具體實施例。在此具體實施例中，每行皆包含一指令區塊。
圖5所顯示的圖示例示來源觀點內的廣播依附的第二具體實施例。
圖6根據本發明之一個具體實施例所顯示的圖示例示為了始於提交指示器的配送而選擇就緒區塊，並廣播對應的連接埠分配。
圖7根據本發明之一個具體實施例顯示用於實現圖6中所描述選擇器陣列的加法器樹結構。
圖8更詳細顯示選擇器陣列加法器樹之示範邏輯。
圖9根據本發明之一個具體實施例顯示實現選擇器陣列的加法器樹之平行實作。
圖10根據本發明之一個具體實施例所顯示的示範圖示例示來自圖9的加法器X如何可藉著使用進位儲存加法器而實現。
圖11根據本發明顯示為了始於提交指示器進行排程並使用選擇器陣列加法器而遮蔽(masking)就緒位元的遮蔽具體實施例。
圖12根據本發明之一個具體實施例顯示寄存器觀點條目如何由寄存器樣板填充之概觀圖。
圖13根據本發明之一個具體實施例顯示用於減縮寄存器觀 點覆蓋區的第一具體實施例。
圖14根據本發明之一個具體實施例顯示用於減縮寄存器覆蓋區的第二具體實施例。
圖15根據本發明之一個具體實施例顯示快照之間的差量之示範格式。
圖16根據本發明之一個具體實施例顯示在指令區塊之配置上形成寄存器樣板快照的程序之圖示。
圖17根據本發明之一個具體實施例顯示在指令區塊之配置上形成寄存器樣板快照的程序之另一圖示。
圖18根據本發明之一個具體實施例顯示用於實現從先前寄存器樣板形成後續寄存器樣板之串列實作的硬體之概觀圖。
圖19根據本發明之一個具體實施例顯示用於實現從先前寄存器樣板形成後續寄存器樣板之平行實作的硬體之概觀圖。
圖20根據本發明之一個具體實施例顯示用於指令區塊型執行的硬體之概觀圖，以及其如何採用來源觀點、指令觀點、寄存器樣板、與寄存器觀點運作。
圖21根據本發明之一個具體實施例顯示組集(chunking)架構之範例。
圖22根據本發明之一個具體實施例顯示執行緒如何根據其區塊編號及執行緒識別碼(ID)進行配置之繪圖。
圖23根據本發明之一個具體實施例顯示排程器之實作，其使用為了管理多重執行緒執行而指向實體儲存位置的執行緒指示器映射。
圖24根據本發明之一個具體實施例顯示使用執行緒型指示器映射的排程器之另一實作。
圖25根據本發明之一個具體實施例顯示對執行緒的執行資源之動態日曆型配置之圖示。
圖26根據本發明之一個具體實施例圖示雙重配送程序。
圖27根據本發明之一個具體實施例圖示雙重配送暫態乘法積累。
圖28根據本發明之一個具體實施例圖示雙重配送架構上可見狀態乘法加法。
圖29根據本發明之一個具體實施例顯示用於群組執行單元程序上的執行的指令區塊之提取及排列之概觀圖。
圖30根據本發明之一個具體實施例顯示指令群組之示範圖示。在圖30具體實施例中，採用第三輔助運算顯示兩個指令。
圖31根據本發明之一個具體實施例顯示區塊堆疊內的半區塊配對如何映射於執行區塊單元上。
圖32根據本發明之一個具體實施例所顯示的圖示將中間區塊結果儲存體描繪為第一階寄存器檔案。
圖33根據本發明之一個具體實施例顯示奇數/偶數連接埠排程器。
圖34顯示圖33之更詳細的版本，其中顯示四個執行單元接收來自排程器陣列的結果，並將輸出寫入暫時寄存器檔案段。
圖35根據本發明之一個具體實施例所顯示的圖示描繪出客戶旗標架構仿真。
圖36根據本發明之一個具體實施例所顯示的圖示例示機器之前端、排程器及執行單元、與集中旗標寄存器。
圖37顯示如本發明之具體實施例所實現的集中旗標寄存器仿真程序之圖示。
圖38顯示在客戶設定下仿真集中旗標寄存器行為之程序3800之步驟流程圖。
雖然本發明已結合一個具體實施例進行描述，但本發明不欲限於文中所闡述的特定形式。相反地，係欲涵蓋如同可合理包括於如所附諸申請專利範圍所界定出的本發明之範疇內的這種替代例、修飾例、與相等物。
在以下實施方式中，諸如特定方法順序、結構、元件、與連接的眾多特定細節皆已闡述。然而應可理解這些及其他特定細節不需要利用於實作本發明之具體實施例。在其他狀況下，已習知的結構、元件、或連接皆已省略，或者並未特別詳細描述，以避免不必要地模糊本描述。
在本說明書內提及「一個具體實施例(one embodiment)」或「一具體實施例(an embodiment)」，係欲指示結合該具體實施例所描述的特定特徵、結構、或特性包括於本發明之至少一個具體實施例中。在本說明書內各處所出現的片語「在一個具體實施例中(in one embodiment)」不必皆指稱同一具體實施例，亦非互斥其他具體實施例的分離或替代性具體實施例。而且，描述可藉著一些具體實施例而非其他所呈現出的各種特徵。同樣地，描述對於一些具體實施例而非其他具體實施例可能為要求的各種要求。
所依循的實施方式之一些部分在電腦記憶體內資料位元上的運算之流程、步驟、邏輯區塊、處理、與其他符號代表方面進行說明。這些描述與指示為熟習資料處理領域技術者用來最有效傳達其工作實質給熟習此項技術其他者的方法。流程、電腦執行步驟、邏輯區塊、程序等在此一般設想成導致所需結果的步驟或指令之自相一致序列。這些步驟為需求實體量之實體操控者。通常，但並非必然，這些量具有的形式為電腦可讀取儲存媒體之電或磁信號，並能在電腦系統中儲存、傳送、結合、比較、與另行操控。主要由於通用之原因，有時已證明指稱這些信號為位元、數值、元件、符號、字元、用語、數字或此類的便利性。
然而，以此為前提，所有這些及類似用語將與適當實體量相關聯，並僅為施加於這些量的便利標記。除非如從以下詳述所顯而易見另外明確聲明，應可瞭解貫穿本發明利用諸如「處理(processing)」或「存取(accessing)」或「寫入(writing)」或「儲存(storing)」或「複製(replicating)」或此類用語的詳述指稱電腦系統或類似電子運算裝置之動作及程序，其將在該電腦系統的寄存器及記憶體及其他電腦可讀取媒體內表示為實體(電子)量的資料，操控及變換成在該電腦系統記憶體或寄存器或其他這種資訊儲存、傳輸或顯示裝置內同樣表示為實體量的其他資料。
圖1顯示將指令群組於區塊中且藉著使用寄存器樣板而追蹤該等指令之間的依附的程序之概觀圖。
圖1顯示具有標頭及本體(body)的指令區塊。該區塊從一群指令形成。該區塊包含一實體，其包覆(encapsulate)該指令群。在微處理器之本發明具體實施例中，摘要階層提高到區塊而非個別指令。區塊經處理進行配送，而非個別指令。每個區塊皆用區塊編號(block number)標記。機器的無序管理工作由此顯著簡化。一個關鍵特徵為找出藉以管理正在處理的更大量指令而不會顯著增加機器之管理負載的方法。
本發明之各具體實施例藉著實現指令區塊、寄存器樣板、與繼承向量而達成此目的。在圖1所顯示的區塊中，區塊之標頭列出且包覆區塊指令之所有來源及目標，以及那些來源的出處(例如來自哪些區塊)。該標頭包括該等目標，其更新該寄存器樣板。包括於該標頭中的該等來源將與儲存於該寄存器樣板中的該等區塊編號序連(concatenated)在一起。
經無序(out of order)處理的該些指令判定無序機器之管理複雜度。更多無序指令導致更高的複雜度。來源需要與處理器之無序配送視窗中的先前指令之目標比較。
如圖1所顯示，寄存器樣板對於從R0至R63的每個寄存器都有欄位。區塊將其各自的區塊編號寫入對應於區塊目標的寄存器樣板欄 位。每個區塊皆從該寄存器樣板讀取表示其寄存器來源的寄存器欄位。區塊拉回(retire)並將其目標寄存器內容寫入寄存器檔案時，其編號從寄存器樣板抹除。這意指那些寄存器可從寄存器檔案自身讀取為來源。
在本發明具體實施例中，寄存器樣板在每當區塊配置時機器之每個循環皆進行更新。隨著新的樣板更新產生，寄存器樣板之先前快照每個區塊一個儲存於陣列中(例如圖2所顯示的寄存器觀點)。此資訊留存直到對應的區塊拉回為止。這允許機器從未中預測(miss-predictions)恢復且非常迅速清除(例如藉著得到最後已知的依附狀態)。
在一個具體實施例中，儲存於寄存器觀點中的寄存器樣板可藉著僅儲存連續快照之間的差量(delta)(快照之間的增量改變)而壓縮(由此節省儲存空間)。以此方式機器得到縮小的寄存器觀點。進一步壓縮可藉著僅為具有分支指令的區塊儲存樣板而得到。
若除了分支未中預測之外還需要恢復點，則最初會在分支恢復點得到恢復，隨後狀態可由於配置指令(但並非將其執行)而重建直到機器求取到恢復點為止。
應注意到在一個具體實施例中，文中所使用的用語「寄存器樣板(register template)」與美國專利申請號13/428,440中所描述的用語「繼承向量(inheritance vector)」同義，於本文中將此專利申請案全部併入作為參照。
圖2根據本發明之一個具體實施例顯示寄存器觀點、來源觀點、與指令觀點之概觀圖。此圖示顯示排程器架構(例如具有來源觀點、指令觀點、寄存器觀點等)之一個具體實施例。藉著結合或分離以上所引述結構之一個或多個而達成相同功能的排程器架構之其他實作亦可能。
圖2圖示支援寄存器樣板之運算及機器狀態之保留的功能性實體。圖2之左側顯示寄存器樣板T0至T4，具有箭頭指示從一個寄存器樣板/繼承向量到下一個的資訊之繼承。寄存器觀點、來源觀點、與指令觀點每個皆包含資料結構，其用於儲存與指令區塊相關的資訊。圖2亦顯示具有標 頭的示範指令區塊，以及該指令區塊如何為機器之寄存器包括來源及目標兩者。有關區塊所指稱寄存器的資訊儲存於寄存器觀點資料結構中。有關區塊所指稱來源的資訊儲存於來源觀點資料結構中。有關區塊所指稱指令自身的資訊儲存於指令觀點資料結構中。該等寄存器樣板/繼承向量自身包含資料結構，其儲存區塊所指稱依附及繼承資訊。
圖3根據本發明之一個具體實施例所顯示的圖示例示示範寄存器樣板及如何由來自寄存器樣板的資訊填充來源觀點。
在本發明具體實施例中，應注意到來源觀點之目標為判定何時可配送(dispatch)特定區塊。區塊被配送時，會將其區塊編號廣播到所有剩餘區塊。對於其他區塊之來源的任何匹配(例如比較)皆會造成就緒位元(例如或者某其他類型之指示符)被設定。所有就緒位元皆設定(例如及閘(AND gate))時，區塊就緒進行配送。區塊依據其所依賴其他區塊之就緒度而被配送。
多個區塊就緒進行配送時，最早的區塊在較新的區塊前被選擇進行配送。舉例來說，在一個具體實施例中，最初找出的迴路(circuit)可用於依據接近於提交指示器及依據相對接近於該提交指示器的後續區塊找出最早的區塊(例如致力於每個區塊的就緒位元)。
仍參照圖3，在此範例中，正在檢查抵達區塊20時所形成的寄存器樣板快照。如上述，寄存器樣板具有用於R0至R63每個寄存器的欄位。區塊將其各自的區塊編號寫入對應於區塊目標的寄存器樣板欄位。每個區塊皆從寄存器樣板讀取代表其寄存器來源的寄存器欄位。第一編號為寫入寄存器的區塊，而第二編號為該區塊之目標編號。
舉例來說，區塊20抵達時，會讀取寄存器樣板之快照並在寄存器樣板中查找其自身的寄存器來源，以判定寫入其每個來源的最新區塊並根據其目標對先前寄存器樣板快照所進行的更新填充來源觀點。後續區塊將會用其自身的目標更新寄存器樣板。這顯示於圖3之左下方，其中區塊 20填充其來源：來源1、來源2、來源3、一直到來源8。
圖4所顯示的圖示例示來源觀點內的廣播依附的第一具體實施例。在此具體實施例中，每行皆包含一指令區塊。區塊被配置時，會在其來源曾經對那些區塊有依附的所有區塊行中進行標記(例如藉著寫入0)。任何其他區塊被配送時，其編號跨越與該區塊相關的確切欄進行廣播。應注意到寫入1為預設數值，指示對該區塊沒有依附。
區塊中的所有就緒位元皆就緒時，該區塊被配送且其編號廣播回到所有剩餘區塊。該區塊編號與儲存於其他區塊之來源中的所有編號比較。若有匹配，則設定用於該來源的就緒位元。舉例來說，若廣播於來源1上的區塊編號等於11，則將會設定用於區塊20之來源1的就緒位元。
圖5所顯示的圖示例示來源觀點內的廣播依附的第二具體實施例。此具體實施例由來源組織，而非由區塊組織。這藉著跨越來源觀點資料結構的來源S1至S8而顯示。以類似於以上圖4中所描述的方式，在圖5具體實施例中，區塊中的所有就緒位元皆就緒時，該區塊被配送且其編號廣播回到所有剩餘區塊。該區塊編號與儲存於其他區塊之來源中的所有編號比較。若有匹配，則設定用於該來源的就緒位元。舉例來說，若廣播於來源1上的區塊編號等於11，則將會設定用於區塊20之來源1的就緒位元。
圖5具體實施例亦顯示比較為何僅在提交指示器和配置指示器之間的區塊上啟動。所有其他區塊皆無效。
圖6根據本發明之一個具體實施例所顯示的圖示例示為了始於提交指示器的配送而選擇就緒區塊，並廣播對應的連接埠分配。來源觀點資料結構顯示於圖6之左側。指令觀點資料結構顯示於圖6之右側。選擇器陣列顯示於來源觀點和指令觀點之間。在此具體實施例中，選擇器陣列經由四個配送連接埠P1至P4每個循環配送四個區塊。
如上述，為從環繞包覆(wrapping around)的提交指示器到配置指示器的配送而選擇區塊(例如試著實踐最初配送較早的區塊)。選擇器陣 列用於找出始於提交指示器的最初四個就緒區塊。所需為配送最早的就緒區塊。在一個具體實施例中，選擇器陣列可藉著使用加法器樹結構而實現。這將會在以下的圖7中進行描述。
圖6亦顯示選擇器陣列如何耦接於通過指令觀點中的條目的四個連接埠之每個。在此具體實施例中，連接埠耦接為連接埠啟動，並啟動四個連接埠之一啟用，且為該指令觀點條目向下通過到配送連接埠及執行單元上。此外，如上述，經配送區塊透過來源觀點廣播回去。用於配送的選擇區塊之區塊編號廣播回去(最多四個)。這顯示於圖6之最右側。
圖7根據本發明之一個具體實施例顯示用於實現圖6中所描述選擇器陣列的加法器樹(adder tree)結構。所描繪出的加法器樹實現選擇器陣列之功能。加法器樹撿出最初四個就緒區塊，並將其裝入用於配送的四個可用連接埠(例如讀取連接埠1至讀取連接埠4)。未使用仲裁(arbitration)。 用於具體啟動特定連接埠的實際邏輯明確顯示於條目編號1中。為了清楚表示，該邏輯並未具體顯示於其他條目中。以此方式，圖7顯示如何實現直接選擇用於區塊配送的每個特定連接埠之一個特定具體實施例。然而或者應注意到，可實現使用優先編碼器的具體實施例。
圖8更詳細顯示選擇器陣列加法器樹之示範邏輯。在圖8具體實施例中，為範圍超過位元(range exceed bit)顯示邏輯。範圍超過位元確保將會選擇不超過四個區塊進行配送，若第五區塊就緒且最初四個區塊亦就緒，則範圍超過位元不會允許配送第五區塊。應注意到在串列實作中，總位元S0至S3皆用於啟動配送連接埠以及傳遞到下一個加法器階段。
圖9根據本發明之一個具體實施例顯示實現選擇器陣列的加法器樹之平行實作。平行實作並未將總和從每個加法器轉發到下一個。在平行實作中，每個加法器皆使用多重輸入加法實作直接使用所有其必要的輸入，諸如多輸入進位儲存加法器樹。舉例來說，加法器「X」加總先前的所有輸入。若為了執行更快速的運算次數(例如單一循環)，較佳地可採用此 平行實作。
圖10根據本發明之一個具體實施例所顯示的示範圖示例示來自圖9的加法器X如何可藉著使用進位儲存加法器而實現。圖10顯示可在單一循環中加入32個輸入的結構。該結構使用4×2進位儲存加法器組成。
圖11根據本發明顯示為了始於提交指示器進行排程並使用選擇器陣列加法器而遮蔽就緒位元的遮蔽具體實施例。在此實作中，選擇器陣列加法器正試著選擇最初四個就緒區塊，藉以始於可能環繞包覆的提交指示器到配置指示器進行配送。在此實作中，使用多輸入平行加法器。此外，在此實作中，利用這些循環緩衝之來源。
圖11顯示就緒位元如何與兩個遮罩(masks)之每個(個別或分離)皆一起ANDed，並平行施行於兩個加法器樹。最初四個藉著使用兩個加法器樹並與四個之臨界值比較而選擇。「X」標記表示「從用於該加法器樹的選擇陣列排除(exclude from the selection array for that adder tree)」，因此「X」數值為零。另一方面「Y」標記表示「確實包括於用於該加法器樹的選擇陣列中(do include in the selection array for that adder tree)」，因此「Y」數值為一。
圖12根據本發明之一個具體實施例顯示寄存器觀點條目(entries)如何由寄存器樣板填充(populate)之概觀圖。
如上述，寄存器觀點條目由寄存器樣板填充。寄存器觀點序列儲存用於每個區塊的寄存器樣板之快照。猜測無效(例如分支未中預測)時，寄存器觀點在無效猜測點之前有最新的有效快照。機器可藉著讀取該寄存器觀點條目並將其載入寄存器樣板之基底而將其狀態回復到最後的有效快照。寄存器觀點之每個條目皆會顯示所有的寄存器繼承狀態。舉例來說，在圖12具體實施例中，若用於區塊F的寄存器觀點無效，則機器狀態可回復到稍早最後的有效寄存器樣板快照。
圖13根據本發明之一個具體實施例顯示用於減縮寄存器觀 點覆蓋區的第一具體實施例。儲存寄存器觀點條目所需要的記憶體量可藉著僅儲存包含分支指令的那些寄存器觀點樣板快照而減縮。發生例外情形(例如猜測無效、分支未中預測等)時，最後的有效快照可從發生於例外情形之前的分支指令進行重建。為了建立最後的有效快照，從在例外情形之前向下到例外情形的分支提取指令。該等指令經提取但並未執行。如圖13中所顯示，僅包括分支指令的那些快照儲存於減縮寄存器觀點中。這顯著減縮儲存寄存器樣板快照所需要的記憶體量。
圖14根據本發明之一個具體實施例顯示用於減縮寄存器覆蓋區的第二具體實施例。儲存寄存器觀點條目所需要的記憶體量可藉著僅儲存快照之序列子集(例如每四個快照一個)而減縮。連續快照之間的改變可使用與完整連續快照比較更小的記憶體量儲存為偏離原始快照的「差量(delta)」。發生例外情形(例如猜測無效、分支未中預測等)時，最後的有效快照可從在例外情形之前所發生的原始快照重建。偏離在例外情形之前所發生的原始快照的「差量(delta)」及連續快照用於重建最後的有效快照。初始的原始狀態可積累差量以抵達所需求快照之狀態。
圖15根據本發明之一個具體實施例顯示快照之間的差量之示範格式。圖15顯示原始快照及兩個差量。在一個差量中，R5及R6為B3正進行更新的唯二寄存器。條目之其餘部分並未改變。在另一差量中，R1及R7為B2正進行更新的唯二寄存器。條目之其餘部分並未改變。
圖16根據本發明之一個具體實施例顯示在指令區塊之配置上形成寄存器樣板快照的程序之圖示。在此具體實施例中，圖16之左側顯示兩個解多工器(de-multiplexers)，而圖16之上方為快照寄存器樣板。圖16顯示用於從先前寄存器樣板(例如串列實作)形成後續寄存器樣板的圖示。
此串列實作顯示寄存器樣板快照如何在指令區塊之配置上方形成。那些快照用來擷取用於依附追蹤(例如圖1至圖4中所描述)以及更新用於處理未中預測/例外情形的寄存器觀點(例如圖12至圖15中所描述)的最 新寄存器架構狀態更新。
解多工器藉著選擇傳遞哪個輸入來源而起作用。舉例來說，寄存器R2將會在第二輸出解多工為1，而R8將會在第七輸出解多工為1等。
圖17根據本發明之一個具體實施例顯示在指令區塊之配置上形成寄存器樣板快照的程序之另一圖示。圖17具體實施例亦顯示從先前寄存器樣板形成後續寄存器樣板。圖17具體實施例亦顯示寄存器樣板區塊繼承之範例。此圖示顯示寄存器樣板如何從經配置的區塊編號進行更新之範例。舉例來說，區塊Bf更新R2、R8、與R10。Bg更新R1及R9。虛線箭頭指示數值從先前快照繼承。此程序向下一直進行到區塊Bi。因此，舉例來說，由於沒有快照更新寄存器R7，故原始數值Bb將會向下一直傳遞。
圖18根據本發明之一個具體實施例顯示用於實現從先前寄存器樣板形成後續寄存器樣板之串列實作的硬體之概觀圖。解多工器用於控制一連串兩個輸入多工器，其具有兩個區塊編號將會向下傳遞到下一個階段。可為來自先前階段的區塊編號或現有區塊編號任一者。
圖19根據本發明之一個具體實施例顯示用於實現從先前寄存器樣板形成後續寄存器樣板之平行實作的硬體之概觀圖。此平行實作使用特殊的編碼多工器控制，藉以從先前寄存器樣板形成後續寄存器樣板。
圖20根據本發明之一個具體實施例顯示用於指令區塊型執行的硬體之概觀圖，以及其如何採用來源觀點、指令觀點、寄存器樣板、與寄存器觀點運作。
在此實施例中，配送器中的配置器排程器接收機器前端所提取的指令。這些指令以先前我們描述過的方式通過區塊排列。如先前所描述，該等區塊產生寄存器樣板且這些寄存器樣板用於填充寄存器觀點。從來源觀點來看，該等來源傳送到寄存器檔案階層，並有廣播以上述方式回到來源觀點。指令觀點將指令傳送到執行單元。由於該等指令所需要的該等來源來自寄存器檔案階層，因此該等指令由執行單元執行。這些經執行 的指令隨後從執行單元傳送出來並回到寄存器檔案階層中。
圖21根據本發明之一個具體實施例顯示組集(chunking)架構之範例。組集之重要性在於其藉著使用所顯示的四個多工器而將進入每個排程器條目的寫入連接埠之數量皆從四減縮成一，同時仍密集堆積所有條目而未形成磁泡(bubbles)。
組集之重要性可由以下範例看出(例如注意到在每個循環中的區塊之配置皆始於上方位置，在此例中為B0)。假設在循環1中，三個指令區塊即將配置到排程器條目(例如這三個區塊將會占用排程器中的最初三個條目)。在下一個循環(例如循環2)中，另兩個指令區塊即將進行配置。為了避免在排程器陣列條目中形成磁泡(bubble)，該等排程器陣列條目必須支援四個寫入連接埠而建立。這在功率消耗、時序、面積、與此類方面代價很大。以上的組集結構藉著在配置到陣列之前先使用多工結構而將所有排程器陣列皆簡化成僅有一個寫入連接埠。在以上的範例中，在循環2中的B0將會由最後的多工器選擇，而在循環2中的B1將會由第一多工器選擇(例如從左到右進行)。
以此方式，條目組集之每個皆僅需要每個條目一個寫入連接埠及每個條目四個讀取連接埠。在成本上有折衷，因為必須實現多工器，然而由於可能有非常多個條目，因此該成本多次從不必實現每個條目皆四個寫入連接埠的節省而補足。
圖21亦顯示中間配置緩衝。若排程器陣列無法接受發送來的所有組集，則其可暫時儲存於中間配置緩衝中。排程器陣列有可用空間時，該等組集將會從中間配置緩衝傳送到排程器陣列。
圖22根據本發明之一個具體實施例顯示執行緒如何根據其區塊編號及執行緒ID進行配置之繪圖。區塊如上述經由組集實作配置到排程器陣列。該等執行緒區塊之每個皆使用區塊編號在其自身之間維持序列順序。來自不同執行緒的區塊可交錯(例如用於執行緒Th1的區塊和用於執 行緒Th2的區塊在排程器陣列中交錯)。以此方式，在排程器陣列內呈現出來自不同執行緒的區塊。
圖23根據本發明之一個具體實施例顯示排程器之實作，其使用為了管理多重執行緒執行而指向實體儲存位置的執行緒指示器映射。在此具體實施例中，執行緒之管理透過執行緒映射之控制而實現。舉例來說，圖23在此顯示執行緒1映射及執行緒2映射。該等映射追蹤個別執行緒之區塊之位置。在映射中的條目配置到屬於該執行緒的區塊。在此實作中，每個執行緒皆有為兩者執行緒計數的配置計數器。整體計數不可超過N除以2(例如超過可用空間)。為了在來自池的總條目之配置上實現公平性，該等配置計數器有可調整的臨界值。配置計數器可避免一個執行緒使用所有可用空間。
圖24根據本發明之一個具體實施例顯示使用執行緒型指示器映射的排程器之另一實作。圖24顯示提交指示器和配置指示器之間的關係。如所顯示，每個執行緒皆有提交指示器及配置指示器，箭頭顯示用於執行緒2的實境指示器如何可環繞包覆配置區塊B1及B2的實體儲存體，但其直到用於執行緒2的提交指示器向下移動才可配置區塊B9。這由執行緒2之提交指示器之位置及刪除線顯示。圖24之右側顯示逆時針環繞移動的區塊之配置和提交指示器之間的關係。
圖25根據本發明之一個具體實施例顯示對執行緒的執行資源之動態日曆型配置之圖示。公平性可依據每個執行緒之向前進展而皆使用配置計數器進行動態控制。若兩者執行緒皆正做出重大向前進展，則兩者配置計數器皆設定成相同臨界值(例如9)。然而，若一個執行緒做出緩慢向前進展，諸如受到L2快取未中或這種事件影響，則臨界值計數器之比率可依仍然正在做出重大向前進展的執行緒而調整。若一個執行緒拖延或中止(例如處於等待作業系統(OS)或輸入輸出(IO)回應的等待或自旋狀態下)，則該比率可完全調整到另一執行緒，其具有為了經中止的執行緒而保留以 發信號解除等待狀態的單一返回條目之例外情形。
在一個具體實施例中，程序採用50%：50%之比率開始。L2快取未中區塊22上的偵測時，指令管線之前端拖延任何進一步進入指令管線的提取或進入執行緒2區塊之排程器的配置。從排程器拉回執行緒2區塊時，將會使得那些條目可用於執行緒1配置直到達成新的執行緒配置動態比率。舉例來說，出於新近所拉回執行緒2區塊的3將會為了配置到執行緒1而非執行緒2而回到池中，使得執行緒1對執行緒2比率為75%：25%。
應注意到在指令管線前面的執行緒2區塊之拖延若沒有硬體機制可略過，則可能需要從指令管線前面清除那些區塊(例如由執行緒1區塊藉著經過受到拖延的執行緒2區塊)。
圖26根據本發明之一個具體實施例圖示雙重配送程序。多配送一般涵蓋多次配送區塊(其內有多個指令)，使得區塊的不同指令在每次通過執行單元時皆可執行。一個範例為位址計算指令之配送，接著為耗用所得到資料的後續配送。另一範例為浮點運算，其中第一部分執行為固定點運算，而第二部分執行以藉著進行捨入、旗標產生/計算、指數調整或此類而完成運算。區塊作為單一實體基元地(atomically)進行配置、提交、與拉回。
多配送之主要效益為避免將多個分離區塊配置到機器視窗中，由此使得機器視窗有效更大。更大的機器視窗意指有更多機會進行最佳化及重新排序。
看到圖26之左下方，描繪出指令區塊。此區塊由於來自快取/記憶體的負載位址計算和負載返回資料之間有延遲，因此無法在單一循環中進行配送。所以此區塊最初採用其保持為暫態的中間結果進行配送(其結果正即時輸送到第二配送而看不見架構狀態)。第一配送發送在LA之位址計算及配送中所使用的兩個分量1及2。第二配送發送在來自快取/記憶體的負載返回資料上的負載資料之執行部分的分量3及4。
看到圖26之右下方，描繪出浮點乘法積累運算。如乘法積累 圖示顯示，在硬體沒有足夠輸入來源頻寬以在單一相中配送運算的案例中，則使用雙重配送。第一配送如所顯示為固定點乘法。第二配送如所顯示為浮點加法捨入。執行這兩者經配送的指令時，其有效進行浮點乘法/積累。
圖27根據本發明之一個具體實施例圖示雙重配送暫態乘法積累(transient multiply-accumulate)。如圖27中所顯示，第一配送為整數32位元乘法，而第二配送為整數積累加法。在第一配送和第二配送之間進行溝通的狀態(乘法之結果)為暫態且架構上看不見。暫態儲存體在一個實施例中可保存一個以上乘法器之結果，並可對它們加標籤以識別對應的乘法積累對，由此允許以隨意方式(例如交錯等)配送的多個乘法積累對之混合。
應可知到其他指令可將此同一硬體用於其實作(例如浮點等)。
圖28根據本發明之一個具體實施例圖示雙重配送架構上可見狀態乘法加法。第一配送為單一精確度乘法，而第二配送為單一精確度加法。在此實作中，由於此儲存體為架構狀態寄存器，因此在第一配送和第二配送之間進行溝通的狀態資訊(例如乘法之結果)為架構上可見。
圖29根據本發明之一個具體實施例顯示用於群組執行單元程序上的執行的指令區塊之提取及排列之概觀圖。本發明之具體實施例利用藉以由硬體或動態轉換器/JIT將指令提取及排列為區塊的程序。區塊中的指令經組織使得區塊中稍早指令之結果饋送區塊中後續指令之來源。這由指令區塊中的虛線箭頭顯示。此特性致能區塊以在執行區塊之堆疊執行單元上有效執行。即使指令可平行執行，但諸如若其分享同一來源時(在此圖示中未明確顯示)，則亦可群組。
在硬體中排列區塊的一個替代例為在排列指令配對、三重、四重等的軟體中排列區塊(靜態或在運行時間)。
可美國專利8,327,115中找到指令群組功能之其他範例。
圖30根據本發明之一個具體實施例顯示指令群組之示範圖示。在圖30具體實施例中，採用第三輔助運算顯示兩個指令。圖31指令區塊之左側包含一上半區塊/一個狹槽(slot)及一下半區塊/一個狹槽。從上方往下的垂直箭頭指示進入區塊的來源，而從底部往下的垂直箭頭指示回到記憶體的目標。繼續從圖3之左側向右側看到，例示出可能的不同指令組合。在此實作中，每個半區塊可接收三個來源，並可傳遞兩個目標。OP1及OP2為正常運算。AuxiliaryOP為諸如邏輯值、移位、移動、記號擴充、分支等的輔助運算。將區塊分成兩個半部之效益為允許每個半部皆依據依附解析而自身獨立配送或作為一個區塊一起動態配送之效益(為了連接埠利用或因為資源限制任一者)，因此有較佳的執行時間利用，同時有對應於一個區塊的兩個半部允許機器對即將像是一個區塊進行管理的兩個半區塊之複雜度(亦即配置及拉回)取得摘要(abstract)。
圖31根據本發明之一個具體實施例顯示區塊堆疊內的半區塊配對如何映射於執行區塊單元上。如執行區塊中所顯示，每個執行區塊皆有兩個狹槽：狹槽1及狹槽2。目的為將區塊映射於執行單元上，使得第一半區塊在狹槽1上執行，而第二半區塊在狹槽2上執行。目的為若每個半區塊之指令群組皆不依賴另一半部，則允許兩個半區塊獨立配送。從上方進入執行區塊的配對箭頭為來源之兩個32位元字詞。離開執行區塊往下的配對箭頭為目標之兩個32位元字詞。從圖31之左側向右側，顯示能堆疊於執行區塊單元上的指令之不同示範組合。
圖31之上方總結半區塊之配對如何在完整區塊脈絡或任一半區塊脈絡中執行。執行區塊之每個皆有兩個狹槽/半區塊，且半區塊/執行狹槽之每一個皆執行單一、配對或三重群組的運算任一者。有四種類型之區塊執行類型。第一為平行半部(其允許每個半區塊一旦其自身來源就緒則皆獨立執行，但若兩者半部同時就緒，則兩個半區塊在一個執行單元上仍可作為一個區塊執行)。第二為基元(atomic)平行半部(其指稱由於兩個半部 之間沒有依附因此可平行執行的半區塊，但由於兩個半部之間的資源分享使得對於兩個半部較佳或必要在每個執行區塊中可用的資源限制內基元地一起執行，因此其被迫作為一個區塊一起執行)。第三類型為基元串列半部(其需求第一半部透過帶或不帶內部儲存體的暫態轉發將資料轉發到第二半部)。第四類型為序列半部(如在雙重配送中)，其中第二半部依賴第一半部並在第一半部以後的循環上進行配送，且透過類似於雙重配送案例為依附解析而追蹤的外部儲存體轉發資料。
圖32根據本發明之一個具體實施例所顯示的圖示將中間區塊結果儲存體描繪為第一階寄存器檔案。寄存器之每個群組皆表示指令區塊(表示兩個半區塊)，其中可藉著使用兩個32位元寄存器來支援一個64位元寄存器而支援32位元結果以及64位元結果兩者。每個區塊的儲存體皆假設虛擬區塊儲存體，其意指來自不同區塊的兩個半區塊可寫入同一虛擬區塊儲存體。兩個半區塊之經結合的結果儲存體構成一個虛擬區塊儲存體。
圖33根據本發明之一個具體實施例顯示奇數/偶數連接埠排程器。在此實施例中，結果儲存體為不對稱。一些結果儲存體為每半區塊三個64位元結果寄存器，而其他為每半區塊一個64位元結果寄存器，然而替代性實施例可每半區塊使用對稱儲存體，且此外亦可如圖32中所描述採用64位元及32位元分區。在這些具體實施例中，儲存體每半區塊分配，而非每個區塊。此實施例藉著將其作為奇數或偶數使用而減縮進行配送所需要的連接埠數量。
圖34顯示圖33之更詳細的版本，其中顯示四個執行單元接收來自排程器陣列的結果，並將輸出寫入暫時寄存器檔案段。連接埠以偶數及奇數間隔連接。排程陣列之左側顯示區塊編號，而右側顯示半區塊編號。
每個核心皆有偶數及奇數連接埠進入排程陣列，其中每個連接埠皆連接到奇數或偶數半區塊位置。在一個實作中，偶數連接埠及其對應的半區塊可常駐於與奇數連接埠不同的核心及其對應的半區塊中。在另 一實作中，奇數及偶數連接埠將會如此圖示中所顯示跨越多個不同的核心而分散。如美國專利申請號13/428,440中所描述，於本文中將此專利申請案全部併入為參照，核心可為實體核心或虛擬核心。
在某些類型之區塊中，區塊之一個半部可與區塊之另一個半部獨立配送。在其他類型之區塊中，區塊之兩者半部皆需要同時配送到同一執行區塊單元。在又其他類型之區塊中，區塊之兩個半部需要依序配送(第二半部在第一半部之後)。
圖35根據本發明之一個具體實施例所顯示的圖示描繪出客戶旗標架構仿真。圖35之左側顯示有五個旗標的集中旗標寄存器。圖35之右側顯示有分散旗標寄存器的分散旗標架構，其中旗標分散於寄存器自身之中。
在架構仿真期間，分散旗標架構有必要仿真集中客戶旗標架構之行為。分散旗標架構亦可藉著使用多個獨立的旗標寄存器而非與資料寄存器相關聯的旗標欄位而實現。舉例來說，資料寄存器可實現為R0至R15，而獨立的旗標寄存器可實現為F0至F3。那些旗標寄存器在此例中並未與資料寄存器直接相關聯。
圖36根據本發明之一個具體實施例所顯示的圖示例示機器之前端、排程器及執行單元、與集中旗標寄存器。在此實作中，前端依據其更新客戶指令旗標的方式分類輸入指令。在一個具體實施例中，客戶指令分類成四種原生指令類型：T1、T2、T3、與T4。T1-T4為指示每個客戶指令類型皆更新哪個旗標欄位的指令類型。客戶指令類型依據其類型更新不同的客戶指令旗標。舉例來說，邏輯客戶指令更新T1原生指令。
圖37顯示如本發明之具體實施例所實現的集中旗標寄存器仿真程序之圖示。圖37中的動作主包含一最新的更新類型表、一重新命名的表擴充、實體寄存器、與分散旗標寄存器。圖37現在由圖38之流程圖進行描述。
圖38顯示在客戶設定下仿真集中旗標寄存器行為之程序3800之步驟流程圖。
在步驟3801中，前端/動態轉換器(硬體或軟體)依據其更新客戶指令旗標的方式分類輸入指令。在一個具體實施例中，客戶指令分類成四種旗標架構類型：T1、T2、T3、與T4。T1-T4為指示每個客戶指令類型皆更新哪個旗標欄位的指令類型。客戶指令類型依據其類型更新不同的客戶旗標。舉例來說，邏輯客戶指令更新T1類型旗標、移位客戶指令更新T2類型旗標、算術客戶指令更新T3類型旗標、以及特殊客戶指令更新類型T4旗標。應注意到客戶指令可為架構式指令表示，而原生可為機器內部所執行者(例如微碼)。或者，客戶指令可為來自仿真架構(例如x86、java、ARM碼等)的指令。
在步驟3802中，那些指令類型更新其各自客戶旗標的順序記錄於最新的更新類型表資料結構中。在一個具體實施例中，此動作由機器之前端進行。
在步驟3803中，那些指令類型到達排程器(配置/重新命名階段之依順序部分)時，排程器分配對應於架構類型的隱含實體目標，並將該分配記錄於重新命名/映射表資料結構中。
以及在步驟3804中，後續客戶指令到達排程器中的配置/重新命名階段且該指令想要讀取客戶旗標欄位時，(a)機器判定需要存取哪些旗標架構類型以進行讀取；(b)若所有需要的旗標皆在同一最新的更新旗標類型中找出(例如由最新的更新類型表判定)，則讀取對應實體寄存器(例如映射於該最新的旗標類型者)以得到需要的旗標；(c)若所有需要的旗標無法皆在同一最新的更新旗標類型中找出，則需要從映射於個別最新的更新旗標類型的對應實體寄存器讀取每個旗標。
以及在步驟3805中，每個旗標皆從保存其最後所更新(如採用最新的更新旗標類型表所追蹤)最新數值的實體寄存器個別讀取。
應注意到若最新的更新類型包括另一種類型，則所有子集類型皆必須映射於母集(super set)類型之同一實體寄存器。
在拉回時，該目標旗標欄位與仿製的集中/客戶旗標架構寄存器合併。應注意到仿製由於原生架構利用分散旗標架構而非單一寄存器集中旗標架構的事實而進行。
更新某些旗標類型的指令之範例：CF、OF、SF、ZR-算術指令及負載/寫入旗標指令
SF、ZF、與有條件的CF-邏輯值及移位
SF、ZF-移動/負載、EXTR、一些乘法
ZF-POPCNT及STREX[P]
GE-SIMD指令？？？
讀取某些旗標的條件/預測之範例：0000 EQ等於Z=1
0001 NE不等於或無序Z=0
0010 CS b進位集，大於或等於或無序C=1
0011 CC c進位歸零，小於C=0
0100 MI減，負數，小於N=1
0101 PL加，正數或零，大於或等於、無序N=00110 VS溢出，無序V=1
0111 VC沒有溢出，非無序V=0
1000 HI無正負號大於、大於、無序C=1且Z=0
1001 LS無正負號低於或相同、小於或等於C=0或Z=1
1010 GE帶正負號大於或等於、大於或等於N=V
1011 LT帶正負號小於、小於、無序N！=V
1100 GT帶正負號大於、大於Z=0且N=V
1101 LE帶正負號小於或等於、小於或等於、無序Z=1或 N！=V
1110無(AL)、始終(無條件)、設定成任何數值的任何旗標
為了解釋之目的，前述描述已參照特定具體實施例進行描述。然而，以上所例示的詳述不欲為全面性或將本發明限制在所揭示的精確形式。許多修飾例與變化例鑑於以上講述為可能。各具體實施例為了最佳解釋本發明之原理及其實際應用而選擇並描述，以由此讓其他熟習此項技術者能採用可能適合所設想特定用途的各種修改來最佳利用本發明與各種具體實施例。
R0-R63‧‧‧寄存器

Claims (19)

  1. 一種利用原生分散旗標架構仿真客戶集中旗標架構的方法，包含：使用一全域前端接收一輸入的指令序列；群組該等指令以排列指令區塊，其中該等指令區塊之每個皆包含兩個半區塊；排程該指令區塊之該等指令，以根據一排程器執行；以及為了客戶指令執行之該仿真，而利用一分散旗標架構仿真一集中旗標架構。
  2. 如申請專利範圍第1項之方法，其中該分散旗標架構仿真一集中客戶旗標架構之該行為。
  3. 如申請專利範圍第1項之方法，其中一分散旗標架構可使用多重獨立的旗標寄存器實現。
  4. 如申請專利範圍第1項之方法，其中客戶指令分類成四種原生指令類型。
  5. 如申請專利範圍第1項之方法，其中客戶指令分類成四種原生指令類型，且客戶指令類型依據其類型更新不同的客戶指令旗標。
  6. 如申請專利範圍第1項之方法，其中一前端/動態轉換器依據於其中其更新客戶指令旗標的該方式分類輸入的指令。
  7. 一種具有當由電腦系統執行時，使得該電腦系統進行利用原生分散旗 標架構仿真客戶集中旗標架構的方法的電腦可讀取碼的非暫時性電腦可讀取媒體，包含：使用一全域前端接收一輸入的指令序列；群組該等指令以排列指令區塊，其中該等指令區塊之每個皆包含兩個半區塊；排程該指令區塊之該等指令，以根據一排程器執行；以及為了客戶指令執行之該仿真而利用一分散旗標架構仿真一集中旗標架構。
  8. 如申請專利範圍第7項之電腦可讀取媒體，其中該分散旗標架構仿真一集中客戶旗標架構之該行為。
  9. 如申請專利範圍第7項之電腦可讀取媒體，其中一分散旗標架構可使用多重獨立的旗標寄存器實現。
  10. 如申請專利範圍第7項之電腦可讀取媒體，其中客戶指令分類成四種原生指令類型。
  11. 如申請專利範圍第7項之電腦可讀取媒體，其中客戶指令分類成四種原生指令類型，且客戶指令類型依據其類型更新不同的客戶指令旗標。
  12. 如申請專利範圍第7項之電腦可讀取媒體，其中一前端/動態轉換器依據於其中其更新客戶指令旗標的該方式分類輸入的指令。
  13. 一種具有耦接於記憶體的處理器的電腦系統，該記憶體具有當由該電腦系統執行時，使得該電腦系統實現利用原生分散旗標架構仿真客戶 集中旗標架構的方法的電腦可讀取碼，包含：使用一全域前端接收一輸入的指令序列；群組該等指令以排列指令區塊，其中該等指令區塊之每個皆包含兩個半區塊；排程該指令區塊之該等指令，以根據一排程器執行；以及為了客戶指令執行之該仿真而利用一分散旗標架構仿真一集中旗標架構。
  14. 如申請專利範圍第13項之電腦系統，其中該分散旗標架構仿真一集中客戶旗標架構之該行為。
  15. 如申請專利範圍第13項之電腦系統，其中一分散旗標架構可使用多重獨立的旗標寄存器實現。
  16. 如申請專利範圍第13項之電腦系統，其中客戶指令分類成四種原生指令類型。
  17. 如申請專利範圍第13項之電腦系統，其中客戶指令分類成四種原生指令類型，且客戶指令類型依據其類型更新不同的客戶指令旗標。
  18. 如申請專利範圍第13項之電腦系統，其中一前端/動態轉換器依據於其中其更新客戶指令旗標的該方式分類輸入的指令。
  19. 一種執行區塊及半區塊之雙重配送的方法，包含：使用一全域前端接收一輸入的指令序列；群組該等指令以排列指令區塊，其中該等指令區塊之每個皆包含兩 個半區塊；排程該指令區塊之該等指令，以根據一排程器執行；以及為了一執行單元上的執行而進行該等兩個半區塊之一雙重配送。
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