TWI514943B - 微電子電路圖案化的方法 - Google Patents

微電子電路圖案化的方法 Download PDF

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TWI514943B
TWI514943B TW098134625A TW98134625A TWI514943B TW I514943 B TWI514943 B TW I514943B TW 098134625 A TW098134625 A TW 098134625A TW 98134625 A TW98134625 A TW 98134625A TW I514943 B TWI514943 B TW I514943B
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necking
region
area
main wiring
plating
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John Guzek
Yonggang Li
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Intel Corp
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Description

微電子電路圖案化的方法
本發明之實施例係大致有關積體電路封裝基板之領域，尤係有關使用混合雷射投射圖案化(Laser Projection Patterning；簡稱LPP)及半加成圖案化(Semi-Additive Patterning；簡稱SAP)之相同層微電子電路圖案化。
積體電路裝置的尺寸及間距之減小需要積體電路封裝基板製造的進展。將基板圖案化時使用雷射已是更為常見。不利之處在於：將雷射投射圖案化用來使基板層圖案化之成本經常比半加成圖案化之成本高出許多。
 【發明內容及實施方式】
在下文的說明中，為了便於解說，述及了許多特定細節，以便提供對本發明的徹底了解。然而，熟悉此項技術者應可了解：可在沒有這些特定細節的情形下實施本發明之各實施例。在其他的情形中，係以方塊圖之形式示出一些結構及裝置，以避免模糊了本發明。
在本說明書中提及“一個實施例”或“一實施例”時，意指參照該實施例而述及的一特定特徵、結構、或特性被包含在本發明的至少一實施例中。因此，在本說明書的各處中出現詞語“在一個實施例中”或“在一實施例中”時，不必然都參照到相同的實施例。此外，可在一或多個實施例中以任何適當的方式合併該等特定特徵、結構、或特性。
第1圖是根據本發明的一範例實施例的一封裝基板表面之一俯視圖。根據所示範例實施例，封裝基板100包含一或多個頸縮區102、主佈線區104、晶粒置放區106、以及信號走線108。
頸縮區102代表基板100的表面上的一區域，在該區域中，諸如被佈線的信號走線108之信號自佔用晶粒置放區106的一積體電路晶粒離開。在一個實施例中，信號走線108是自該積體電路晶粒的外凸塊(bump)佈線之輸入/輸出(Input/Output；簡稱I/O)信號。頸縮區102通常有比主佈線區104高的密度。在一個實施例中，頸縮區102包含大約9微米的線寬以及大約12微米的間隔。在一個實施例中，主佈線區104包含大於大約14微米的線寬以及大於大約14微米的間隔。在一個實施例中，信號走線108具有頸縮區102內的幾毫米之長度。如圖所示，頸縮區102稍大於晶粒置放區106。
如將於後文的實施例中說明的，相同層微電子電路圖案化可將雷射投射圖案化(LPP)用於頸縮區102，並將半加成圖案化(SAP)用於主佈線區104。信號走線108無縫地(例如，連續的銅走線)跨越這兩區。
第2A-2J圖是根據本發明的一範例實施例而部分地形成的一積體電路封裝基板之一橫斷面圖。第2A圖示出在將被建構的介電材料202疊合在其中包含墊204的一核心或現有被建構層上然後將該介電材料預硬化之基板200。該等介電材料通常是基於聚合物且以諸如可自市場上購得的填充料及各種其他材料等的散佈之二氧化矽填充料填充。
第2B圖示出在鑽穿整個圖案的雷射通孔206及除膠渣(desmear)之後的基板200。該除膠渣製程包含下列步驟：使用諸如氫氧化鈉(sodium hydroxide)等的鹼性溶液使通孔206的壁膨脹，然後以諸如含過錳酸鹽(permanganate)的水溶液等的高還原性化學物蝕刻通孔206的壁。
第2C圖示出在施加LPP剝蝕(ablation)而在諸如頸縮區102等的頸縮區的介電材料202中形成空圖案208之後的基板200。該頸縮區通常是略大於該晶粒置放區，且包含用於I/O信號佈線及扇出(fan-out)之細線及間隔。
第2D圖示出在以無電電鍍(electroless plating)法鍍製銅晶種層(seed layer)再接續以電解電鍍(elctrolytic plating)法鍍製銅210至諸如5-20微米等的特定厚度之後的基板200。以介電材料上表面上之過度鍍製的銅212覆蓋該頸縮區。
第2E圖示出在使用諸如化學機械研磨(CMP)、機械研磨、化學蝕刻、或以上各項的組合等的方法中所選擇之一方法去除過度鍍製的銅212之後的基板200。在該步驟之後，完成了該頸縮區的圖案。
第2F圖示出在以無電電鍍法鍍製銅214及乾膜光阻(Dry Film Resist；簡稱DFR)216疊合之後的基板200。
第2G圖示出在以傳統的微影製程(曝光及顯影)將DFR 216圖案化之後的基板200。除了該頸縮區的外圍部分217之外，以DFR 216覆蓋被圖案化之該頸縮區。
第2H圖示出在以電解電鍍法鍍製銅218至諸如5-20微米等的特定厚度之後的基板200。在此種方式下，在該頸縮佈線區的外圍部分217之頂部鍍製了該主佈線區。
第2I圖示出在以諸如碳酸鈉(sodium carbonate)水溶液等的鹼性溶液剝除DFR 216之後的基板200。亦可使用有機類型的溶液。
第2J圖示出在執行化學蝕刻以便去除無電電鍍銅晶種層214以形成整個圖案之後的基板200。
在一個實施例中，封裝基板200在表面220上被耦合到諸如覆晶型矽晶粒的一積體電路晶粒。在另一實施例中，係以另一介電層疊合表面220，作為一後續建構製程的一部分。
第3A-3K圖是根據本發明的一範例實施例而部分地形成的一積體電路封裝基板之一橫斷面圖。第3A圖示出在將被建構的介電材料疊合在其中包含墊304的一核心或現有層上然後將該介電材料預硬化之基板300。該等介電材料通常是基於聚合物且以諸如可自市場上購得的填充料及各種其他材料等的散佈之二氧化矽填充料填充。
第3B圖示出在該頸縮區的介電表面307上製作的一介電突出部306之後的基板300。可選擇性地疊合一增添的介電層，或以對應於將要被形成的該突出部的一袋狀物壓印(imprinting)步驟1中被疊合的該介電層。
第3C圖示出在鑽穿整個圖案的雷射通孔308及除膠渣之後的基板300。該除膠渣製程包含下列步驟：使用諸如氫氧化鈉等的鹼性溶液使通孔308的壁膨脹，然後以諸如含過錳酸鹽的水溶液等的高還原性化學物蝕刻通孔308的壁。
第3D圖示出在施加LPP剝蝕而在頸縮區的突出部306內形成空圖案310之後的基板300。該頸縮區通常是略大於該晶粒置放區，且包含用於I/O信號佈線及扇出之細線及間隔。
第3E圖示出在整個圖案之上以無電電鍍法鍍製銅晶種層312之後的基板300。
第3F圖示出在整個圖案之上進行DFR 314疊合之後的基板300。
第3G圖示出在以傳統的微影製程(曝光及顯影)將DFR 314圖案化之後的基板300。在微影製程之後曝露出了頸縮區圖案310。界定了在該頸縮區外部的主佈線區圖案316。
第3H圖示出在以電解電鍍法鍍製318整個圖案至諸如5-20微米等的特定厚度之後的基板300。介電層的上表面上之過度鍍製的銅320覆蓋了該頸縮區。
第3I圖示出在使用諸如化學機械研磨(CMP)、機械研磨、化學蝕刻、或以上各項的組合等的方法中所選擇之一方法去除過度鍍製的銅320之後的基板300。在該步驟之後，完成了該頸縮區的圖案。
第3J圖示出在使用諸如碳酸鈉水溶液等的鹼性溶液剝除DFR 314之後的基板300。亦可使用有機類型的溶液。
第3K圖示出在執行化學蝕刻以便去除無電電鍍銅晶種層312以形成整個圖案之後的基板300。
在一個實施例中，封裝基板300在表面322上被耦合到諸如覆晶型矽晶粒的一積體電路晶粒。在另一實施例中，係以另一介電層疊合表面322，作為一後續建構製程的一部分。
在前文之說明中，為了便於解說，述及了許多特定細節，以便提供對本發明的徹底了解。然而，熟悉此項技術者應可了解：可在沒有這些特定細節的某些特定細節之情形下實施本發明。在其他的情形中，係以方塊圖之形式示出一些習知的結構及裝置。
係在許多方法的最基本形式下說明了該等方法，但是在不脫離本發明的基本範圍下，可將一些操作加入該等方法中之任何方法，或可自該等方法中之任何方法刪除一些操作，而且可將一些資訊加入所需訊息中之任何訊息，或自所需訊息中之任何訊息去掉一些資訊。在本發明的範圍及精神內，將預期有本發明觀念之任何數目的變形。就這一點而言，並非為了限制本發明，而只是為了例示本發明，而提供該等特定量施例。因此，並非由前文提供的該等特定例子決定本發明之範圍，而只是由申請專利範圍決定本發明之範圍。
100,200,300．．．封裝基板
102．．．頸縮區
104．．．主佈線區
106．．．晶粒置放區
108．．．信號走線
202,302．．．介電材料
204,304．．．墊
206,308．．．雷射通孔
208,310．．．空圖案
210,218,318．．．電解電鍍銅
212,320．．．過度鍍製的銅
214．．．無電電鍍銅
216,314．．．乾膜光阻
217．．．頸縮區的外圍部分
220,322．．．表面
307．．．介電表面
306．．．介電突出部
312．．．銅晶種層
316．．．主佈線區圖案
已參照各附圖而以舉例但非限制之方式說明了本發明，在該等附圖中，相似的代號表示類似的元件，其中：
第1圖是根據本發明的一範例實施例的一封裝基板表面之一俯視圖；
第2A-2J圖是根據本發明的一範例實施例而部分地形成的一積體電路封裝基板之一橫斷面圖；以及
第3A-3K圖是根據本發明的一範例實施例而部分地形成的一積體電路封裝基板之一橫斷面圖。
200．．．封裝基板
208．．．空圖案

Claims (7)

  1. 一種微電子電路圖案化的方法，包含：在一疊層基板表面上形成一介電突出部，該介電突出部包含一頸縮區及一主佈線區，該頸縮區包含會被置放於該介電突出部上的一晶粒的覆蓋區內的一區域，且該主佈線區連續連接該頸縮區，該主佈線區從該頸縮區向外延伸；以雷射投射圖案化(LPP)法僅僅剝蝕該頸縮區中的該介電突出部；以銅鍍製該主佈線區及該頸縮區；從該主佈線區及該頸縮區去除過度鍍製的銅；在該主佈線區及該頸縮區上實施無電銅電鍍；以乾膜光阻(DFR)將該介電突出部上之該主佈線區及該頸縮區圖案化；鍍製該主佈線區，使該頸縮區中的佈線密度大於該主佈線區中的佈線密度；以及去除該DFR。
  2. 如申請專利範圍第1項之方法，其中在一疊層基板表面上形成一介電突出部包含：選擇性地疊合一增添的介電層。
  3. 如申請專利範圍第1項之方法，其中在一疊層基板表面上形成一介電突出部包含：以對應於將要被形成的該突出部之一袋狀物壓印該基板表面。
  4. 如申請專利範圍第1項之方法，其中鍍製該主 佈線區及頸縮區包含：過度鍍製該頸縮區。
  5. 如申請專利範圍第4項之方法，進一步包含：去除該頸縮區的頂部上之該過度鍍製的銅。
  6. 如申請專利範圍第1項之方法，其中鍍製該主佈線區及頸縮區包含：以電解電鍍法鍍銅至大約5微米與大約20微米間之厚度。
  7. 如申請專利範圍第1項之方法，其中鍍製該主佈線區及頸縮區包含：在一相同的電解電鍍步驟中鍍製跨越該主佈線區及頸縮區之特徵。
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