TWI514513B - 準確移除可控基板製造三維積體電路裝置 - Google Patents

準確移除可控基板製造三維積體電路裝置 Download PDF

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TWI514513B
TWI514513B TW098120386A TW98120386A TWI514513B TW I514513 B TWI514513 B TW I514513B TW 098120386 A TW098120386 A TW 098120386A TW 98120386 A TW98120386 A TW 98120386A TW I514513 B TWI514513 B TW I514513B
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layer
wafer
active circuit
circuit layer
interface
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TW201017820A (en
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Mukta G Farooq
Robert Hannon
Subramanian S Iyer
Steven J Koester
Sampath Purushothaman
Roy R Yu
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Description

準確移除可控基板製造三維積體電路裝置
本發明一般有關積體電路的領域，尤其有關三維(3D)積體電路裝置的製造。
業界目前正積極研發三維(3D)積體電路裝置。3D積體電路裝置製造所面臨的一個問題是，通用基板薄化技術無法產生可控制厚度的最終基板，其厚度薄到足以實現具有合理縱橫比的高密度穿透矽介層。一項克服此問題的已知技術是利用埋藏氧化物層(BOX)作為蝕刻停止層。但是，此技術僅對絕緣體上矽(SOI)晶圓片有用。另外，即使是SOI晶圓片，此技術對於具有延伸於埋藏氧化物下方之結構(如嵌入式DRAM(e-DRAM)溝渠)的SOI電路也無法發揮作用。
另一項克服此問題的已知技術是利用雙埋藏氧化物層(雙BOX)結構。然而，此技術卻使製造成本大幅增加。另外，如同單埋藏氧化物層結構的解決方案，雙BOX技術也需要保護基板不受其他晶圓片的影響。需要此種保護的原因是，儘管SOI晶圓片用作蝕刻停止層，但其無法提供不同基板間的蝕刻選擇性。
又另一項克服此問題的已知技術是不使用蝕刻停止層而是執行「盲」薄化("blind" thinning)。但此技術無法有效地薄化晶圓片，因而在均勻性上有問題。另外，對於需要3D介層之高密度的積體電路，此技術還強制使用不能用銅填充的高縱橫比介層。事實上，介層必須使用鎢，其電阻率比銅高三倍。
在製造3D積體電路裝置時所面臨的另一問題是，為形成多層堆疊而堆疊三層或更多層導致產量降低。一項嘗試克服此問題的技術是透過接合至臨時處理晶圓片來堆疊層。但使用此種臨時處理晶圓片(如，玻璃晶圓片)將引起重疊變形，因而降低晶圓片間的對準重疊。也就是說，此技術在後續的微影步驟中無法實現高精確度的光學對準。沒有高精確度的光學對準，將降低介層密度且必須使用具有高寄生電容的大捕獲焊墊。另外，使用此接合至臨時處理晶圓片在堆疊晶圓片的方式上很沒有彈性。
另一嘗試克服此問題的技術是僅使用晶圓片的直接面對面連結。但此種直接面對面連結有問題，因為接下來在整個堆疊製程中，必須使用底部晶圓片(通常是邏輯晶圓片)作為處理晶圓片。儘管這在製造兩層堆疊時是可以接受的，但對於多層(即，三層或更多層)堆疊，這意味著邏輯晶圓片必須歷經許多接合及薄化步驟。這對於整個積體電路，包括在堆疊中常常是最昂貴晶圓片的邏輯晶圓片，增加了不幸失敗及損失的機率。
本發明之一具體實施例提供一種製造3D積體電路結構的方法。依據此方法提供一第一主動電路層晶圓片。第一主動電路層晶圓片包含為P-層所覆蓋的P+部分，且P-層包含主動電路。第一主動電路層晶圓片面朝下地接合至包含一第一佈線層的界面晶圓片，並接著相對於第一主動電路層晶圓片的P-層選擇性移除第一主動電路層晶圓片的P+部分。然後，製造一怖線層於P-層的背面。
本發明之另一具體實施例提供一種3D積體電路結構，其包含一界面晶圓片、包含具有主動電路之P-層的一第一主動電路層晶圓片，位於P-層背面的一第二佈線層、一第二主動電路層晶圓片，其包含為P-層所覆蓋的P+部分。界面晶圓片包含一第一佈線層，且第一主動電路層晶圓片面朝下地接合至界面晶圓片。第二主動電路層晶圓片的P-層包含主動電路，第二主動電路層晶圓片面朝下地接合至第二佈線層。
參考以下所述詳細說明，將可瞭解本發明的其他目的、特色、及優點。然而，應明白，「實施方式」及特定範例儘管代表本發明的較佳具體實施例，但僅是藉由解說的方式來提供，且當然可在不脫離本發明的情況下執行各種修改。
以下參考附圖詳細說明本發明的較佳具體實施例。
本發明的具體實施例利用P+/P-基板以在三維(3D)積體電路裝置製造期間準確可控地移除基板。P+/P-基板為具有一P-頂部主動層的一P+晶圓片。在一具體實施例中，P-頂部主動層係磊晶式地成長於P+晶圓片上且具有約5至20微米的厚度。P+/P-基板之P+晶圓片及P-頂部主動層使可控基板的移除降到非常薄的層。因此，本發明克服習知三維積體電路之基板薄化技術所提供之可控基板的缺失。本發明之基板移除的可控度可達成能填充銅的低的縱橫比介層，因此可呈現低電阻抗。此外，本發明之實施例也提供具成本效益且堅固的通用蝕刻終止層。
圖1至11根據本發明之一具體實施例，圖解製造三維積體電路裝置的製程。如圖1所示，製程始於界面晶圓片100，其為完成積體電路中的堆疊主動電路層及封裝之間的界面。尤其，界面晶圓片100的暴露表面將承載完成積體電路中的C4(控制破裂晶片連接)焊料凸塊。這些C4(或倒裝晶片)焊料凸塊係用於將積體電路附著至封裝(如，樹脂或陶瓷模組)。界面晶圓片100是一種基板，其由在後續基板移除步驟所用的蝕刻劑中為不可溶的材料製成(即，在相對於P-層選擇性蝕刻P+層的蝕刻劑中為不可溶的材料)。
在此具體實施例中，界面晶圓片並非由P+基板形成，所以其不會受到移除堆疊中主動電路層之晶圓片基板之蝕刻的影響。界面晶圓片100是一種矽基板，其具有間距同於封裝的穿透矽介層102。另外，在此具體實施例中，以鎢金屬填充穿透矽介層。在進一步具體實施例中，以其他冶金，如銅，填充穿透矽介層。界面晶圓片100的穿透矽介層不需要以堆疊中其他層之穿透矽介層的相同材料製成。界面晶圓片100還具有佈線層104，其分配信號及功率至積體電路的堆疊層。在此具體實施例中，界面晶圓片100對紅外線輻射為透通。
此外，提供第一主動電路層晶圓片200。第一主動電路層晶圓片200以P+/P-矽基板形成，其為具有P-頂部主動電路層204的P+晶圓片202。在此具體實施例中，P-頂部主動電路層204磊晶生長於P+晶圓片上且具有厚度介於約5及20微米。另外，在此具體實施例中，P+晶圓片為硼摻雜晶圓片，其摻雜濃度介於約1×1018 cm-3 至3×1020 cm-3 ，及P-磊晶層具有摻雜濃度小於約1×1018 cm-3 。在進一步具體實施例中，P-磊晶層未經特意摻雜，或為N型摻雜，其濃度小於約1×1013 cm-3 。
將穿透矽介層206蝕刻至P-頂部主動電路層204中，其末端接近P+晶圓片202。在進一步具體實施例中，介層206穿過P+晶圓片202的表面。主動電路(即，主動組件，如電晶體)及一或多個佈線層208形成於第一主動電路層晶圓片200的頂面。
接下來，如圖2所示，第一主動電路層晶圓片200面朝下地對準界面晶圓片100。比起晶圓片之一利用臨時處理晶圓片(如，玻璃的臨時處理晶圓片)的情況，此使用兩個矽晶圓片的面對面對準可以有更高的精確度對準。第一主動電路層晶圓片200接合至界面晶圓片100。在此具體實施例中，利用銅-銅或是銅-銅及黏著接合(如，使用高分子黏合劑)的組合。在進一步具體實施例中，利用其他冶金(如銅合金或鎳-金合金)。
然後選擇性移除第一主動電路層晶圓片200的P+層202，如圖3所示。在此具體實施例中，首先利用一系列非選擇性基板薄化製程(如，晶圓片研磨及拋光)，然後再利用濕式化學蝕刻相對於P-層204選擇性移除其餘P+層202。使用如HNA(氫氟酸/硝酸/乙酸)的選擇性蝕刻劑，執行第一主動電路層晶圓片200之P+層202的最後移除。由於界面晶圓片100的塊體在此選擇性蝕刻劑中為不可溶，製程十分穩當。此外，在此具體實施例中，界面晶圓片100以輕摻雜的N-或P-矽製成，以便執行紅外線(IR)對準。在其他具體實施例中，界面晶圓片100亦為P+矽基板。
此選擇性移除P+層實質上未影響到保留下來的P-磊晶層204、主動電路及佈線層104及208、或界面晶圓片100。因此，使用P+/P-基板可使P+層被選擇性移除，使得可控制地薄化晶圓至P-層的厚度，且其可以變得非常薄(如，約5-20微米厚)。
接下來，在此具體實施例中，執行回蝕(如，使用反應離子蝕刻)，以暴露P-層204中介層206的頂部部分。在其中介層206穿入P+層202的其他具體實施例中，不需要這種蝕刻，因為介層的頂部部分在選擇性移除P+層之後已經暴露。然後將具有絕緣及一或多個耦合至介層206的後段製程(BEOL)金屬層層的佈線層210圖案化至P-層204的背面，如圖4所示。在此具體實施例中，佈線層210的每一個金屬層層藉由以下方式形成：沈積介電層、蝕刻該介電層、及沈積金屬於蝕刻區域中。
接著重複這些步驟任意次數，以在界面晶圓片100上形成多層堆疊。例如，在所示具體實施例中，再重複這些步驟一次，以形成第二主動電路層。更明確地說，形成第二主動電路層晶圓片300，如圖5所示。第二主動電路層晶圓片300亦以P+/P-矽基板形成，其為具有P-頂部主動電路層304的P+晶圓片302。在此具體實施例中，P-頂部主動電路層304係磊晶生長且具有厚度介於約5及20微米。將穿透矽介層306蝕刻至P-頂部主動電路層304中，使其末端接近P+晶圓片302，及形成主動電路及一或多個佈線層308於第二主動電路層晶圓片300的頂面。
接下來，如圖6所示，使第二主動電路層晶圓片300面朝下地對準附著至界面晶圓片100之第一P-層204上的佈線層210。比起晶圓片之一利用臨時處理晶圓片(如，玻璃的臨時處理晶圓片)的情況，此使用兩個矽晶圓片的面對面對準可以有更高的精確度對準。使用銅-銅或是銅-銅及黏著接合的組合，將第二主動電路層晶圓片300接合至佈線層210。在進一步具體實施例中，利用其他冶金(如銅合金或鎳-金合金)。
然後選擇性移除第二主動電路層晶圓片300的P+層302，如圖7所示。在此具體實施例中，首先利用一系列非選擇性基板薄化製程(如，晶圓片研磨及拋光)，然後再利用化學蝕刻相對於第二主動電路層晶圓片300的P-層304選擇性移除第二主動電路層晶圓片300的其餘P+層302。此選擇性移除第二主動電路層晶圓片300的P+層302實質上未影響到保留下來的P-層204及304、主動電路及佈線層104、208、210、及308、或界面晶圓片100。因此，界面晶圓片100十分堅固，能夠應付移除用於形成多層堆疊之所有主動電路層晶圓片的P+層的多個基板移除蝕刻。
接著執行回蝕以暴露第二P-層304中介層306的頂部部分。然後將具有絕緣及一或多個耦合至介層306的BEOL金屬層層的佈線層310圖案化至第二P-層304的背面，如圖8所示。
以此方式將所要數量的主動電路層接合一起之後，形成附著至基底晶圓片800的結構，如圖9所示。此具體實施例的基底晶圓片800由塊體矽或SOI製成，且其頂部為具有絕緣及一或多個BEOL金屬層層的佈線層808。在此具體實施例中，基底晶圓片800沒有任何穿透矽介層。在一些具體實施例中，基底晶圓片包括主動電路(如，電晶體)及/或被動電路元件(如，電阻器及電容器)。界面晶圓片100及附著至界面晶圓片之主動電路層的堆疊面朝下地對準基底晶圓片。因此，由於這些元件在此具體實施例中已「翻轉」兩次，先前堆疊在界面晶圓片100上的所有主動電路層現在相對於基底晶圓片800為面向上方，如圖9中的箭頭所示。
接著將多層堆疊的頂部佈線層310接合至基底晶圓片800。在此具體實施例中，利用銅-銅或是銅-銅及黏著接合(如，使用高分子黏合劑)的組合。在進一步具體實施例中，利用其他冶金(如銅合金或鎳-金合金)。接著薄化界面晶圓片100。在此具體實施例中，以兩個步驟達成此薄化。第一，執行晶圓片研磨及拋光的組合，使界面晶圓片薄化至界面晶圓片100中的介層102上。然後，透過乾式蝕刻(如，使用反應離子蝕刻)，使界面晶圓片100進一步薄化，以形成暴露介層102之頂部部分的界面層101，如圖10所示。接著沈積背面介電層820於界面層101的背面上。
如圖11所示，接著拋光及/或蝕刻背面介電層820，及沈積接觸金屬層822於界面層101的介層102上。在此具體實施例中，沈積簡單的球限制金屬層於介層上，以便能夠沈積C4焊料凸塊。在其他具體實施例中，形成比較複雜的介電層及金屬層層。然後，沈積C4焊料凸塊825於接觸金屬層822上，以完成3D積體電路結構。在此具體實施例中，C4焊料凸塊的直徑大約為100μm及間距為200μm或以下。接著使用這些C4(或倒裝晶片)焊料凸塊將積體電路接合至封裝(如，樹脂或陶瓷模組)。
上述示範性製程僅是用來解說本發明的原理。只要改變界面晶圓片上堆疊之層的數量、類型及順序，即可產生許多不同的3D積體電路結構。例如，雖然上述示範性製程產生具有1+2+1堆疊(1基底晶圓片、2主動電路層、及1界面層)的結構，但只要重複上述主動電路層堆疊製程N次，即可形成具有1+N+1堆疊的結構。在1+N+1堆疊結構中，額外的主動電路層(每一個類似於由層210、204、及208形成的主動電路層)係堆疊在圖11之結構中第一主動電路層的層210及最後一個(第N個)主動電路層的層308之間(例如，見圖12)。
同樣地，僅執行主動電路層堆疊製程一次，可形成具有1+1+1堆疊的結構。在1+1+1堆疊結構中，第二主動電路層(由層310、304、及308所形成的主動電路層)不存在於圖11的結構中。因此，可按一致的方式使用本發明之堆疊多個主動電路層於基底晶圓片頂部上的製程，以在基底晶圓片上僅堆疊一主動電路層。
在進一步具體實施例中，使用邏輯晶圓片(即，含邏輯電路的晶圓片)作為基底晶圓片(即，包括邏輯電路的基底晶圓片)。例如，圖12根據本發明之一具體實施例，顯示具有邏輯晶圓片-主動電路層-界面層堆疊結構的3D積體電路結構。此示範性具體實施例具有堆疊在N個主動電路層(即記憶體層)頂部上的界面層，N個主動電路層又堆疊在邏輯晶圓片的頂部上。記憶體層可以是任何類型的記憶體，如SRAM記憶體、e-DRAM記憶體、或此二者之組合。邏輯晶圓片含有控制及/或邏輯電路，如記憶體控制器或處理器核心。在另一具體實施例中，將界面層及僅一個主動電路層(如，記憶體層)堆疊在邏輯晶圓片的頂部上。
此外，上述製程中所使用的一或多個晶圓片可以是絕緣體上矽(SOI)晶圓片。例如，圖13根據本發明之一具體實施例，顯示其中所有層均在SOI晶圓片上形成的3D積體電路結構。在替代性具體實施例中，基底晶圓片係SOI基板(如圖13)，而主動電路層及界面層的晶圓片係塊體矽晶圓片(如圖12)。在又另一具體實施例中，基底晶圓片係SOI基板(如圖13)，主動電路層的晶圓片包括SOI晶圓片(如圖13)及塊體矽晶圓片(如圖12)二者，及界面層的晶圓片係SOI或塊體矽晶圓片。
圖14根據本發明之一具體實施例，顯示在堆疊結構的界面層中具有電路元件的3D積體電路結構。在此具體實施例中，透過主動電路及/或被動電路元件的供應，界面層包括額外的功能性。例如，界面層可包括解耦電容器層，以穩定電壓柵。或者或此外，界面層可包括由主動電晶體以及如解耦電容器的被動元件所形成的電壓調節電路。
因此，本發明的具體實施例利用P+/P-基板製造三維(3D)積體電路裝置。此係準確可控地移除基板以降到非常薄的層。因此，本發明克服習知三維積體電路之基板薄化技術所提供之可控基板的缺失。此亦達成能填充銅的低的縱橫比介層，因此可呈現低電阻抗。此外，本發明之實施例也提供具成本效益且堅固的通用蝕刻終止層。
上述本發明之具體實施例係用來解說本發明原理。這些裝置的製程與習用的半導體製造方法相容，因而一般技術者可進行各種修改及調整。所有此類修改仍然屬於本發明的範疇之內。例如，上述各種層厚度、材料類型、沈積技術等並沒有限制的意思。
此外，本發明範例的一些特色可在未相應使用其他特色的情況下用來獲得好處。因此，應將上述說明視為只是本發明之原理、教示、範例及示範具體實施例的舉例說明，而非其限制。
應明白，這些具體實施例僅是此處創新方法之許多有利運用的範例。一般而言，本申請案說明書中所做陳述未必限制任何不同的主張發明。再者，某些陳述可能適用於一些發明特色但對於其他發明特色則不適用。一般而言，除非另有指明，否則在不失一般性的原則下，單一元件也可以指複數個元件，反之亦然。
上述電路為積體電路晶片設計的一部分。晶片設計在圖形電腦程式語言中建立並儲存於電腦儲存媒體(如磁碟、磁帶、實體硬碟、或虛擬硬碟，如在儲存存取網路中)。如果設計者並不製造晶片或用於製造晶片的光微影遮罩，則設計者以實體方式(如，藉由提供儲存設計之儲存媒體的複製)或以電子方式(如，透過網際網路)直接或間接地將所完成的設計傳送到此類實體。接著將儲存的設計轉換成製造光微影遮罩的適當格式(如，GDSII)，該等遮罩通常包括所論將在晶圓片上形成之晶片設計的多個複製。利用光微影遮罩界定晶圓片將要蝕刻或以其他方式處理的區域(及/或其上的層)。
上述方法可用於製造積體電路晶片。製造商可以原料晶圓片的形式(即作為具有多個未封裝晶片的單一晶圓片)、作為裸晶片、或以封裝形式銷售所產生的積體電路晶片。在封裝形式的情況中，晶片係安裝於單一晶片封裝中(諸如引線已固定於母板的塑膠載板、或其他更高階載板)或安裝於多晶片封裝中(諸如具有表面互連線或埋藏互連線之一或二者皆有的陶瓷載板)。在任何情況中，晶片接著將與其他晶片、分立電路元件、及/或其他信號處理裝置整合，作為(a)中間產品，諸如母板；或(b)終端產品的部分。終端產品可以是包括積體電路晶片的任何產品，其範圍涵蓋玩具及其他低階應用至具有顯示器、鍵盤、或其他輸入裝置、及中央處理器的進階電腦產品。
圖15顯示例如在半導體IC邏輯設計、模擬測試、配置及製造中使用之示範性設計流程900的方塊圖。設計流程900包括處理設計結構或裝置的製程及機制，以產生上述及圖1-14所示設計結構及/或裝置在邏輯上或在功能上的等效表示法。設計流程900所處理及/或產生的設計結構可在機器可讀傳輸或儲存媒體上編碼，其包括資料及/或指令：當在資料處理系統上執行或以其他方式處理時，在邏輯上、結構上、機械上或在功能上產生硬體組件、電路、裝置、或系統的等效表示。設計流程900可根據所設計的表示法類型而有所變化。例如，建立特定應用IC(ASIC)的設計流程900不同於設計標準組件的設計流程900，或不同於將設計體現成可程式陣列的設計流程900，可程式陣列例如AlteraInc.或xilinXInc.提供的可程式閘陣列(PGA)或場可程式閘陣列(FPGA)。
圖15圖解多個此類設計結構，其包括較佳是由設計程序910處理的輸入設計結構920。設計結構920可以是由設計程序910產生及處理的邏輯模擬設計結構，以產生硬體裝置之邏輯上等效的功能表示。設計結構920亦可包含或替代地包含資料及/或程式指令：當由設計程序910處理時，產生硬體裝置實體結構的功能表示。無論是代表功能及/或結構設計特色，均可使用如由核心開發者/設計者實施的電子電腦輔助設計(EGAD)產生設計結構920。當編碼於機器可讀資料傳輸、閘陣列或儲存媒體上時，可由設計程序910內的一或多個硬體及/或軟體模組存取及處理設計結構920，以模擬或在功能上表示電子組件、電路、電子或邏輯模組、設備、裝置、或系統，如圖1-14中所顯示的。因此，設計結構920可包含檔案或其他資料結構，包括人類及/或機器可讀原始碼、編譯結構、及電腦可執行碼結構，當由設計或模擬資料處理系統處理時，在功能上模擬或以其他方式表示硬體邏輯設計的電路或其他層級。此類資料結構可包括硬體描述語言(HDL)設計實體或其他資料結構，其符合及/或相容於低階HDL設計語言，如Verilog及VHDL，及/或相容於高階設計語言，如C或C++。
設計程序910較佳是採用及併入硬體及/或軟體模組，以便合成、轉譯、或以其他方式處理圖1-14中所示組件、電路、裝置、或邏輯結構之設計/模擬功能等效物，以產生線路連接表980，其可含有如設計結構920的設計結構。線路連接表980可包含例如編譯或以其他方式處理的資料結構，其表示線路、離散組件、邏輯閘、控制電路、I/O裝置、模型等的清單，線路連接表描述積體電路設計中與其他元件及電路的連接。線路連接表980可使用反覆程序合成，其中根據電路的設計規格及參數，將線路連接表980重新合成一或多次。如同本文所述的其他設計結構類型，可將線路連接表980記錄於機器可讀資料儲存媒體上或程式化於可程式閘陣列中。媒體可以是非揮發性儲存媒體，如磁碟機或光碟機、可程式閘陣列、小型快閃記憶體或其他快閃記憶體。此外，或替代地，媒體可以是系統或快取記憶體、緩衝器空間、或電氣或光學傳導裝置及工具，資料封包可經由網際網路或其他網路連接的合適構件在這些媒體上傳輸且在其間儲存。
設計程序910包括硬體及軟體模組，用於處理各種包括線路連接表980的輸入資料結構類型。此等資料結構類型例如可駐存在程式庫元件930內且包括一組常用元件、電路、及裝置，包括用於特定製造技術(如，不同的技術節點32nm、45nm、90nm等)的模型、配置及符號表示。資料結構類型另外包括設計規格940、特徵資料950、確認資料960、設計規則970、及測試資料檔案985，測試資料檔案包括輸入測試模式、輸出測試結果、及其他測試資訊。設計程序910另外包括例如標準機械設計程序，如應力分析、熱分析、機械事件模擬、製程模擬，用於如鑄造、模製、及模壓形成等作業。在不脫離本發明範疇及精神下，機械設計的一般技術者應明白可能之機械設計工具的範圍及設計程序910中所使用的應用程式。設計程序910亦可包括模組用於執行標準電路設計程序，諸如時序分析、確認、設計規則檢查、布局與布線作業等。
設計程序910採用及併入邏輯及實體設計工具，如HDL編譯器及模擬模型建立工具，以連同任何額外機械設計或資料(若適用)與所描繪支援資料結構的部分或全部一起處理設計結構920，以產生第二設計結構990。設計結構990以交換機械裝置及結構之資料所使用的資料格式(如，以IGES、DXF、Parasolid XT、JT、DRG、或任何其他儲存或呈現此機械設計結構之合適格式儲存的資訊)駐存於儲存媒體或可程式閘陣列。類似於設計結構920，設計結構990較佳是包含一或多個檔案、資料結構、或其他電腦編碼資料或指令，其駐存於傳輸或資料儲存媒體及在由ECAD系統處理時，產生圖1-14所示本發明之一或多個具體實施例的邏輯上或功能上等效的形式。在一具體實施例中，設計結構990包含編譯、可執行的HDL模擬模型，其在功能上模擬圖1-14所示的裝置。
設計結構990亦可採用積體電路之配置資料之交換所使用的資料格式及/或符號資料格式(如，以GDSII(GDS2)、GL1、OASIS、映射檔案、或任何其他儲存此設計資料結構之合適格式儲存的資訊)。設計結構990包含資訊如：符號資料、映射檔案、測試資料檔案、設計內容檔案、製造資料、配置參數、線路、金屬層級、介層、形狀、透過生產線布線的資料、及製造商或其他設計者/開發者需要的任何其他資料，以產生上述及圖1-14所示的裝置或結構。設計結構990接著進行至階段995，其中(例如)設計結構990：進行至試產(tape-out)、發表以進行製造、送至遮罩廠、送至另一設計廠、送回客戶等。
100．．．界面晶圓片
101．．．界面層
102、206、306．．．穿透矽介層
104、208、210、308、310、808．．．佈線層
200．．．第一主動電路層晶圓片
202、302．．．P＋晶圓片
204、304．．．P-頂部主動電路層
300．．．第二主動電路層晶圓片
800．．．基底晶圓片
820．．．介電層
822．．．接觸金屬層
825．．．C4銲料凸塊
圖1至11根據本發明之一具體實施例，為製造三維積體電路裝置之製程的橫截面圖；
圖12根據本發明之一具體實施例，顯示具有邏輯層-主動電路層-界面層堆疊結構的3D積體電路結構；
圖13根據本發明之一具體實施例，顯示其中所有層為SOI晶圓片的3D積體電路結構；
圖14根據本發明之一具體實施例，顯示在堆疊結構的界面層中具有電路元件的3D積體電路結構；及
圖15為半導體設計、製造、及/或測試中所用設計程序的流程圖。
101．．．界面層
102．．．穿透矽介層
104、208、210、308、310、808．．．佈線層
204、304．．．P-頂部主動電路層
800．．．基底晶圓片
820．．．介電層
822．．．接觸金屬層
825．．．C4銲料凸塊

Claims (19)

  1. 一種製造一3D積體電路的方法，該方法包含以下步驟：提供一界面晶圓片，該界面晶圓片包括一第一佈線層及穿透矽介層；提供一第一主動電路層晶圓片，該第一主動電路層晶圓片包括一P-層所覆蓋的一P+層，該第一主動電路層晶圓片之P-層包括主動電路及穿透矽介層；製造一第二佈線層於該第一主動電路層晶圓片的一頂表面；執行高準度面對面對準使該第一主動電路層晶圓片面朝下地對至該界面晶圓片；將該第一主動電路層晶圓片的該第二佈線層直接接合至該界面晶圓片的該第一佈線層；在將該第一主動電路層晶圓片接合至該界面晶圓片之後，相對於該第一主動電路層晶圓片的P-層選擇性移除該第一主動電路層晶圓片的P+部分；在選擇性移除該第一主動電路層晶圓片的P+部分之後，製造一第三佈線層於該P-層的背面；提供一第二主動電路層晶圓片，該第二主動電路層晶圓片包括一P-層所覆蓋的一P+部分，該第二主動電路層晶圓片之P-層包括主動電路；製造一第四佈線層於該第二主動電路層晶圓片的一頂表面；執行高準度面對面對準使該第二主動電路層晶圓片面朝下地對至該第一主動電路層晶圓片的P-層；將該第二主動電路層晶圓片的該第四佈線層直接接合至 該第三佈線層於該P-層的背面；在將該第二主動電路層晶圓片接合至該第三佈線層之後，相對於該第二主動電路層晶圓片的P-層選擇性移除該第二主動電路層晶圓片的P+部分；在選擇性移除該第二主動電路層晶圓片的P+部分之後，製造一第五佈線層於該第二主動電路層晶圓片的該P-層的背面上；提供一基底晶圓片，該基底晶圓片包括一第六佈線層；執行高準度面對面對準使該第二主動電路層晶圓片的該P-層面朝下地對至該基底晶圓片；將位於該第二主動電路層晶圓片的該P-層的背面上的該第五佈線層直接接合至該基底晶圓片的第六佈線層；及在將該第五佈線層面接合至該基底晶圓片之後，薄化該界面晶圓片以形成一界面層，及形成包含焊料凸塊在該界面層上的金屬層(metallizations)，該焊料凸塊透過該界面層中的該等穿透矽介層耦合至該第一佈線層，其中該界面晶圓片具有不溶於一蝕刻劑的一材料，該蝕刻劑係用於相對於該第一主動電路層晶圓片的P-層選擇性蝕刻該第一主動電路層晶圓片的P+部分之選擇性移除步驟。
  2. 一種製造一3D積體電路結構的方法，該方法包含以下步驟：提供一第一主動電路層晶圓片，該第一主動電路層晶圓片包括一P-層所覆蓋的一P+層，該第一主動電路層晶圓片之P-層包括主動電路；製造一第一佈線層於該第一主動電路層晶圓片的一頂表 面；執行高準度面對面對準使該第一主動電路層晶圓片面朝下地對至一界面晶圓片，該界面晶圓片包括一第二佈線層；將該第一主動電路層晶圓片的該第一佈線層直接接合至該界面晶圓片的該第二佈線層；在將該第一主動電路層晶圓片接合至該界面晶圓片之後，相對於該第一主動電路層晶圓片的P-層選擇性移除該第一主動電路層晶圓片的P+部分；及在選擇性移除該第一主動電路層晶圓片的P+部分之後，製造一第三佈線層直接於該P-層的背面。
  3. 如申請專利範圍第2項所述之方法，另外包含以下步驟：提供一基底晶圓片，該基底晶圓片包括一第四佈線層；執行高準度面對面對準使該第一主動電路層晶圓片的該P-層面朝下地對至該基底晶圓片；及將於該第一主動電路層晶圓片的該P-層背面的該第三佈線層直接接合至該基底晶圓片的該第四佈線層。
  4. 如申請專利範圍第3項所述之方法，另外包含以下步驟：將位於該第一主動電路層晶圓片的該P-層背面之該第三佈線層接合至該基底晶圓片之後，薄化該界面晶圓片以形成一界面層，及形成金屬層(metallizations)在該界面層上，該金屬層透過該界面層中的該等介層耦合至該第二佈線層。
  5. 如申請專利範圍第3項所述之方法，其中該基底晶圓片包括邏輯電路。
  6. 如申請專利範圍第2項所述之方法，其中該界面晶圓片具有不溶於一蝕刻劑的一材料，該蝕刻劑係用於相對於該第一主動電路層晶圓片的P-層選擇性蝕刻該第一主動電路層晶圓片的P+部分之選擇性移除步驟。
  7. 如申請專利範圍第2項所述之方法，其中該第一主動電路層晶圓片另外包含穿透矽介層。
  8. 如申請專利範圍第2項所述之方法，另外包含以下步驟：提供一另一主動電路層晶圓片，該另一主動電路層晶圓片包括一P-層所覆蓋的一P+部分，該另一主動電路層晶圓片之P-層包括主動電路；製造一第四佈線層於該另一主動電路層晶圓片的一頂表面；執行高準度面對面對準使該另一主動電路層晶圓片面朝下地對至該第一主動電路層晶圓片之該P-層；將該另一主動電路層晶圓片的該第四佈線層直接接合至位於該第一主動電路層晶圓片之該P-層背面該第三佈線層；在接合該另一主動電路層晶圓片之後，相對於該另一主動電路層晶圓片的P-層選擇性移除該另一主動電路層晶圓片的P+部分；在選擇性移除該另一主動電路層晶圓片的P+部分之後，製造一另一佈線層直接於該另一主動電路層晶圓片的該P-層的背面上。
  9. 一種用一製造一3D積體電路結構之程式編碼的具體電腦可讀媒體，該程式包含執行以下步驟的指令：提供一第一主動電路層晶圓片，該第一主動電路層晶圓片包括一P-層所覆蓋的一P+層，該第一主動電路層晶圓片之P-層包括主動電路；製造一第一佈線層於該第一主動電路層晶圓片的一頂表面；將該第一主動電路層晶圓片的該第一佈線層直接接合至一界面晶圓片的一第二佈線層；在將該第一主動電路層晶圓片接合至該界面晶圓片之後，相對於該第一主動電路層晶圓片的P-層選擇性移除該第一主動電路層晶圓片的P+部分；及在選擇性移除該第一主動電路層晶圓片的P+部分之後，製造一第三佈線層直接於該P-層的背面，其中該程式另外包含執行以下步驟的指令：提供一基底晶圓片，該基底晶圓片包括一第四佈線層；執行高準度面對面對準使該第一主動電路層晶圓片的該P-層面朝下地對至該基底晶圓片；及將位於該第一主動電路層晶圓片的該P-層的背面的該第三佈線層直接接合至該基底晶圓片的該第四佈線層。
  10. 如申請專利範圍第9項所述之具體電腦可讀媒體，其中該程式另外包含執行以下步驟的指令：將位於位於該第一主動電路層晶圓片的該P-層背面之該第三佈線層接合至該基底晶圓片之後，薄化該界面晶圓片以形成一界面層，及形成金屬層(metallizations)在該界面層上，該金屬層透過該界面層中的該等介層耦合至該第二佈線層。
  11. 如申請專利範圍第9項所述之具體電腦可讀媒體，其中該界面晶圓片具有不溶於一蝕刻劑的一材料，該蝕刻劑係用於相對於該第一主動電路層晶圓片的P-層選擇性蝕刻該第一主動電路層晶圓片的P+部分之選擇性移除步驟。
  12. 一種3D積體電路結構，包含：一界面晶圓片，該界面晶圓片包括一第一佈線層；一第一主動電路層晶圓片，包括一P-層，該P-層包括主動電路，該第一主動電路層晶圓片的一第三佈線層直接接合至該界面晶圓片的該第一佈線層；一第二佈線層位於該第一主動電路層晶圓片的該P-層之背面；及一第二主動電路層晶圓片包括一P-層所覆蓋的一P+層，該第二主動電路層晶圓片之P-層包括主動電路，該第二主動電路層晶圓片的一第四佈線層接合至位於該第一主動電路層晶圓片的該P-層之背面的該第二佈線層。
  13. 如申請專利範圍第12項所述之3D積體電路結構，其中該 界面晶圓片具有不溶於一蝕刻劑的一材料，該蝕刻劑係能相對於該第二主動電路層晶圓片的P-層選擇性移除該第二主動電路層晶圓片的P+部分。
  14. 如申請專利範圍第12項所述之3D積體電路結構，其中該第一主動電路層晶圓片之該P-層另外包含穿透矽介層。
  15. 如申請專利範圍第12項所述之3D積體電路結構，其中該第一主動電路層晶圓片包含一塊體矽晶圓片，且該第二主動電路層晶圓片包含一塊體矽晶圓片。
  16. 如申請專利範圍第12項所述之3D積體電路結構，其中該第一主動電路層晶圓片包含一SOI晶圓片，且該第二主動電路層晶圓片包含一塊體矽晶圓片。
  17. 如申請專利範圍第12項所述之3D積體電路結構，其中該第一主動電路層晶圓片包含一SOI晶圓片，且該第二主動電路層晶圓片包含一SOI晶圓片。
  18. 如申請專利範圍第12項所述之3D積體電路結構，其中該界面晶圓片另外包括主動電路及/或被動電路元件。
  19. 如申請專利範圍第12項所述之3D積體電路結構，其中該界面晶圓片另外包括解耦電容器及/或電壓調整電路。
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