JP2012500504A - 3次元集積回路、これの製造方法及び記録媒体(基板の一部を正確に制御可能に除去することができる3次元集積回路デバイスの製造方法) - Google Patents
3次元集積回路、これの製造方法及び記録媒体(基板の一部を正確に制御可能に除去することができる3次元集積回路デバイスの製造方法) Download PDFInfo
- Publication number
- JP2012500504A JP2012500504A JP2011523964A JP2011523964A JP2012500504A JP 2012500504 A JP2012500504 A JP 2012500504A JP 2011523964 A JP2011523964 A JP 2011523964A JP 2011523964 A JP2011523964 A JP 2011523964A JP 2012500504 A JP2012500504 A JP 2012500504A
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- layer
- active circuit
- circuit layer
- interface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 39
- 239000000758 substrate Substances 0.000 title description 32
- 238000000034 method Methods 0.000 claims abstract description 64
- 229910052710 silicon Inorganic materials 0.000 claims description 31
- 239000010703 silicon Substances 0.000 claims description 31
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 28
- 229910052751 metal Inorganic materials 0.000 claims description 21
- 239000002184 metal Substances 0.000 claims description 21
- 238000005530 etching Methods 0.000 claims description 9
- 239000000463 material Substances 0.000 claims description 9
- 229910000679 solder Inorganic materials 0.000 claims description 9
- 239000003990 capacitor Substances 0.000 claims description 4
- 239000003795 chemical substances by application Substances 0.000 claims 2
- 235000012431 wafers Nutrition 0.000 description 133
- 238000013461 design Methods 0.000 description 63
- 230000008569 process Effects 0.000 description 31
- 238000012938 design process Methods 0.000 description 14
- 238000012360 testing method Methods 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 7
- 238000004088 simulation Methods 0.000 description 7
- 238000003860 storage Methods 0.000 description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 6
- 239000010949 copper Substances 0.000 description 6
- ALKZAGKDWUSJED-UHFFFAOYSA-N dinuclear copper ion Chemical compound [Cu].[Cu] ALKZAGKDWUSJED-UHFFFAOYSA-N 0.000 description 6
- 238000012545 processing Methods 0.000 description 6
- 238000000151 deposition Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 3
- 229910001020 Au alloy Inorganic materials 0.000 description 3
- 229910000881 Cu alloy Inorganic materials 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 239000000919 ceramic Substances 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 239000003353 gold alloy Substances 0.000 description 3
- MSNOMDLPLDYDME-UHFFFAOYSA-N gold nickel Chemical compound [Ni].[Au] MSNOMDLPLDYDME-UHFFFAOYSA-N 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 239000000047 product Substances 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 238000012546 transfer Methods 0.000 description 3
- 238000012795 verification Methods 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 238000004026 adhesive bonding Methods 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 2
- 238000013500 data storage Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 238000003631 wet chemical etching Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000007795 chemical reaction product Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000013067 intermediate product Substances 0.000 description 1
- 238000012804 iterative process Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000009877 rendering Methods 0.000 description 1
- 238000002076 thermal analysis method Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05005—Structure
- H01L2224/05008—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05005—Structure
- H01L2224/05009—Bonding area integrally formed with a via connection of the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0502—Disposition
- H01L2224/05024—Disposition the internal layer being disposed on a redistribution layer on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05147—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/05184—Tungsten [W] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05568—Disposition the whole external layer protruding from the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
Abstract
【解決手段】 本発明の方法に従うと、第1の能動回路層ウエハが準備される。第1の能動回路層ウエハは、能動回路を含むP−層により覆われているP+部分を有する。第1の能動回路層ウエハは第1配線層を含むインターフェース・ウエハにフェイス・ダウン・ボンディングされ、次いで、第1の能動回路層ウエハのP−層を残すように第1の能動回路層ウエハのP+部分が選択的に除去される。次に、P−層の背面に配線層が形成される。更に本発明に従うと、3次元集積回路構造及びこの3次元集積回路構造を製造するための手順を実行させるためのプログラムを記録したコンピュータ読み取り可能な記録媒体が提供される。
【選択図】 図11
Description
102 スルー・シリコン・ビア
104 配線層
200 第1の能動回路層ウエハ
202 P+ウエハ
204 P−上部能動回路層
206 スルー・シリコン・ビア
208 配線レベル
300 第2の能動回路層ウエハ
302 P+ウエハ
304 P−上部能動回路層
306 スルー・シリコン・ビア
308 配線レベル
800 ベース・ウエハ
808 配線層
820 誘電体層
822 コンタクト金属
825 C4ハンダ・バンプ
910 設計プロセス
920 入力設計構造
930 ライブラリィ・エレメント
940 設計仕様
950 特性データ
960 検証データ
970 設計ルール
980 ネットリスト
985 テスト・データ・ファイル
990 設計構造
995 ステージ
Claims (25)
- 第1配線層及びスルー・シリコン・ビアを含むインターフェース・ウエハを準備するステップと、
能動回路及びスルー・シリコン・ビアを含むP−層により覆われているP+部分を有する第1の能動回路層ウエハを準備するステップと、
前記第1の能動回路層ウエハを前記インターフェース・ウエハにフェイス・ダウン・ボンディングするステップと、
前記第1の能動回路層ウエハを前記インターフェース・ウエハにフェイス・ダウン・ボンディングした後に、前記第1の能動回路層ウエハの前記P−層を残すように前記第1の能動回路層ウエハの前記P+部分を選択的に除去するステップと、
前記第1の能動回路層ウエハのP+部分を除去した後に、前記P−層の背面に第2配線層を形成するステップと、
能動回路を含むP−層により覆われているP+部分を有する第2の能動回路層ウエハを準備するステップと、
前記第2の能動回路層ウエハを前記第2配線層にフェイス・ダウン・ボンディングするステップと、
前記第2の能動回路層ウエハを前記第2配線層にフェイス・ダウン・ボンディングした後に、前記第2の能動回路層ウエハの前記P−層を残すように前記第2の能動回路層ウエハの前記P+部分を選択的に除去するステップと、
前記第2の能動回路層ウエハの前記P+部分を選択的に除去した後に、前記第2の能動回路層ウエハの前記P−層の背面に第3配線層を形成するステップと、
第4配線層を含むベース・ウエハを準備するステップと、
前記第3配線層を前記ベース・ウエハにフェイス・ダウン・ボンディングするステップと、
前記第3配線層を前記ベース・ウエハにフェイス・ダウン・ボンディングした後に、前記インターフェース・ウエハを薄くしてインターフェース層を形成し、そして前記インターフェース層上にハンダ・バンプを構成する金属を形成するステップであって、前記ハンダ・バンプは前記インターフェース層の前記スルー・シリコン・ビアを介して前記第1配線層に結合されている前記ステップとを含み、
前記インターフェース・ウエハは、前記第1の能動回路層ウエハの前記P−層を残すように前記第1の能動回路層ウエハの前記P+部分を選択的にエッチングする前記選択的に除去するステップにおいて使用されるエッチング剤に溶解しない材料で形成されている、3次元集積回路の製造方法。 - 能動回路を含むP−層により覆われているP+部分を有する第1の能動回路層ウエハを準備するステップと、
前記第1の能動回路層ウエハを、第1配線層を含むインターフェース・ウエハにフェイス・ダウン・ボンディングするステップと、
前記第1の能動回路層ウエハを前記インターフェース・ウエハにフェイス・ダウン・ボンディングした後に、前記第1の能動回路層ウエハの前記P−層を残すように前記第1の能動回路層ウエハの前記P+部分を選択的に除去するステップと、
前記第1の能動回路層ウエハのP+部分を選択的に除去した後に、前記P−層の背面に配線層を形成するステップとを含む、3次元集積回路の製造方法。 - 第2配線層を含むベース・ウエハを準備するステップと、
前記P−層の背面の配線層を前記ベース・ウエハにフェイス・ダウン・ボンディングするステップとを含む、請求項2に記載の方法。 - 前記P−層の背面の配線層を前記ベース・ウエハにフェイス・ダウン・ボンディングした後に、前記インターフェース・ウエハを薄くしてインターフェース層を形成し、そして前記インターフェース層上に金属を形成するステップであって、前記金属は前記インターフェース層のビアを介して前記第1配線層に結合されている前記ステップを含む、請求項3に記載の方法。
- 前記ベース・ウエハは論理回路を含む、請求項3に記載の方法。
- 前記インターフェース・ウエハは、前記第1の能動回路層ウエハの前記P−層を残すように前記第1の能動回路層ウエハの前記P+部分を選択的にエッチングする前記選択的に除去するステップにおいて使用されるエッチング剤に溶解しない材料で形成されている、請求項2に記載の方法。
- 前記第1の能動回路層ウエハは、スルー・シリコン・ビアを有する、請求項2に記載の方法。
- 能動回路を含むP−層により覆われているP+部分を有する他の能動回路層ウエハを準備するステップと、
前記他の能動回路層ウエハを、該他の能動回路層ウエハに先行して既に設けられている能動回路層ウエハのP−層の背面の配線層にフェイス・ダウン・ボンディングするステップと、
前記他の能動回路層ウエハを、前記既に設けられている能動回路層ウエハP−層の背面の配線層にフェイス・ダウン・ボンディングした後に、前記他の能動回路層ウエハの前記P−層を残すように前記他の能動回路層ウエハの前記P+部分を選択的に除去するステップと、
前記他の能動回路層ウエハの前記P+部分を選択的に除去した後に、前記他の能動回路層ウエハの前記P−層の背面に他の配線層を形成するステップとを含む、請求項2に記載の方法。 - 前記他の能動回路層ウエハを準備するステップと、前記他の能動回路層ウエハを前記既に設けられている能動回路層ウエハP−層の背面上の配線層にフェイス・ダウン・ボンディングするステップと、前記他の能動回路層ウエハの前記P+部分を選択的に除去するステップと、前記他の能動回路層ウエハの前記P−層の背面に他の配線層を形成するステップとをN回繰り返すステップを含む、請求項8に記載の方法。
- 第2配線層を含むベース・ウエハを準備するステップと、
N番目の能動回路層ウエハのP−層の背面の配線層を前記ベース・ウエハにフェイス・ダウン・ボンディングするステップとを含む、請求項9に記載の方法。 - コンピュータに、3次元集積回路構造を製造するための、
能動回路を含むP−層により覆われているP+部分を有する第1の能動回路層ウエハを準備する手順と、
前記第1の能動回路層ウエハを、第1配線層を含むインターフェース・ウエハにフェイス・ダウン・ボンディングする手順と、
前記第1の能動回路層ウエハを前記インターフェース・ウエハにフェイス・ダウン・ボンディングした後に、前記第1の能動回路層ウエハの前記P−層を残すように前記第1の能動回路層ウエハの前記P+部分を選択的に除去する手順と、
前記第1の能動回路層ウエハのP+部分を除去した後に、前記P−層の背面に第2の配線層を形成する手順とを実行させるためのプログラムを記録したコンピュータ読み取り可能な記録媒体。 - 第2配線層を含むベース・ウエハを準備する手順と、
前記P−層の背面の配線層を前記ベース・ウエハにフェイス・ダウン・ボンディングする手順とを含む、請求項11に記載の記録媒体。 - 前記P−層の背面の配線層を前記ベース・ウエハにフェイス・ダウン・ボンディングした後に、前記インターフェース・ウエハを薄くしてインターフェース層を形成し、そして前記インターフェース層上に金属を形成する手順であって、前記金属は前記インターフェース層のビアを介して前記第1配線層に結合されている前記手順を含む、請求項12に記載の記録媒体。
- 前記インターフェース・ウエハは、前記第1の能動回路層ウエハの前記P−層を残すように前記第1の能動回路層ウエハの前記P+部分を選択的にエッチングする前記選択的に除去する手順において使用されるエッチング剤に溶解しない材料で形成されている、請求項11に記載の記録媒体。
- 能動回路を含むP−層により覆われているP+部分を有する他の能動回路層ウエハを準備する手順と、
前記他の能動回路層ウエハを、該他の能動回路層ウエハに先行して既に設けられている能動回路層ウエハのP−層の背面の配線層にフェイス・ダウン・ボンディングする手順と、
前記他の能動回路層ウエハを前記既に設けられている能動回路層ウエハのP−層の背面上の配線層にフェイス・ダウン・ボンディングした後に、前記他の能動回路層ウエハの前記P−層を残すように前記他の能動回路層ウエハの前記P+部分を選択的に除去する手順と、
前記他の能動回路層ウエハの前記P+部分を選択的に除去した後に、前記他の能動回路層ウエハの前記P−層の背面に他の配線層を形成する手順とを含む、請求項11に記載の記録媒体。 - 前記他の能動回路層ウエハを準備する手順と、前記他の能動回路層ウエハを前記既に設けられている能動回路層ウエハのP−層の背面上の配線層にフェイス・ダウン・ボンディングする手順と、前記他の能動回路層ウエハの前記P+部分を選択的に除去する手順と、前記他の能動回路層ウエハの前記P−層の背面に他の配線層を形成する手順とをN回繰り返すステップを含む、請求項15に記載の記録媒体。
- 第2配線層を含むベース・ウエハを準備する手順と、
N番目の能動回路層ウエハのP−層の背面の配線層を前記ベース・ウエハにフェイス・ダウン・ボンディングする手順とを含む請求項16に記載の記録媒体。 - 第1配線層を含むインターフェース・ウエハと、
能動回路を含むP−層を有し、前記インターフェース・ウエハにフェイス・ダウン・ボンディングされた第1の能動回路層ウエハと、
前記P−層の背面の第2配線層と、
能動回路を含むP−層により覆われたP+部分を有し、前記第2配線層にフェイス・ダウン・ボンディングされた第2の能動回路層ウエハとを備える、3次元集積回路構造。 - 前記インターフェース・ウエハは、前記第2の能動回路層ウエハの前記P−層を残すように前記第2の能動回路層ウエハの前記P+部分を選択的にエッチングするエッチング剤に溶解しない材料で形成されている、請求項18に記載の3次元集積回路構造。
- 前記第1の能動回路層ウエハのP−層は、スルー・シリコン・ビアを含む、請求項18に記載の3次元集積回路構造。
- 前記第1の能動回路層ウエハはバルク・シリコン・ウエハであり、そして前記第2の能動回路層ウエハはバルク・シリコン・ウエハである、請求項18に記載の3次元集積回路構造。
- 前記第1の能動回路層ウエハはSOIウエハであり、そして前記第2の能動回路層ウエハはバルク・シリコン・ウエハである、請求項18に記載の3次元集積回路構造。
- 前記第1の能動回路層ウエハはSOIウエハであり、そして前記第2の能動回路層ウエハはSOIウエハである、請求項18に記載の3次元集積回路構造。
- 前記インターフェース・ウエハは、能動回路素子または受動回路素子あるいはその両方を含む、請求項18に記載の3次元集積回路構造。
- 前記インターフェース・ウエハは、減結合キャパシタ又は電圧調整回路あるいはその両方を含む、請求項18に記載の3次元集積回路構造。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/194,065 US8129256B2 (en) | 2008-08-19 | 2008-08-19 | 3D integrated circuit device fabrication with precisely controllable substrate removal |
US12/194,065 | 2008-08-19 | ||
PCT/US2009/054333 WO2010022163A1 (en) | 2008-08-19 | 2009-08-19 | 3d integrated circuit device fabrication |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2012500504A true JP2012500504A (ja) | 2012-01-05 |
JP5285777B2 JP5285777B2 (ja) | 2013-09-11 |
Family
ID=41695575
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2011523964A Expired - Fee Related JP5285777B2 (ja) | 2008-08-19 | 2009-08-19 | 3次元集積回路の製造方法及びプログラム |
Country Status (6)
Country | Link |
---|---|
US (3) | US8129256B2 (ja) |
EP (1) | EP2313923B1 (ja) |
JP (1) | JP5285777B2 (ja) |
KR (1) | KR101332076B1 (ja) |
TW (1) | TWI514513B (ja) |
WO (1) | WO2010022163A1 (ja) |
Families Citing this family (210)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8298914B2 (en) | 2008-08-19 | 2012-10-30 | International Business Machines Corporation | 3D integrated circuit device fabrication using interface wafer as permanent carrier |
US8399336B2 (en) * | 2008-08-19 | 2013-03-19 | International Business Machines Corporation | Method for fabricating a 3D integrated circuit device having lower-cost active circuitry layers stacked before higher-cost active circuitry layer |
US9577642B2 (en) | 2009-04-14 | 2017-02-21 | Monolithic 3D Inc. | Method to form a 3D semiconductor device |
US8384426B2 (en) * | 2009-04-14 | 2013-02-26 | Monolithic 3D Inc. | Semiconductor device and structure |
US7986042B2 (en) | 2009-04-14 | 2011-07-26 | Monolithic 3D Inc. | Method for fabrication of a semiconductor device and structure |
US8427200B2 (en) | 2009-04-14 | 2013-04-23 | Monolithic 3D Inc. | 3D semiconductor device |
US8754533B2 (en) | 2009-04-14 | 2014-06-17 | Monolithic 3D Inc. | Monolithic three-dimensional semiconductor device and structure |
US9711407B2 (en) | 2009-04-14 | 2017-07-18 | Monolithic 3D Inc. | Method of manufacturing a three dimensional integrated circuit by transfer of a mono-crystalline layer |
US8373439B2 (en) | 2009-04-14 | 2013-02-12 | Monolithic 3D Inc. | 3D semiconductor device |
US8362482B2 (en) | 2009-04-14 | 2013-01-29 | Monolithic 3D Inc. | Semiconductor device and structure |
US8405420B2 (en) | 2009-04-14 | 2013-03-26 | Monolithic 3D Inc. | System comprising a semiconductor device and structure |
US8378715B2 (en) | 2009-04-14 | 2013-02-19 | Monolithic 3D Inc. | Method to construct systems |
US9509313B2 (en) | 2009-04-14 | 2016-11-29 | Monolithic 3D Inc. | 3D semiconductor device |
US8669778B1 (en) | 2009-04-14 | 2014-03-11 | Monolithic 3D Inc. | Method for design and manufacturing of a 3D semiconductor device |
US8058137B1 (en) | 2009-04-14 | 2011-11-15 | Monolithic 3D Inc. | Method for fabrication of a semiconductor device and structure |
US8395191B2 (en) | 2009-10-12 | 2013-03-12 | Monolithic 3D Inc. | Semiconductor device and structure |
US20110199116A1 (en) * | 2010-02-16 | 2011-08-18 | NuPGA Corporation | Method for fabrication of a semiconductor device and structure |
US11984445B2 (en) | 2009-10-12 | 2024-05-14 | Monolithic 3D Inc. | 3D semiconductor devices and structures with metal layers |
US10910364B2 (en) | 2009-10-12 | 2021-02-02 | Monolitaic 3D Inc. | 3D semiconductor device |
US9099424B1 (en) | 2012-08-10 | 2015-08-04 | Monolithic 3D Inc. | Semiconductor system, device and structure with heat removal |
US10354995B2 (en) | 2009-10-12 | 2019-07-16 | Monolithic 3D Inc. | Semiconductor memory device and structure |
US10157909B2 (en) | 2009-10-12 | 2018-12-18 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US8148728B2 (en) | 2009-10-12 | 2012-04-03 | Monolithic 3D, Inc. | Method for fabrication of a semiconductor device and structure |
US8450804B2 (en) | 2011-03-06 | 2013-05-28 | Monolithic 3D Inc. | Semiconductor device and structure for heat removal |
US11374118B2 (en) | 2009-10-12 | 2022-06-28 | Monolithic 3D Inc. | Method to form a 3D integrated circuit |
US8536023B2 (en) | 2010-11-22 | 2013-09-17 | Monolithic 3D Inc. | Method of manufacturing a semiconductor device and structure |
US10388863B2 (en) | 2009-10-12 | 2019-08-20 | Monolithic 3D Inc. | 3D memory device and structure |
US10043781B2 (en) | 2009-10-12 | 2018-08-07 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11018133B2 (en) | 2009-10-12 | 2021-05-25 | Monolithic 3D Inc. | 3D integrated circuit |
US10366970B2 (en) | 2009-10-12 | 2019-07-30 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US8581349B1 (en) | 2011-05-02 | 2013-11-12 | Monolithic 3D Inc. | 3D memory semiconductor device and structure |
US8742476B1 (en) | 2012-11-27 | 2014-06-03 | Monolithic 3D Inc. | Semiconductor device and structure |
US8476145B2 (en) | 2010-10-13 | 2013-07-02 | Monolithic 3D Inc. | Method of fabricating a semiconductor device and structure |
US8541819B1 (en) | 2010-12-09 | 2013-09-24 | Monolithic 3D Inc. | Semiconductor device and structure |
US8026521B1 (en) | 2010-10-11 | 2011-09-27 | Monolithic 3D Inc. | Semiconductor device and structure |
US8492886B2 (en) | 2010-02-16 | 2013-07-23 | Monolithic 3D Inc | 3D integrated circuit with logic |
US8373230B1 (en) | 2010-10-13 | 2013-02-12 | Monolithic 3D Inc. | Method for fabrication of a semiconductor device and structure |
US8461035B1 (en) | 2010-09-30 | 2013-06-11 | Monolithic 3D Inc. | Method for fabrication of a semiconductor device and structure |
US9099526B2 (en) | 2010-02-16 | 2015-08-04 | Monolithic 3D Inc. | Integrated circuit device and structure |
US9219005B2 (en) | 2011-06-28 | 2015-12-22 | Monolithic 3D Inc. | Semiconductor system and device |
US9953925B2 (en) | 2011-06-28 | 2018-04-24 | Monolithic 3D Inc. | Semiconductor system and device |
US10217667B2 (en) | 2011-06-28 | 2019-02-26 | Monolithic 3D Inc. | 3D semiconductor device, fabrication method and system |
US8901613B2 (en) | 2011-03-06 | 2014-12-02 | Monolithic 3D Inc. | Semiconductor device and structure for heat removal |
US8642416B2 (en) | 2010-07-30 | 2014-02-04 | Monolithic 3D Inc. | Method of forming three dimensional integrated circuit devices using layer transfer technique |
US20120220101A1 (en) * | 2010-08-27 | 2012-08-30 | Triune Ip Llc | Internal conductive layer |
US8163581B1 (en) | 2010-10-13 | 2012-04-24 | Monolith IC 3D | Semiconductor and optoelectronic devices |
US8273610B2 (en) | 2010-11-18 | 2012-09-25 | Monolithic 3D Inc. | Method of constructing a semiconductor device and structure |
US11482440B2 (en) | 2010-12-16 | 2022-10-25 | Monolithic 3D Inc. | 3D semiconductor device and structure with a built-in test circuit for repairing faulty circuits |
US10497713B2 (en) | 2010-11-18 | 2019-12-03 | Monolithic 3D Inc. | 3D semiconductor memory device and structure |
US11257867B1 (en) | 2010-10-11 | 2022-02-22 | Monolithic 3D Inc. | 3D semiconductor device and structure with oxide bonds |
US11227897B2 (en) | 2010-10-11 | 2022-01-18 | Monolithic 3D Inc. | Method for producing a 3D semiconductor memory device and structure |
US10896931B1 (en) | 2010-10-11 | 2021-01-19 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US10290682B2 (en) | 2010-10-11 | 2019-05-14 | Monolithic 3D Inc. | 3D IC semiconductor device and structure with stacked memory |
US11024673B1 (en) | 2010-10-11 | 2021-06-01 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11315980B1 (en) | 2010-10-11 | 2022-04-26 | Monolithic 3D Inc. | 3D semiconductor device and structure with transistors |
US11469271B2 (en) | 2010-10-11 | 2022-10-11 | Monolithic 3D Inc. | Method to produce 3D semiconductor devices and structures with memory |
US11600667B1 (en) | 2010-10-11 | 2023-03-07 | Monolithic 3D Inc. | Method to produce 3D semiconductor devices and structures with memory |
US11158674B2 (en) | 2010-10-11 | 2021-10-26 | Monolithic 3D Inc. | Method to produce a 3D semiconductor device and structure |
US8114757B1 (en) | 2010-10-11 | 2012-02-14 | Monolithic 3D Inc. | Semiconductor device and structure |
US11018191B1 (en) | 2010-10-11 | 2021-05-25 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11133344B2 (en) | 2010-10-13 | 2021-09-28 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with image sensors |
US11929372B2 (en) | 2010-10-13 | 2024-03-12 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with image sensors and wafer bonding |
US11984438B2 (en) | 2010-10-13 | 2024-05-14 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with oxide bonding |
US9197804B1 (en) | 2011-10-14 | 2015-11-24 | Monolithic 3D Inc. | Semiconductor and optoelectronic devices |
US11063071B1 (en) | 2010-10-13 | 2021-07-13 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with waveguides |
US11694922B2 (en) | 2010-10-13 | 2023-07-04 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with oxide bonding |
US11437368B2 (en) | 2010-10-13 | 2022-09-06 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with oxide bonding |
US11855100B2 (en) | 2010-10-13 | 2023-12-26 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with oxide bonding |
US11605663B2 (en) | 2010-10-13 | 2023-03-14 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with image sensors and wafer bonding |
US10943934B2 (en) | 2010-10-13 | 2021-03-09 | Monolithic 3D Inc. | Multilevel semiconductor device and structure |
US11404466B2 (en) | 2010-10-13 | 2022-08-02 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with image sensors |
US11164898B2 (en) | 2010-10-13 | 2021-11-02 | Monolithic 3D Inc. | Multilevel semiconductor device and structure |
US11163112B2 (en) | 2010-10-13 | 2021-11-02 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with electromagnetic modulators |
US10679977B2 (en) | 2010-10-13 | 2020-06-09 | Monolithic 3D Inc. | 3D microdisplay device and structure |
US11327227B2 (en) | 2010-10-13 | 2022-05-10 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with electromagnetic modulators |
US10998374B1 (en) | 2010-10-13 | 2021-05-04 | Monolithic 3D Inc. | Multilevel semiconductor device and structure |
US11869915B2 (en) | 2010-10-13 | 2024-01-09 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with image sensors and wafer bonding |
US10833108B2 (en) | 2010-10-13 | 2020-11-10 | Monolithic 3D Inc. | 3D microdisplay device and structure |
US11043523B1 (en) | 2010-10-13 | 2021-06-22 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with image sensors |
US11855114B2 (en) | 2010-10-13 | 2023-12-26 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with image sensors and wafer bonding |
US8379458B1 (en) | 2010-10-13 | 2013-02-19 | Monolithic 3D Inc. | Semiconductor device and structure |
US10978501B1 (en) | 2010-10-13 | 2021-04-13 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with waveguides |
US11804396B2 (en) | 2010-11-18 | 2023-10-31 | Monolithic 3D Inc. | Methods for producing a 3D semiconductor device and structure with memory cells and multiple metal layers |
US11004719B1 (en) | 2010-11-18 | 2021-05-11 | Monolithic 3D Inc. | Methods for producing a 3D semiconductor memory device and structure |
US11784082B2 (en) | 2010-11-18 | 2023-10-10 | Monolithic 3D Inc. | 3D semiconductor device and structure with bonding |
US11094576B1 (en) | 2010-11-18 | 2021-08-17 | Monolithic 3D Inc. | Methods for producing a 3D semiconductor memory device and structure |
US11508605B2 (en) | 2010-11-18 | 2022-11-22 | Monolithic 3D Inc. | 3D semiconductor memory device and structure |
US11610802B2 (en) | 2010-11-18 | 2023-03-21 | Monolithic 3D Inc. | Method for producing a 3D semiconductor device and structure with single crystal transistors and metal gate electrodes |
US11121021B2 (en) | 2010-11-18 | 2021-09-14 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11735462B2 (en) | 2010-11-18 | 2023-08-22 | Monolithic 3D Inc. | 3D semiconductor device and structure with single-crystal layers |
US11901210B2 (en) | 2010-11-18 | 2024-02-13 | Monolithic 3D Inc. | 3D semiconductor device and structure with memory |
US11018042B1 (en) | 2010-11-18 | 2021-05-25 | Monolithic 3D Inc. | 3D semiconductor memory device and structure |
US11355381B2 (en) | 2010-11-18 | 2022-06-07 | Monolithic 3D Inc. | 3D semiconductor memory device and structure |
US11031275B2 (en) | 2010-11-18 | 2021-06-08 | Monolithic 3D Inc. | 3D semiconductor device and structure with memory |
US11164770B1 (en) | 2010-11-18 | 2021-11-02 | Monolithic 3D Inc. | Method for producing a 3D semiconductor memory device and structure |
US11107721B2 (en) | 2010-11-18 | 2021-08-31 | Monolithic 3D Inc. | 3D semiconductor device and structure with NAND logic |
US11854857B1 (en) | 2010-11-18 | 2023-12-26 | Monolithic 3D Inc. | Methods for producing a 3D semiconductor device and structure with memory cells and multiple metal layers |
US11482438B2 (en) | 2010-11-18 | 2022-10-25 | Monolithic 3D Inc. | Methods for producing a 3D semiconductor memory device and structure |
US11862503B2 (en) | 2010-11-18 | 2024-01-02 | Monolithic 3D Inc. | Method for producing a 3D semiconductor device and structure with memory cells and multiple metal layers |
US11923230B1 (en) | 2010-11-18 | 2024-03-05 | Monolithic 3D Inc. | 3D semiconductor device and structure with bonding |
US11482439B2 (en) | 2010-11-18 | 2022-10-25 | Monolithic 3D Inc. | Methods for producing a 3D semiconductor memory device comprising charge trap junction-less transistors |
US11443971B2 (en) | 2010-11-18 | 2022-09-13 | Monolithic 3D Inc. | 3D semiconductor device and structure with memory |
US11211279B2 (en) | 2010-11-18 | 2021-12-28 | Monolithic 3D Inc. | Method for processing a 3D integrated circuit and structure |
US11615977B2 (en) | 2010-11-18 | 2023-03-28 | Monolithic 3D Inc. | 3D semiconductor memory device and structure |
US11569117B2 (en) | 2010-11-18 | 2023-01-31 | Monolithic 3D Inc. | 3D semiconductor device and structure with single-crystal layers |
US11495484B2 (en) | 2010-11-18 | 2022-11-08 | Monolithic 3D Inc. | 3D semiconductor devices and structures with at least two single-crystal layers |
US11521888B2 (en) | 2010-11-18 | 2022-12-06 | Monolithic 3D Inc. | 3D semiconductor device and structure with high-k metal gate transistors |
US11355380B2 (en) | 2010-11-18 | 2022-06-07 | Monolithic 3D Inc. | Methods for producing 3D semiconductor memory device and structure utilizing alignment marks |
US8970043B2 (en) * | 2011-02-01 | 2015-03-03 | Maxim Integrated Products, Inc. | Bonded stacked wafers and methods of electroplating bonded stacked wafers |
US8975670B2 (en) | 2011-03-06 | 2015-03-10 | Monolithic 3D Inc. | Semiconductor device and structure for heat removal |
US10388568B2 (en) | 2011-06-28 | 2019-08-20 | Monolithic 3D Inc. | 3D semiconductor device and system |
US8687399B2 (en) | 2011-10-02 | 2014-04-01 | Monolithic 3D Inc. | Semiconductor device and structure |
US9029173B2 (en) | 2011-10-18 | 2015-05-12 | Monolithic 3D Inc. | Method for fabrication of a semiconductor device and structure |
US9000557B2 (en) | 2012-03-17 | 2015-04-07 | Zvi Or-Bach | Semiconductor device and structure |
US11616004B1 (en) | 2012-04-09 | 2023-03-28 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers and a connective path |
US11410912B2 (en) | 2012-04-09 | 2022-08-09 | Monolithic 3D Inc. | 3D semiconductor device with vias and isolation layers |
US11088050B2 (en) | 2012-04-09 | 2021-08-10 | Monolithic 3D Inc. | 3D semiconductor device with isolation layers |
US10600888B2 (en) | 2012-04-09 | 2020-03-24 | Monolithic 3D Inc. | 3D semiconductor device |
US11164811B2 (en) | 2012-04-09 | 2021-11-02 | Monolithic 3D Inc. | 3D semiconductor device with isolation layers and oxide-to-oxide bonding |
US11594473B2 (en) | 2012-04-09 | 2023-02-28 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers and a connective path |
US11694944B1 (en) | 2012-04-09 | 2023-07-04 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers and a connective path |
US8557632B1 (en) | 2012-04-09 | 2013-10-15 | Monolithic 3D Inc. | Method for fabrication of a semiconductor device and structure |
US11476181B1 (en) | 2012-04-09 | 2022-10-18 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers |
US11735501B1 (en) | 2012-04-09 | 2023-08-22 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers and a connective path |
US11881443B2 (en) | 2012-04-09 | 2024-01-23 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers and a connective path |
US8623717B2 (en) * | 2012-06-12 | 2014-01-07 | International Business Machines Corporation | Side-gate defined tunable nanoconstriction in double-gated graphene multilayers |
US8828785B2 (en) * | 2012-09-12 | 2014-09-09 | International Business Machines Corporation | Single-crystal phase change material on insulator for reduced cell variability |
US8686428B1 (en) | 2012-11-16 | 2014-04-01 | Monolithic 3D Inc. | Semiconductor device and structure |
US8574929B1 (en) | 2012-11-16 | 2013-11-05 | Monolithic 3D Inc. | Method to form a 3D semiconductor device and structure |
US11063024B1 (en) | 2012-12-22 | 2021-07-13 | Monlithic 3D Inc. | Method to form a 3D semiconductor device and structure |
US8674470B1 (en) * | 2012-12-22 | 2014-03-18 | Monolithic 3D Inc. | Semiconductor device and structure |
US11217565B2 (en) | 2012-12-22 | 2022-01-04 | Monolithic 3D Inc. | Method to form a 3D semiconductor device and structure |
US11309292B2 (en) | 2012-12-22 | 2022-04-19 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers |
US11784169B2 (en) | 2012-12-22 | 2023-10-10 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers |
US11018116B2 (en) | 2012-12-22 | 2021-05-25 | Monolithic 3D Inc. | Method to form a 3D semiconductor device and structure |
US11967583B2 (en) | 2012-12-22 | 2024-04-23 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers |
US11961827B1 (en) | 2012-12-22 | 2024-04-16 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers |
US11916045B2 (en) | 2012-12-22 | 2024-02-27 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers |
US10651054B2 (en) | 2012-12-29 | 2020-05-12 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11087995B1 (en) | 2012-12-29 | 2021-08-10 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US9871034B1 (en) | 2012-12-29 | 2018-01-16 | Monolithic 3D Inc. | Semiconductor device and structure |
US9385058B1 (en) | 2012-12-29 | 2016-07-05 | Monolithic 3D Inc. | Semiconductor device and structure |
US10600657B2 (en) | 2012-12-29 | 2020-03-24 | Monolithic 3D Inc | 3D semiconductor device and structure |
US11177140B2 (en) | 2012-12-29 | 2021-11-16 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US10903089B1 (en) | 2012-12-29 | 2021-01-26 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11430668B2 (en) | 2012-12-29 | 2022-08-30 | Monolithic 3D Inc. | 3D semiconductor device and structure with bonding |
US11430667B2 (en) | 2012-12-29 | 2022-08-30 | Monolithic 3D Inc. | 3D semiconductor device and structure with bonding |
US10892169B2 (en) | 2012-12-29 | 2021-01-12 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11004694B1 (en) | 2012-12-29 | 2021-05-11 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US10115663B2 (en) | 2012-12-29 | 2018-10-30 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US8902663B1 (en) | 2013-03-11 | 2014-12-02 | Monolithic 3D Inc. | Method of maintaining a memory state |
US11935949B1 (en) | 2013-03-11 | 2024-03-19 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers and memory cells |
US11869965B2 (en) | 2013-03-11 | 2024-01-09 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers and memory cells |
US10325651B2 (en) | 2013-03-11 | 2019-06-18 | Monolithic 3D Inc. | 3D semiconductor device with stacked memory |
US11398569B2 (en) | 2013-03-12 | 2022-07-26 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11088130B2 (en) | 2014-01-28 | 2021-08-10 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US8994404B1 (en) | 2013-03-12 | 2015-03-31 | Monolithic 3D Inc. | Semiconductor device and structure |
US11923374B2 (en) | 2013-03-12 | 2024-03-05 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers |
US10840239B2 (en) | 2014-08-26 | 2020-11-17 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US10224279B2 (en) | 2013-03-15 | 2019-03-05 | Monolithic 3D Inc. | Semiconductor device and structure |
US9117749B1 (en) | 2013-03-15 | 2015-08-25 | Monolithic 3D Inc. | Semiconductor device and structure |
US11270055B1 (en) | 2013-04-15 | 2022-03-08 | Monolithic 3D Inc. | Automation for monolithic 3D devices |
US11030371B2 (en) | 2013-04-15 | 2021-06-08 | Monolithic 3D Inc. | Automation for monolithic 3D devices |
US11720736B2 (en) | 2013-04-15 | 2023-08-08 | Monolithic 3D Inc. | Automation methods for 3D integrated circuits and devices |
US11341309B1 (en) | 2013-04-15 | 2022-05-24 | Monolithic 3D Inc. | Automation for monolithic 3D devices |
US11574109B1 (en) | 2013-04-15 | 2023-02-07 | Monolithic 3D Inc | Automation methods for 3D integrated circuits and devices |
US9021414B1 (en) | 2013-04-15 | 2015-04-28 | Monolithic 3D Inc. | Automation for monolithic 3D devices |
US11487928B2 (en) | 2013-04-15 | 2022-11-01 | Monolithic 3D Inc. | Automation for monolithic 3D devices |
US9646872B2 (en) | 2013-11-13 | 2017-05-09 | Taiwan Semiconductor Manufacturing Company Limited | Systems and methods for a semiconductor structure having multiple semiconductor-device layers |
US10297586B2 (en) | 2015-03-09 | 2019-05-21 | Monolithic 3D Inc. | Methods for processing a 3D semiconductor device |
US11107808B1 (en) | 2014-01-28 | 2021-08-31 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11031394B1 (en) | 2014-01-28 | 2021-06-08 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US9472859B2 (en) | 2014-05-20 | 2016-10-18 | International Business Machines Corporation | Integration of area efficient antennas for phased array or wafer scale array antenna applications |
US9401303B2 (en) | 2014-08-01 | 2016-07-26 | Globalfoundries Inc. | Handler wafer removal by use of sacrificial inert layer |
US11056468B1 (en) | 2015-04-19 | 2021-07-06 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US10381328B2 (en) | 2015-04-19 | 2019-08-13 | Monolithic 3D Inc. | Semiconductor device and structure |
US10825779B2 (en) | 2015-04-19 | 2020-11-03 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11011507B1 (en) | 2015-04-19 | 2021-05-18 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US9570431B1 (en) | 2015-07-28 | 2017-02-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor wafer for integrated packages |
US10468363B2 (en) | 2015-08-10 | 2019-11-05 | X-Celeprint Limited | Chiplets with connection posts |
US11956952B2 (en) | 2015-08-23 | 2024-04-09 | Monolithic 3D Inc. | Semiconductor memory device and structure |
US11978731B2 (en) | 2015-09-21 | 2024-05-07 | Monolithic 3D Inc. | Method to produce a multi-level semiconductor memory device and structure |
DE112016004265T5 (de) | 2015-09-21 | 2018-06-07 | Monolithic 3D Inc. | 3d halbleitervorrichtung und -struktur |
US10522225B1 (en) | 2015-10-02 | 2019-12-31 | Monolithic 3D Inc. | Semiconductor device with non-volatile memory |
US11296115B1 (en) | 2015-10-24 | 2022-04-05 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US10847540B2 (en) | 2015-10-24 | 2020-11-24 | Monolithic 3D Inc. | 3D semiconductor memory device and structure |
US10418369B2 (en) | 2015-10-24 | 2019-09-17 | Monolithic 3D Inc. | Multi-level semiconductor memory device and structure |
US11991884B1 (en) | 2015-10-24 | 2024-05-21 | Monolithic 3D Inc. | 3D semiconductor device and structure with logic and memory |
US11114464B2 (en) | 2015-10-24 | 2021-09-07 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11114427B2 (en) | 2015-11-07 | 2021-09-07 | Monolithic 3D Inc. | 3D semiconductor processor and memory device and structure |
US11937422B2 (en) | 2015-11-07 | 2024-03-19 | Monolithic 3D Inc. | Semiconductor memory device and structure |
US10103069B2 (en) | 2016-04-01 | 2018-10-16 | X-Celeprint Limited | Pressure-activated electrical interconnection by micro-transfer printing |
US10222698B2 (en) | 2016-07-28 | 2019-03-05 | X-Celeprint Limited | Chiplets with wicking posts |
US11064609B2 (en) | 2016-08-04 | 2021-07-13 | X Display Company Technology Limited | Printable 3D electronic structure |
US11930648B1 (en) | 2016-10-10 | 2024-03-12 | Monolithic 3D Inc. | 3D memory devices and structures with metal layers |
US11251149B2 (en) | 2016-10-10 | 2022-02-15 | Monolithic 3D Inc. | 3D memory device and structure |
US11869591B2 (en) | 2016-10-10 | 2024-01-09 | Monolithic 3D Inc. | 3D memory devices and structures with control circuits |
US11812620B2 (en) | 2016-10-10 | 2023-11-07 | Monolithic 3D Inc. | 3D DRAM memory devices and structures with control circuits |
US11711928B2 (en) | 2016-10-10 | 2023-07-25 | Monolithic 3D Inc. | 3D memory devices and structures with control circuits |
US11329059B1 (en) | 2016-10-10 | 2022-05-10 | Monolithic 3D Inc. | 3D memory devices and structures with thinned single crystal substrates |
US10290574B2 (en) | 2017-01-18 | 2019-05-14 | Globalfoundries Inc. | Embedded metal-insulator-metal (MIM) decoupling capacitor in monolitic three-dimensional (3D) integrated circuit (IC) structure |
US10775429B2 (en) | 2017-09-27 | 2020-09-15 | Marvell Asia Pte., Ltd. | Testing monolithic three dimensional integrated circuits |
EP3525232A1 (en) * | 2018-02-09 | 2019-08-14 | Nexperia B.V. | Semiconductor device and method of manufacturing the same |
US11018156B2 (en) | 2019-04-08 | 2021-05-25 | Monolithic 3D Inc. | 3D memory semiconductor devices and structures |
US11158652B1 (en) | 2019-04-08 | 2021-10-26 | Monolithic 3D Inc. | 3D memory semiconductor devices and structures |
US11763864B2 (en) | 2019-04-08 | 2023-09-19 | Monolithic 3D Inc. | 3D memory semiconductor devices and structures with bit-line pillars |
US10892016B1 (en) | 2019-04-08 | 2021-01-12 | Monolithic 3D Inc. | 3D memory semiconductor devices and structures |
US11296106B2 (en) | 2019-04-08 | 2022-04-05 | Monolithic 3D Inc. | 3D memory semiconductor devices and structures |
US11387178B2 (en) | 2020-03-06 | 2022-07-12 | X-Celeprint Limited | Printable 3D electronic components and structures |
US11490519B2 (en) | 2021-01-11 | 2022-11-01 | X-Celeprint Limited | Printed stacked micro-devices |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0613576A (ja) * | 1990-07-31 | 1994-01-21 | Internatl Business Mach Corp <Ibm> | スタック形半導体構造体及びその形成方法 |
JP2004158537A (ja) * | 2002-11-05 | 2004-06-03 | Shinko Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP2005514767A (ja) * | 2001-12-19 | 2005-05-19 | インターナショナル・ビジネス・マシーンズ・コーポレーション | 垂直型接続部を使用したチップおよびウェハ集積方法 |
US20060057836A1 (en) * | 2004-09-10 | 2006-03-16 | Agency For Science, Technology And Research | Method of stacking thin substrates by transfer bonding |
JP2006522461A (ja) * | 2002-12-20 | 2006-09-28 | インターナショナル・ビジネス・マシーンズ・コーポレーション | 3次元デバイスの製造方法 |
Family Cites Families (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2617798B2 (ja) * | 1989-09-22 | 1997-06-04 | 三菱電機株式会社 | 積層型半導体装置およびその製造方法 |
US5102821A (en) * | 1990-12-20 | 1992-04-07 | Texas Instruments Incorporated | SOI/semiconductor heterostructure fabrication by wafer bonding of polysilicon to titanium |
US6714625B1 (en) * | 1992-04-08 | 2004-03-30 | Elm Technology Corporation | Lithography device for semiconductor circuit pattern generation |
US5426072A (en) * | 1993-01-21 | 1995-06-20 | Hughes Aircraft Company | Process of manufacturing a three dimensional integrated circuit from stacked SOI wafers using a temporary silicon substrate |
US6124179A (en) * | 1996-09-05 | 2000-09-26 | Adamic, Jr.; Fred W. | Inverted dielectric isolation process |
US5937312A (en) * | 1995-03-23 | 1999-08-10 | Sibond L.L.C. | Single-etch stop process for the manufacture of silicon-on-insulator wafers |
US5494849A (en) * | 1995-03-23 | 1996-02-27 | Si Bond L.L.C. | Single-etch stop process for the manufacture of silicon-on-insulator substrates |
US5844839A (en) * | 1995-07-19 | 1998-12-01 | Texas Instruments Incorporated | Programmable and convertible non-volatile memory array |
US5915167A (en) * | 1997-04-04 | 1999-06-22 | Elm Technology Corporation | Three dimensional structure memory |
US6130422A (en) * | 1998-06-29 | 2000-10-10 | Intel Corporation | Embedded dielectric film for quantum efficiency enhancement in a CMOS imaging device |
US6683380B2 (en) * | 2000-07-07 | 2004-01-27 | Texas Instruments Incorporated | Integrated circuit with bonding layer over active circuitry |
FR2819099B1 (fr) * | 2000-12-28 | 2003-09-26 | Commissariat Energie Atomique | Procede de realisation d'une structure empilee |
US6762076B2 (en) * | 2002-02-20 | 2004-07-13 | Intel Corporation | Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices |
US7668702B2 (en) | 2002-07-19 | 2010-02-23 | Applied Materials, Inc. | Method, system and medium for controlling manufacturing process using adaptive models based on empirical data |
KR100570514B1 (ko) * | 2004-06-18 | 2006-04-13 | 삼성전자주식회사 | 웨이퍼 레벨 칩 스택 패키지 제조 방법 |
JP2006013576A (ja) | 2004-06-22 | 2006-01-12 | Epson Toyocom Corp | Sawデバイスとこれを用いた装置 |
US7312487B2 (en) * | 2004-08-16 | 2007-12-25 | International Business Machines Corporation | Three dimensional integrated circuit |
US7432201B2 (en) * | 2005-07-19 | 2008-10-07 | Applied Materials, Inc. | Hybrid PVD-CVD system |
US20070122920A1 (en) * | 2005-11-29 | 2007-05-31 | Bornstein William B | Method for improved control of critical dimensions of etched structures on semiconductor wafers |
US20070207592A1 (en) * | 2006-03-03 | 2007-09-06 | Lu James J | Wafer bonding of damascene-patterned metal/adhesive redistribution layers |
US7648851B2 (en) * | 2006-03-06 | 2010-01-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of fabricating backside illuminated image sensor |
US7385283B2 (en) * | 2006-06-27 | 2008-06-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Three dimensional integrated circuit and method of making the same |
US7566632B1 (en) * | 2008-02-06 | 2009-07-28 | International Business Machines Corporation | Lock and key structure for three-dimensional chip connection and process thereof |
US8399336B2 (en) * | 2008-08-19 | 2013-03-19 | International Business Machines Corporation | Method for fabricating a 3D integrated circuit device having lower-cost active circuitry layers stacked before higher-cost active circuitry layer |
US8298914B2 (en) * | 2008-08-19 | 2012-10-30 | International Business Machines Corporation | 3D integrated circuit device fabrication using interface wafer as permanent carrier |
-
2008
- 2008-08-19 US US12/194,065 patent/US8129256B2/en active Active
-
2009
- 2009-06-18 TW TW098120386A patent/TWI514513B/zh not_active IP Right Cessation
- 2009-08-19 KR KR1020117001834A patent/KR101332076B1/ko not_active IP Right Cessation
- 2009-08-19 EP EP09808777.8A patent/EP2313923B1/en not_active Expired - Fee Related
- 2009-08-19 JP JP2011523964A patent/JP5285777B2/ja not_active Expired - Fee Related
- 2009-08-19 WO PCT/US2009/054333 patent/WO2010022163A1/en active Application Filing
-
2012
- 2012-02-16 US US13/398,505 patent/US8629553B2/en active Active
- 2012-02-16 US US13/398,481 patent/US8738167B2/en active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0613576A (ja) * | 1990-07-31 | 1994-01-21 | Internatl Business Mach Corp <Ibm> | スタック形半導体構造体及びその形成方法 |
JP2005514767A (ja) * | 2001-12-19 | 2005-05-19 | インターナショナル・ビジネス・マシーンズ・コーポレーション | 垂直型接続部を使用したチップおよびウェハ集積方法 |
JP2004158537A (ja) * | 2002-11-05 | 2004-06-03 | Shinko Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP2006522461A (ja) * | 2002-12-20 | 2006-09-28 | インターナショナル・ビジネス・マシーンズ・コーポレーション | 3次元デバイスの製造方法 |
US20060057836A1 (en) * | 2004-09-10 | 2006-03-16 | Agency For Science, Technology And Research | Method of stacking thin substrates by transfer bonding |
Also Published As
Publication number | Publication date |
---|---|
JP5285777B2 (ja) | 2013-09-11 |
EP2313923B1 (en) | 2018-11-21 |
US20100044826A1 (en) | 2010-02-25 |
WO2010022163A1 (en) | 2010-02-25 |
US20120149173A1 (en) | 2012-06-14 |
TWI514513B (zh) | 2015-12-21 |
KR20110042062A (ko) | 2011-04-22 |
EP2313923A1 (en) | 2011-04-27 |
EP2313923A4 (en) | 2013-02-20 |
US8629553B2 (en) | 2014-01-14 |
US8129256B2 (en) | 2012-03-06 |
US8738167B2 (en) | 2014-05-27 |
TW201017820A (en) | 2010-05-01 |
US20120153429A1 (en) | 2012-06-21 |
KR101332076B1 (ko) | 2013-11-22 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5285777B2 (ja) | 3次元集積回路の製造方法及びプログラム | |
JP5435593B2 (ja) | 3次元集積回路の製造方法及び記録媒体(インターフェース・ウエハを永久的キャリアとして使用する3次元集積回路デバイスの製造方法) | |
US8492869B2 (en) | 3D integrated circuit device having lower-cost active circuitry layers stacked before higher-cost active circuitry layer | |
US9613921B2 (en) | Structure to prevent solder extrusion | |
US7928549B2 (en) | Integrated circuit devices with multi-dimensional pad structures | |
CN104766806A (zh) | 晶圆三维集成的方法 | |
US9455214B2 (en) | Wafer frontside-backside through silicon via | |
US20130320359A1 (en) | Heterogeneous stack structures with optical to electrical timing reference distribution | |
US9236301B2 (en) | Customized alleviation of stresses generated by through-substrate via(S) | |
CN104766828A (zh) | 晶圆三维集成的方法 | |
US8912091B2 (en) | Backside metal ground plane with improved metal adhesion and design structures | |
CN112219276A (zh) | 一种芯片以及芯片封装方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20120329 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20130110 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20130122 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20130419 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20130514 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20130531 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
LAPS | Cancellation because of no payment of annual fees |