TWI512929B - 具有暴露之導體的積體電路封裝系統及其製造方法 - Google Patents
具有暴露之導體的積體電路封裝系統及其製造方法 Download PDFInfo
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Description
本專利申請案包含與同時在2010年2月26日提出申請之美國專利申請案第12/714,291號之相關的內容。該相關申請案係讓渡予史特斯晶片封裝公司(STATS ChipPAC Ltd)。該相關申請案之內容係併入本說明書作為參考。
一般而言,本發明係關於積體電路封裝系統,更具體而言,係關於具有暴露之導體的封裝件系統。
為了成功,產品必須於全球市場中競爭,並且吸引許多消費者或買家。對於產品而言,在降低產品成本、產品尺寸的同時,持續改善特徵、效能、及可靠度是非常重要的,且能夠被消費者或買家迅速購買獲得也同樣重要。
高密度及高輸出/輸入之積體電路封裝件的市場成長已經造成電子產品輕量化、尺寸更小、功能更多的趨勢,且伴隨著速度的持續增進。電子產品(如以行動電話為基礎的產品、全球定位系統(Global Positioning System;GPS)、衛星、通訊設備、消費性產品、及其他大量的相似產品)的全球性需求正不斷增加。
因此,對於較小的封裝件有著相當重要的需求。較小的封裝件必須與其他部份及組件進行電性連接。當具有更多電路的較小的封裝件持續縮減尺寸時,必須製造具有更多封裝件連接器的較小的封裝件,以支援連接至及連接自那些較小的封裝件的持續增加的電性連接的數量。
因此,當封裝件的尺寸持續縮減且封裝件內部的電路持續增加的同時,增加封裝件的電性連接之需求仍持續增加。同樣關鍵的是,該等電性連接經精確地產生及放置,使得各個電性連接彼此互相間隔開。該較小的封裝件及其電性連接必須能夠連接至電路板,並且實現功能性、速度、及效能的增進。有鑑於經濟及技術上的挑戰,對於這些問題的答案的尋求也益形關鍵。
有鑑於持續增加的商業競爭壓力,伴隨著消費者期望的成長及市場上有意義的產品區隔機會越來越縮減,對於這些問題的答案的尋求也益形關鍵。此外,降低成本、改善可靠度及產品良率以達到競爭壓力的需求,使得尋求這些問題的答案的必要性顯得更加迫切且必要。
先前對於這些已經長期為人們所思索的問題的研究並未能夠教示或建議任何解決方案,因此這些問題的解決方案已長期困惑所屬技術領域中具有通常知識者。
本發明提供一種製造積體電路封裝系統的方法,包含:設置基板;於該基板上形成組件連接器;於該基板上形成抗蝕層(resist layer),且暴露出該組件連接器;於該抗蝕層中形成垂直注入腔(vertical insertion cavity),該垂直注入腔與該組件連接器或另外的垂直注入腔隔離,該垂直注入腔具有與該基板垂直之腔側(cavity side);於該垂直注入腔中形成圓形互連件,該圓形互連件與該垂直注入腔非共形(nonconformal);以及,於該組件連接器上接置積體電路裝置。
本發明提供一種積體電路封裝系統,包含:基板;組件連接器,係位於該基板上;抗蝕層,係具有垂直注入腔並位於該基板上,該組件連接器自該抗蝕層暴露,該垂直注入腔與該組件連接器或另外的垂直注入腔隔離,該垂直注入腔具有與該基板垂直之腔側;圓形互連件,係位於該垂直注入腔中,且與該垂直注入腔非共形;以及,積體電路裝置,係位於該組件連接器上。
本發明之特定實施例除了上述步驟或元件以外具有其他步驟或元件或者可以其他步驟或元件替代上述步驟或元件。對於所屬技術領域中具有通常知識者而言,當參照附加圖式並藉由閱讀以下詳細說明書內容將更清楚明瞭該等步驟或元件。
以下實施例係經充分詳細描述,以使得所屬技術領域中具有通常知識者能夠製造並使用本發明。應了解到,基於本發明所揭露之內容,其他實施例將變得清楚明瞭,且可完成所述之系統、製程、或機械變化而不背離本發明之範疇。
於以下說明書中,給定許多特定細節以助於透徹了解本發明。然而,將清楚了解到,無須這些特定細節亦可實現本發明。為了避免混淆本發明,並未詳細揭露一些眾所周知的電路、系統組構、及製程步驟。
顯示系統之實施例之圖式係半概略式的,且並未依據比例繪示,具體而言,為了清楚起見,一些尺寸於圖式中係以誇張的尺寸顯示。相似地,儘管為了便於說明起見,該等圖式一般而言係以相似的定向顯示,但是在大部份情況下,圖式中所示係為任意定向。一般而言,本發明可操作於任何定向。
本發明所揭露及描述的多個實施例具有一些共同的特徵,為了清楚起見及便於說明、描述及理解,彼此相似及類似的特徵將通常以類似的參考編號進行描述。為了方便說明,實施例已編號為第一實施例、第二實施例等,且並非意指具有任何其他含意或對本發明作出限制。
為了說明起見,本說明書中所使用的名詞「水平」係定義為平行本發明之平面或表面之平面,而與其定向無關。該名詞「垂直」係指元件之方向垂直或垂直於另一元件。如「在…下方(below)」、「底部(bottom)」、「頂部(top)」、「側邊(side)」(如同「側壁(sidewall)」)、「較高(higher)」、「下側(lower)」、「上側(upper)」、「上方(over)」、「低於(under)」之名詞係相對於該水平平面所定義。
名詞「在…上(on)」意指元件之間有直接接觸。名詞「直接位在…上(directly on)」意指一個元件與另一元件之間有直接接觸,而無中介元件(intervening element)。
名詞「主動側(active side)」係指於其上製造有主動電路系統的晶粒(die)、模組、封裝件、或電子結構之側,或者指於該晶粒、該模組、該封裝件、或該電子結構內具有用於連接至該主動電路系統的元件之側。本說明書中所使用的名詞「處理(processing)」包含形成上述結構所需之沉積材料或光阻(photoresist)、圖案化(patterning)、曝光(exposure)、顯影(development)、蝕刻(etching)、清潔、及/或移除該材料或光阻。
現在請參照第1圖,顯示本發明之第一實施例中積體電路封裝系統100沿著第2圖之線1--1之剖面圖。較佳的情況是,該積體電路封裝系統100可包含基板102。
該基板102可包含暴露於該基板102之組件側106及該基板102相對該組件側106之側上之基底導體(base conductor)104。可利用導電性材料形成該基底導體104,並且於該基板102的側邊之間提供連接能力(connectivity)。
組件連接器108提供連接至該基板102之連接能力,並且可利用導電性材料來形成。該等組件連接器108可接置於暴露於該組件側106上之基底導體104上,並且可經定位於該基板102之組件區域(component region)110內。該組件區域110係定義為該基板102之組件側106上之區域,用於將其他組件接置及附接於該基板102上,如稍後所述者。
為了說明起見,該組件區域110係顯示為位於該基板102之中心部份(center portion)上。該組件區域110可位於該組件側106上之其他位置。舉例而言,該組件區域110可經定位為對該基板102之一側具有偏移(offset)或者經定位為沿著該基板102之一側。
較佳的情況是,抗蝕層112可覆蓋該組件區域110外側之組件側106之部份,並且暴露該基板102上之組件連接器108。該抗蝕層112係利用固化材料(curable material)而形成於該組件側106上之以永久樹脂為基礎之塗料(permanent resin based coating),該固化材料包含光敏(photo sensitive)、熱敏(thermo sensitive)、或化學敏感材料。該組件區域110內之組件側106及該組件區域110係自該抗蝕層112暴露出來。
該抗蝕層112的範例係與層疊基板(laminated substrate)相關之阻焊(solder resist),該層疊基板係該基板102之範例。該抗蝕層112可用以保護該基底導體104、用以保護該組件側106、及用以對該基板102提供熱及結構剛性(thermal and structural rigidity)。
垂直注入腔114可形成於該抗蝕層112中,以暴露該抗蝕層112下方該基板102之基底導體104。該抗蝕層112之腔側116(形成該垂直注入腔114之邊界)可垂直於該基板102之組件側106。具有該腔側116之垂直注入腔114實質上可與該基板102之組件側106垂直,並且與該組件連接器108隔離或者與彼此互相隔離。
圓形互連件120可形成並接置於該基底導體104上,並且定位於該抗蝕層112之垂直注入腔114內側。該等圓形互連件120係由具有恢復性質(restorative property)及實質上表面張力(surface tension)的材料所形成之電性互連件。該恢復性質及該表面張力提供相互分子接著力(mutual molecular cohesive force),使得該等圓形互連件120具有不超過兩個接著表面(cohesive surface)122。
任何接著表面122皆為具有圓形、橢圓形、或彎曲形狀其中一者之單一輪廓形狀(single profile shape)之表面。該圓形互連件120之接著表面122並不符合任何垂直注入腔114之內部形狀(interior shape)。
該等圓形互連件120不符合該垂直注入腔114且與該垂直注入腔114非共形的結果係由於熱變異所造成該抗蝕層112與該等圓形互連件120之間的移動消弭轉移(dampened transference of movement)。該移動消弭轉移造成對該等圓形互連件120或該抗蝕層112之結構性應力(structural stress)的降低。
該圓形互連件120之接著表面122之部份可自該抗蝕層112暴露出來,以於電子組件(未顯示)及該積體電路封裝系統100之間提供電性連接能力。在該恢復性質恢復之前,該圓形互連件120可經施加、經分佈、經接置、或經附接至該基底導體104。
具有主動側之積體電路裝置124可於鄰近該抗蝕層112且位於該抗蝕層112之暴露側下方的組件區域110中接置於該等組件連接器108上。該積體電路裝置124之主動側係接置於該組件連接器108上,以於該積體電路裝置124與該基板102之間提供電性連接能力。
底部填充(underfill)126可施加於該等組件連接器108周圍以及該積體電路裝置124與該基板102之間。該底部填充126係使用於該積體電路裝置124與該基板102之間用以保護該等組件連接器108與該積體電路裝置124免於受損的材料。該底部填充126並未完全覆蓋該積體電路裝置124且經限定於該主動側上。
可包含導電球、接腳、或引腳(lead)之系統連接器128可接置於經暴露於該基板102相對該組件側106之側上之基底導體104上。該系統連接器可用以於該積體電路封裝系統100及另一電子組件之間提供連接能力。
已發現到,本發明提供具高度連接能力之結構予該積體電路封裝系統100。該抗蝕層112之垂直注入腔114中的圓形互連件120提供高密度電性連接能力,係達到具高度連接能力之結構。由於該抗蝕層112作為該等圓形互連件120之間的阻障,故垂直注入腔114中的圓形互連件120亦縮減了遮擋區(keep out zone),且該遮擋區之縮減進一步增加了該圓形互連件120之密度,係進一步提供了具高度連接能力之結構。
也已經發現到,本發明提供該積體電路封裝系統100具有更好的可靠度及更高的良率。具有該垂直注入腔114之抗蝕層112係在避免翹曲(warpage)與機械性損害的同時,改善表面接置技術的良率。翹曲的減少亦改善了該積體電路封裝系統100之可靠度。
現在請參照第2圖,顯示第1圖之積體電路封裝系統100之頂面圖。第2圖係顯示該積體電路裝置124、該底部填充126、該組件側106、該抗蝕層112、及該接著表面122。該底部填充126係顯示為超過位於該組件側106上之積體電路裝置124的側邊。
該抗蝕層112係顯示為形成於該底部填充126的周圍,並且藉由該組件側106而與該底部填充126相分隔。該接著表面122係顯示為暴露於該抗蝕層112之垂直注入腔114內。
該等圓形互連件120之接著表面122之部份可形成為相對於該腔側116或該組件側106暴露於該垂直注入腔114內之區域且並未與該腔側116或該組件側106暴露於該垂直注入腔114內之區域接觸。相對於且未與該腔側116或該組件側106接觸的接著表面122的部份間的三維區域可定義為腔間隙(cavity gap)202。
該腔間隙202係顯示為介於該圓形互連件120與該腔側116之間。該等腔間隙202於該圓形互連件120與該抗蝕層112之間降低或消弭熱或機械結構性應力。
已經發現到,本發明之積體電路封裝系統100顯著地改善了對流熱散逸(convection thermal dissipation)。對於自該基板102之熱散逸而言,該垂直注入腔114係垂直的是重要的。該腔側116之垂直輪廓容許該圓形互連件120黏接於該腔側116,同時該圓形互連件120之表面張力幫助形成該圓形互連件120之圓形組構。此圓形組構造成該圓形互連件120與該腔側116及該基板102之間的腔間隙202。當該積體電路裝置124產生熱時,一些熱係轉移至該基板102,主要係透過該基板102中的傳導路徑。這些傳導路徑通往該等垂直注入腔114。由該腔側116與該圓形互連件120之垂直輪廓所產生的腔間隙202容許透過垂直注入腔114自該基板102對流熱散逸,藉此提供熱管理解決方案。缺少該腔側116及該圓形互連件120之垂直輪廓可能無法具有形成該腔間隙202所需的表面黏接性(surface adhesion),而缺少該腔間隙202可能無法透過該垂直注入腔114進行對流熱散逸。
也已經發現到,本發明之積體電路封裝系統100顯著地改善了機械性配對與擬合(mechanical mating and fit)。該垂直注入腔114之腔側116之垂直輪廓容許沿著至少兩個面對面之腔側116的機械性壓力擬合(press fit),藉此加強與該等圓形互連件120及來自接置裝置(未顯示)的任何電性連接器之機械接合(mechanical bond)。當幾何結構越來越小且輸入/輸出密度越來越高時,來自該圓形互連件120用以形成焊接點(solder joint)所需之堅硬且可靠的金屬間化合物(intermetallic compound;IMC)(未顯示)之表面面積越來越小。該腔側116於該圓形互連件120加強該IMC之機械約束(mechanical bound),形成與接置裝置的更可靠之互連件,同時仍然容許增加該圓形互連件120之輸入密度、輸出密度、及縮減尺寸。
現在請參照第3圖,顯示第1圖於製造之連接器附接階段中之結構。於該連接器附接階段期間,該等電性連接器302可形成且接置於經暴露於該組件側106上之基底導體104上。該連接器附接階段可包含該基板102上方之組件連件器之印刷及回焊(reflow)製程。
現在請參照第4圖,顯示第3圖於基板塗佈(substrate coating)階段中之結構。於該基板塗佈階段期間,該遮罩層402可覆蓋該組件側106之部份且未覆蓋該基板102上之組件區域110。該基板塗佈階段可包含光敏層塗佈製程(photosensitive layer coating process)。
現在請參照第5圖,顯示第4圖於塗佈移除階段中之結構。藉由第4圖之遮罩層402,該抗蝕層112可經形成為具有腔側116。於該塗佈移除階段期間,該等腔側116形成該垂直注入腔114之側邊界(side boundary),以暴露該基板102之基底導體104。該塗佈移除階段可包含正抗蝕或負抗蝕移除製程。
已經發現到,能夠以相較於利用環氧鑄模化合物(epoxy molding compound)之相似製程流程更有彈性且更快速的製程流程來形成具有該垂直注入腔114之抗蝕層112。具有該垂直注入腔114之抗蝕層112同時提供用於焊接之焊接遮罩(solder mask)及環氧鑄模化合物之功能性的優勢。
現在請參照第6圖,顯示第5圖於組裝注入階段中之結構。於該互連件注入階段(interconnect insertion phase)期間,具有提供實質上表面張力之恢復性質的導電性材料602可經注入該垂直注入腔114中。該互連件注入階段可包含焊錫注入(solder injection)、印刷、或者球落下(ball dropping)製程。
現在請參照第7圖,顯示第6圖於回焊階段中之結構。於該回焊階段期間,具有該接著表面122之圓形互連件120可經形成且經連接於經暴露於該垂直注入腔114下方該組件側106上之基底導體104上。
於該回焊階段期間,具有該接著表面122之圓形互連件120可由導電性材料602所形成,並且經接置且經連接於該基底導體104上。該回焊階段可包含利用回焊爐夾具(reflow oven fixture)、紅外線燈(infrared lamp)、或熱空氣排放器的控制加熱製程,並且於圓形互連件1420及該垂直注入腔114所暴露的基底導體104之間形成電性連接能力。
現在請參照第8圖,顯示第7圖於壓印階段(coining phase)中之結構。於該壓印階段期間,該基板102之組件區域110內之第3圖之電性連接器302可經壓印或經壓平,以形成該等組件連接器108。該壓印階段可包含沖壓(stamping)、下壓、或冷加工(cold-working)製程。
現在請參照第9圖,顯示第8圖於材料分配階段(material dispensing phase)中之結構。該積體電路裝置124係顯示為經定向於該組件區域110上方,且經接置於附接於該組件側106上之組件連接器108上。該系統連接器128係顯示為連接至暴露於該基板102相對該組件側106之側上之基底導體104。
於該材料分配階段期間,該底部填充126可圍繞該組件連接器108。該材料分配階段可包含利用注入、分配、加熱製程、或前述製程之任何組合來施加共形填充材料(conformal fill material)。
已經發現到,該抗蝕層112可避免該底部填充126滲入該抗蝕層112之垂直注入腔114及污染該垂直注入腔114。避免污染該垂直注入腔114於該圓形互連件120與該基板102之間形成了堅固且可靠的電性連接能力。
現在請參照第10圖,顯示本發明之第二實施例中積體電路封裝系統1000之剖面圖。較佳的情況是,該積體電路封裝系統1000可包含該積體電路封裝系統100。
密封體(encapsulation)1002可用以密封且覆蓋該積體電路裝置124、該底部填充126、及該基板102之組件區域110。該密封體1002可符合該基板102之組件區域110、該積體電路裝置124、該底部填充126、及該抗蝕層112之垂直側,以提供防止損壞的額外保護。
已經進一步發現到,該密封體1002及具有該垂直注入腔114之抗蝕層112在防止翹曲及機械性損壞的同時,改善表面接置技術的良率。
已經發現到,本發明提供具有改善之可靠度之積體電路封裝系統1000。該抗蝕層112內的密封體1002防止直接於該組件區域110下方的移動或該基板102之彎曲,藉此緩和或消除可能降低可靠度的翹曲。
現在請參照第11圖,顯示本發明之實施例中製造積體電路封裝系統之方法1100之流程圖。該方法1100包含:於步驟1102中,設置基板;於步驟1104中,於該基板上形成組件連接器;於步驟1106中,於該基板上形成抗蝕層,且暴露出該組件連接器;於步驟1108中,於該抗蝕層中形成垂直注入腔,該垂直注入腔與該組件連接器或另外的垂直注入腔隔離,該垂直注入腔具有與該基板垂直之腔側;於步驟1110中,於該垂直注入腔中形成圓形互連件,該圓形互連件與該垂直注入腔非共形;以及,於步驟1112中,於該組件連接器上接置積體電路裝置。
所產生的方法、製程、設備、裝置、產品、及/或系統係易懂的、具成本效益的、不複雜的、多功能且有效的,可令人意外地且非顯而易見地藉由習知技術實現得到,並且因此容易地完全相容於傳統製造方法或製程與技術而有效率且經濟地於封裝件系統中製造封裝件。
本發明的另一個重要態樣係能夠有益地支持並維護降低成本、簡化系統、及增進效能的歷史趨勢。
本發明的這些及其他有益態樣,使得本領域之技術狀態邁入至少下一層次。
儘管已結合特定的最佳實施方式對本發明進行描述,但是應了解到,對於所屬技術領域中具有通常知識者而言,有鑑於上述說明書內容將清楚了解本發明的許多變動、修改、及變化形式。因此,本發明意圖涵蓋落入本發明申請專利範圍之範圍內的所有此類變動、修改、及變化形式。到目前為止,本說明書中所提及或附加圖式中所顯示的所有事項應理解成作為說明之目的,而並非限定本發明。
1─1...線
100、1000...積體電路封裝系統
102...基板
104...基底導體
106...組件側
108...組件連接器
110...組件區域
112...抗蝕層
114...垂直注入腔
116...腔側
120...圓形互連件
122...接著表面
124...積體電路裝置
126...底部填充
128...系統連接器
202...腔間隙
302...電性連接器
402...遮罩層
602...導電性材料
1002...密封體
1100...方法
1102、1104、1106、1108、1110、1112...步驟
第1圖係本發明之第一實施例中積體電路封裝系統沿著第2圖之線1--1之剖面圖;
第2圖係第1圖之積體電路封裝系統之頂面圖;
第3圖係第1圖於製造之連接器附接階段中之結構;
第4圖係第3圖於基板塗佈階段中之結構;
第5圖係第4圖於塗佈移除階段中之結構;
第6圖係第5圖於組裝注入階段中之結構;
第7圖係第6圖於回焊階段中之結構;
第8圖係第7圖於壓印階段中之結構;
第9圖係第8圖於材料分配階段中之結構;
第10圖係本發明之第二實施例中積體電路封裝系統之剖面圖;以及
第11圖係本發明之實施例中製造積體電路封裝系統之方法之流程圖。
100...積體電路封裝系統
102...基板
104...基底導體
106...組件側
108...組件連接器
110...組件區域
112...抗蝕層
114...垂直注入腔
116...腔側
120...圓形互連件
122...接著表面
124...積體電路裝置
126...底部填充
128...系統連接器
Claims (10)
- 一種製造積體電路封裝系統之方法,包括:設置基板;於該基板上形成組件連接器;於該基板上形成抗蝕層,且暴露出該組件連接器;於該抗蝕層中形成垂直注入腔,該垂直注入腔與該組件連接器或另外的垂直注入腔隔離,該垂直注入腔具有與該基板垂直之腔側;於該垂直注入腔中形成結合該腔側之圓形互連件,且產生暴露該基板之腔間隙於該圓形互連件與對應未接觸該圓形互連件的該腔側之間;以及於該組件連接器上接置積體電路裝置。
- 如申請專利範圍第1項所述之製造積體電路封裝系統之方法,其中,形成該圓形互連件包含形成具有具彎曲形狀之接著表面之該圓形互連件。
- 如申請專利範圍第1項所述之製造積體電路封裝系統之方法,其中,接置該積體電路裝置包含將該積體電路裝置接置於鄰近該抗蝕層。
- 如申請專利範圍第1項所述之製造積體電路封裝系統之方法,其中,形成該圓形互連件包含形成該圓形互連件之部份,該圓形互連件之該部份位於該抗蝕層及該基板對面,且未與該抗蝕層及該基板接觸。
- 如申請專利範圍第1項所述之製造積體電路封裝系統之方法,復包括於該積體電路裝置上方施加密封體。
- 一種積體電路封裝系統,包括:基板;組件連接器,係位於該基板上;抗蝕層,係具有垂直注入腔並位於該基板上,該組件連接器自該抗蝕層暴露,該垂直注入腔與該組件連接器或另外的垂直注入腔隔離,該垂直注入腔具有與該基板垂直之腔側;圓形互連件,係位於該垂直注入腔中並結合該腔側,且具有暴露該基板之腔間隙於該圓形互連件與對應未接觸該圓形互連件的該腔側之間;以及積體電路裝置,係位於該組件連接器上。
- 如申請專利範圍第6項所述之積體電路封裝系統,其中,該圓形互連件包含具有具彎曲形狀之接著表面之該圓形互連件。
- 如申請專利範圍第6項所述之積體電路封裝系統,其中,該積體電路裝置包含接置於鄰近該抗蝕層之該積體電路裝置。
- 如申請專利範圍第6項所述之積體電路封裝系統,其中,該圓形互連件包含該圓形互連件之部份,該圓形互連件之該部份位於該抗蝕層及該基板對面,且未與該抗蝕層及該基板接觸。
- 如申請專利範圍第6項所述之積體電路封裝系統,復包括位於該積體電路裝置上方之密封體。
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US8633100B2 (en) * | 2011-06-17 | 2014-01-21 | Stats Chippac Ltd. | Method of manufacturing integrated circuit packaging system with support structure |
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KR20230132883A (ko) | 2016-10-04 | 2023-09-18 | 스카이워크스 솔루션즈, 인코포레이티드 | 오버몰드 구조체를 갖는 양면 라디오-주파수 패키지 |
US10586716B2 (en) | 2017-06-09 | 2020-03-10 | Advanced Semiconductor Engineering, Inc. | Semiconductor device package |
US10217649B2 (en) * | 2017-06-09 | 2019-02-26 | Advanced Semiconductor Engineering, Inc. | Semiconductor device package having an underfill barrier |
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US8409920B2 (en) * | 2007-04-23 | 2013-04-02 | Stats Chippac Ltd. | Integrated circuit package system for package stacking and method of manufacture therefor |
KR100811034B1 (ko) * | 2007-04-30 | 2008-03-06 | 삼성전기주식회사 | 전자소자 내장 인쇄회로기판의 제조방법 |
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