TWI497666B - 先進四方扁平無引腳封裝的表面黏著技術製程及其使用的模板 - Google Patents

先進四方扁平無引腳封裝的表面黏著技術製程及其使用的模板 Download PDF

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TWI497666B
TWI497666B TW101143378A TW101143378A TWI497666B TW I497666 B TWI497666 B TW I497666B TW 101143378 A TW101143378 A TW 101143378A TW 101143378 A TW101143378 A TW 101143378A TW I497666 B TWI497666 B TW I497666B
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Taiwan
Prior art keywords
solder paste
quad flat
wafer pad
openings
circuit board
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TW101143378A
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English (en)
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TW201322392A (zh
Inventor
Chih Tai Hsu
Nan Cheng Chen
Chih Ming Chiang
Hung Chang Hung
Xin Zhong
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Mediatek Singapore Pte Ltd
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Publication of TW201322392A publication Critical patent/TW201322392A/zh
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Publication of TWI497666B publication Critical patent/TWI497666B/zh

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    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
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    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49144—Assembling to base an electrical component, e.g., capacitor, etc. by metal fusion
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/53—Means to assemble or disassemble
    • Y10T29/5313—Means to assemble electrical device
    • Y10T29/53174—Means to fasten electrical component to wiring board, base, or substrate

Description

先進四方扁平無引腳封裝的表面黏著技術製程及其使用的模板
本發明係有關於一種先進四方扁平無引腳封裝的表面黏著技術及其使用的模板，特別係有關於一種先進四方扁平無引腳封裝的晶片墊的焊點設計。
先進四方扁平無引腳封裝(advanced quad flat no-lead(aQFN)package，以下簡稱aQFN封裝)為具有不需引腳、多列及精細間距導線架的封裝體，其具有厚度小、腳位面積小(small footprint)、重量輕和不受限於輸入/輸出(I/O)配置設計等優點，因而具有傑出的電性能和熱性能。aQFN封裝可使用做為高產量、對價格敏感的客戶端應用，例如電信產品、可攜式產品、消費產品和中引腳數封裝體(medium lead count package)。並且，因為aQFN封裝以銅線取代金線，所以具有明顯的成本優勢。aQFN封裝可以因為低線材成本而增加價格上的競爭力。
然而，aQFN封裝與印刷電路板(PCB)的表面黏著技術(surface mount technology，以下簡稱SMT)的製程可靠度會遭受位於aQFN封裝的晶片墊(die pad)/接觸端子(引腳)和印刷電路板之間的焊點(solder joint)的應力影響，因而導致焊點破裂問題。
在此技術領域中，需要一種先進四方扁平無引腳封裝的表面黏著技術，以改善上述缺點。
有鑑於此，本發明提供一種先進四方扁平無引腳封裝的表面黏著技術製程及其使用的模板。
本發明一實施例係提供一種先進四方扁平無引腳封裝的表面黏著技術製程，包括提供一印刷電路板；於上述印刷電路板的一頂面上架設一模板，其具有複數個第一開孔；將一錫膏印刷穿過上述些第一開孔，以於上述印刷電路板的上述頂面上形成複數個第一錫膏圖案；移開上述模板；進行一零件黏貼製程，將一先進四方扁平無引腳封裝置於上述印刷電路板的上述頂面上，其中上述先進四方扁平無引腳封裝包括一晶片墊，具有一上表面和一下表面；以及複數個接觸端子，圍繞上述晶片墊；其中上述些第一錫膏圖案接觸上述晶片墊的上述下表面，其中上述些第一開孔和上述晶片墊的上述下表面的面積比例介於1：2和1：10之間；以及進行一回焊製程，以熔化上述些第一錫膏圖案成為一第一液化錫膏，其中上述第一液化錫膏的一部分圍繞上述晶片墊的一側壁，其中該模板具有與該些第一開孔隔離的複數個第二開孔，並且於該印刷電路板的該頂面上形成該些第一錫膏圖案期間更包括將該錫膏印刷穿過該些第二開孔，以分別於該印刷電路板的該頂面上形成複數個第二錫膏圖案。
本發明另一實施例係提供一種先進四方扁平無引腳封裝的表面黏著技術製程使用的模板，包括一鋼薄板，具有一中間區域和圍繞上述中間區域的一周圍區域；複數個第一開孔，穿過上述鋼薄板，且位於上述中間區域中，其中 上述些第一開孔的位置對應至一先進四方扁平無引腳封裝的一晶片墊的位置，且上述些第一開孔和上述晶片墊與一印刷電路板接觸的一表面的面積比例介於1：2和1：10之間；以及複數個第二開孔，穿過該鋼薄板，且位於該周圍區域中，其中當該模板架設於該先進四方扁平無引腳封裝的上方時，該些第二開孔的位置分別對應至該先進四方扁平無引腳封裝的複數個接觸端子的位置。
本發明實施例提供之先進四方扁平無引腳封裝的表面黏著技術製程及其使用的模板能藉由控制模板之設計對應至晶片墊的開孔和晶片墊的下表面兩者的總面積比例，使其錫膏總量少於習知技術之完全覆蓋晶片墊下表面的錫膏圖案的錫膏總量。並且，在本發明實施例之表面黏著技術，可以提升aQFN封裝的機械強度。
以下以各實施例詳細說明並伴隨著圖式說明之範例，做為本發明之參考依據。在圖式或說明書描述中，相似或相同之部分皆使用相同之圖號。且在圖式中，實施例之形狀或厚度可擴大，並以簡化或方便標示。再者，圖式中各元件之部分將以分別描述說明之，值得注意的是，圖中未繪示或描述之元件，為所屬技術領域中具有通常知識者所知的形式，另外，特定之實施例僅為揭示本發明使用之特定方式，其並非用以限定本發明。
第1圖為本發明一實施例之四方扁平無引腳封裝(advanced quad flat no-lead(aQFN)package，以下簡稱 aQFN封裝)500的剖面圖。如第1圖所示，aQFN封裝500包括一晶片墊(die pad)200，位於aQFN封裝500的中間區域中，晶片墊200具有一上表面204和一下表面206。晶片墊200的上表面204係凹陷形成一凹槽202，用以使一晶片208設置於其中。晶片208可藉由一黏著層240貼附至凹槽202的底面238。而晶片墊200的上表面204和下表面206上分別設置金屬層212和214。晶片墊200包括一上方側壁210和一下方側壁216，分別與上表面204和下表面206鄰接。注意晶片墊200的上方側壁210和下方側壁216分別朝上表面204和下表面206傾斜。aQFN封裝500更包括獨立的接觸端子(引腳)218，圍繞晶片墊200。在本發明一實施例中，接觸端子(引腳)218係以排列為具有最小間距(pitch)P1的一陣列。每一個接觸端子(引腳)218係具有一上表面220和一下表面222，而每一個接觸端子(引腳)218的上表面220和下表面222上分別設置金屬層224和226。注意每一個接觸端子(引腳)218的上方側壁240和下方側壁242分別朝上表面220和下表面222傾斜。晶片208具有接合墊236設置於其上，用以做為輸入/輸出(I/O)連接。導線228係電性連接接合墊236和晶片墊200的金屬層212，以及接觸端子(引腳)218的金屬層224。在本發明一實施例中，晶片墊200和接觸端子(引腳)218係藉由對單一金屬(例如銅)載板進行蝕刻和切割製程而形成。aQFN封裝500更包括一封膠模蓋(mold cap)230，覆蓋晶片墊200與接觸端子(引腳)218的上部、晶片208和導線228。
第2圖為本發明一實施例之先進四方扁平無引腳封裝 500的底視圖。aQFN封裝500的晶片墊200之被第2圖所示的金屬層214覆蓋的下表面206(如第1圖所示)的面積遠大於每一個接觸端子(引腳)218之被第2圖所示的金屬層226覆蓋的下表面222(如第1圖所示)的面積。在本發明一實施例中，晶片墊200可視為晶片208的一散熱墊(thermal pad)或一接地墊(ground pad)。另外，aQFN封裝500更包括用於對準製程的一對準標記232。而且，對準標記232具有一金屬層244，塗佈於其底面上。
第3~7圖為本發明一實施例之先進四方扁平無引腳封裝500的表面黏著技術之製程。如第3圖所示，首先，提供一印刷電路板262。在本發明一實施例中，印刷電路板(PCB)262可包括一散熱墊(thermal pad)/接地墊(ground pad)266及數個各自獨立的接合墊264(例如訊號墊或電源墊)。如第3圖所示的aQFN封裝500係用以顯示aQFN封裝500之接觸端子(引腳)218位置與印刷電路板(PCB)262之各自獨立的接合墊264位置之間的關係，以及aQFN封裝500之晶片墊200位置與印刷電路板(PCB)262之散熱墊(thermal pad)/接地墊(ground pad)266位置之間的關係。如第3圖所示，印刷電路板(PCB)262之各自獨立的接合墊264的位置分別對應至aQFN封裝500之接觸端子(引腳)218的位置，且印刷電路板(PCB)262之散熱墊(thermal pad)/接地墊(ground pad)266位置對應至aQFN封裝500之晶片墊200的位置。
接著，於印刷電路板262的頂面261上方架設具有複數個第一開孔406和複數個第二開孔408的一模板400。 模板400係用於後續錫膏印刷製程期間，分別在印刷電路板262的散熱墊/接地墊266及各自獨立的接合墊264上形成複數個錫膏圖案。因此，如第3圖所示，第一開孔406大體上對準印刷電路板262的散熱墊/接地墊266，且第二開孔408大體上分別對準印刷電路板262的各自獨立的接合墊264。
第8圖為本發明一實施例之先進四方扁平無引腳封裝500的表面黏著技術使用的模板400的上視圖。如第3、8圖所示，模板400包括一鋼薄板450，具有一中間區域402和圍繞中間區域402的一周圍區域404。在本發明一實施例中，中間區域402係對應至印刷電路板262的散熱墊/接地墊266的佔據位置，且周圍區域404對應至印刷電路板262的各自獨立的接合墊264的佔據位置。如第8圖所示，模板400包括穿過鋼薄板450的複數個第一開孔406，且位於中間區域402中。第一開孔406係彼此隔離。並且設計第一開孔406的位置大體上對應於aQFN封裝500之晶片墊200的位置(如第1圖所示)。在本發明一實施例中，第一開孔406的總面積係設計等於印刷電路板262的散熱墊/接地墊266的總面積，但小於aQFN封裝500之晶片墊200的下表面206的總面積。在本發明一實施例中，第一開孔406的總面積與晶片墊200的下表面206(如第1圖所示)的總面積的面積比例介於1：2和1：10之間。上述模板400更包括穿過鋼薄板450的複數個第二開孔408，且位於周圍區域404中。如第8圖所示，在本發明一實施例中，第二開孔408排列為具有最小間距(pitch)P2的一陣列。並 且，第二開孔408的位置係設計分別對應至aQFN封裝500的接觸端子(引腳)218(如第1圖所示)的位置。因此，第二開孔408之間具有一最小間距P2，其等於接觸端子(引腳)218之間的最小間距P1。在本發明一實施例中，每一個第二開孔408與印刷電路板262的每一個各自獨立的接合墊264和每一個接觸端子(引腳)218的下表面222可具有大體上相同的形狀和面積。在本發明一實施例中，每一個第二開孔408和印刷電路板262的每一個各自獨立的接合墊264與aQFN封裝500的每一個接觸端子(引腳)218的下表面222的面積比例約為1：1。在本發明其他實施例中，可設計每一個第二開孔408的面積小於印刷電路板262的每一個各自獨立的接合墊264，同時也小於aQFN封裝500的每一個接觸端子(引腳)218的下表面222的面積。
第9a~9d圖顯示本發明一實施例之模板400(如第8圖所示)的第一開孔的不同設計。在本發明一實施例中，第一開孔406的數量可以大於二。如第9a圖所示，在本發明一實施例中，可設計兩個三角形的第一開孔406a，且兩個三角形的第一開孔406a的底邊為彼此相對。在本發明一實施例中，數量大於二的第一開孔406可排列為一陣列。如第9b、9c、9d圖所示的第一開孔406b、406c、406d可分別排列為2x2、4x4、8x8陣列。注意第一開孔406的數量和形狀係依據設計而定，並非為本發明實施例所限制。
接著，如第4圖所示，進行一錫膏印刷製程，使用一刮刀(squeeze)246將一錫膏248印刷穿過模板400的第一開孔406，以於印刷電路板262的散熱墊/接地墊266上形成 複數個第一錫膏圖案250。在進行錫膏印刷製程期間，錫膏248也會印刷穿過模板400的第二開孔408，以分別於印刷電路板262的各自獨立的接合墊264上形成複數個第二錫膏圖案252。
接著，如第5圖所示，進行錫膏印刷製程之後，移開如第4圖所示的模板400。如第5圖所示，形成與印刷電路板262的散熱墊/接地墊266重疊的第一錫膏圖案250。並且，第二錫膏圖案252的邊界分別對準印刷電路板262的各自獨立的接合墊264的邊界。
接著，如第6圖所示，進行一零件黏貼製程(component placement process)，將aQFN封裝500置於一印刷電路板262上。進行零件黏貼製程之後，第一錫膏圖案250係對準並接觸至aQFN封裝500之晶片墊200的下表面206，而第二錫膏圖案252分別對準並接觸至aQFN封裝500的接觸端子(引腳)218的下表面222。在本發明一實施例中，藉由控制模板400的第一開孔406和晶片墊200的下表面206兩者的面積比例，設計第一錫膏圖案250，使其不會完全覆蓋晶片墊200的下表面206。因此，相較於習知技術之完全覆蓋晶片墊下表面的錫膏圖案，藉由模板400的第一開孔406的設計可減少印刷於晶片墊200的下表面206上的錫膏總量。
接著，如第7圖所示，進行一回焊製程(reflow process)，以熔化彼此隔離的第一錫膏圖案250成為覆蓋晶片墊200的下表面206的一第一液化錫膏250a。並且，回焊製程期間會熔化第二錫膏圖案252成為分別覆蓋接觸端 子(引腳)218的下表面222的複數個第二液化錫膏252a。注意位於晶片墊200的下表面206上(面積遠大於接觸端子(引腳)218的下表面222)的第一液化錫膏250a具有較少的錫膏總量。因此，第一液化錫膏250a對其上之aQFN封裝500的晶片墊200的抵抗力會小於習知技術之完全覆蓋晶片墊下表面的錫膏。因此，在回焊製程期間，會因為aQFN封裝500的重量而擠壓第一液化錫膏250a而使其往上覆蓋晶片墊200的下方側壁216。進行回焊製程之後，第一液化錫膏250a的一部分會圍繞晶片墊200的下方側壁216，而第一液化錫膏250a的一剩餘部分位於晶片墊200和印刷電路板262的散熱墊(thermal pad)/接地墊(ground pad)266之間。並且，進行回焊製程之後，第二液化錫膏252a的一部分會圍繞接觸端子(引腳)218的下方側壁242，而第一液化錫膏250a的一剩餘部分位於接觸端子(引腳)218和印刷電路板262的接合墊264之間。
請再參考第7圖，進行一冷卻製程，以固化第一液化錫膏250a為一第一焊點(solder joint)250a，其可視為aQFN封裝500的晶片墊200和印刷電路板262的散熱墊(thermal pad)/接地墊(ground pad)266之間的電性連接。在冷卻製程期間也會固化第二液化錫膏252a為一第二焊點(solder joint)252a，其可視為aQFN封裝500的接觸端子(引腳)218和印刷電路板262的接合墊264之間的電性連接。如第7圖所示，在本發明一實施例中，第一焊點(solder joint)250a可具有圍繞晶片墊200的下方側壁216之一楔狀部分，以鉗住晶片墊200。因此，可以提升aQFN封裝500的晶片墊 200和印刷電路板262的散熱墊(thermal pad)/接地墊(ground pad)266之間的機械強度。在本發明其他實施例中，每一個第二焊點(solder joint)252a可具有圍繞接觸端子(引腳)218的下方側壁242之一楔狀部分，以鉗住接觸端子(引腳)218。
本發明實施例係提供先進四方扁平無引腳(aQFN)封裝的表面黏著技術(SMT)及其使用的模板。在本發明實施例之表面黏著技術(SMT)的錫膏印刷製程中，藉由控制模板之設計對應至晶片墊的開孔和晶片墊的下表面兩者的總面積比例，以使連接至晶片墊的錫膏圖案設計為不會完全覆蓋晶片墊的下表面。因此，可減少連接至晶片墊的下表面上的錫膏總量，使其少於習知技術之完全覆蓋晶片墊下表面的錫膏圖案的錫膏總量。並且，在本發明實施例之表面黏著技術(SMT)的回焊製程中，位於晶片墊的下表面上(其面積遠大於引腳的下表面)的液化錫膏的錫膏總量較少。因此，相較於習知技術之完全覆蓋晶片墊下表面的錫膏，本發明實施例之總量較少的液化錫膏對其上之aQFN封裝的晶片墊的阻力較小。因此，在回焊製程期間，會因為aQFN封裝的重量而擠壓液化錫膏而使其往上覆蓋晶片墊的下方側壁。在進行冷卻製程以固化液化錫膏為焊點時，上述焊點可具有圍繞晶片墊的下方側壁之一楔狀部分，以鉗住晶片墊。因此，可以提升aQFN封裝的晶片墊和印刷電路板的散熱墊(thermal pad)/接地墊(ground pad)之間的機械強度。
雖然本發明已以實施例揭露如上，然其並非用以限定 本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定為準。
200‧‧‧晶片墊
202‧‧‧凹槽
204、220‧‧‧上表面
206、222‧‧‧下表面
208‧‧‧晶片
210、240‧‧‧上方側壁
212、214、224、226‧‧‧金屬層
216、242‧‧‧下方側壁
218‧‧‧接觸端子
224‧‧‧導線
230‧‧‧封膠模蓋
232‧‧‧對準標記
236‧‧‧接合墊
238‧‧‧底面
240‧‧‧黏著層
246‧‧‧刮刀
248‧‧‧錫膏
250‧‧‧第一錫膏圖案
252‧‧‧第二錫膏圖案
250a‧‧‧第一液化錫膏或第一焊點
252a‧‧‧第二液化錫膏或第二焊點
261‧‧‧頂面
262‧‧‧印刷電路板
264‧‧‧接合墊
266‧‧‧散熱墊/接地墊
P1、P2‧‧‧最小間距
400‧‧‧模板
402‧‧‧中間區域
404‧‧‧周圍區域
406、406a、406b、406c、406d‧‧‧第一開孔
408‧‧‧第二開孔
450‧‧‧鋼薄板
500‧‧‧先進四方扁平無引腳封裝
第1圖為本發明一實施例之先進四方扁平無引腳封裝的剖面圖。
第2圖為本發明一實施例之先進四方扁平無引腳封裝的底視圖。
第3~7圖為本發明一實施例之先進四方扁平無引腳封裝的表面黏著技術。
第8圖為本發明一實施例之先進四方扁平無引腳封裝的表面黏著技術使用的模板的上視圖。
第9a~9d圖顯示本發明一實施例之模板的第一開孔的不同設計。
P2‧‧‧最小間距
400‧‧‧模板
402‧‧‧中間區域
404‧‧‧周圍區域
406‧‧‧第一開孔
408‧‧‧第二開孔
410‧‧‧第三開孔
450‧‧‧鋼薄板

Claims (14)

  1. 一種先進四方扁平無引腳封裝的表面黏著技術製程，包括下列步驟：提供一印刷電路板；於該印刷電路板的一頂面上架設一模板，其具有複數個第一開孔；將一錫膏印刷穿過該些第一開孔，以於該印刷電路板的該頂面上形成複數個第一錫膏圖案；移開該模板；進行一零件黏貼製程，將一先進四方扁平無引腳封裝置於該印刷電路板的該頂面上，其中該先進四方扁平無引腳封裝包括：一晶片墊，具有一上表面和一下表面；以及複數個接觸端子，圍繞該晶片墊；其中該些第一錫膏圖案接觸該晶片墊的該下表面，其中該些第一開孔和該晶片墊的該下表面的面積比例介於1：2和1：10之間；以及進行一回焊製程，以熔化該些第一錫膏圖案成為一第一液化錫膏，其中該第一液化錫膏的一部分圍繞該晶片墊的一側壁，其中該模板具有與該些第一開孔隔離的複數個第二開孔，並且於該印刷電路板的該頂面上形成該些第一錫膏圖案期間更包括將該錫膏印刷穿過該些第二開孔，以分別於該印刷電路板的該頂面上形成複數個第二錫膏圖案。
  2. 如申請專利範圍第1項所述先進四方扁平無引腳封 裝的表面黏著技術製程，更包括冷卻該第一液化錫膏，使其形成一第一焊點。
  3. 如申請專利範圍第1項所述先進四方扁平無引腳封裝的表面黏著技術製程，其中進行該零件黏貼製程之後，該些第二錫膏圖案分別接觸該些接觸端子的下表面。
  4. 如申請專利範圍第1項所述先進四方扁平無引腳封裝的表面黏著技術製程，進行該回焊製程包括分別熔化該些第二錫膏圖案成為複數個第二液化錫膏，其中每一個該些第二液化錫膏的一部分圍繞每一個該些接觸端子的一側壁。
  5. 如申請專利範圍第1項所述先進四方扁平無引腳封裝的表面黏著技術製程，其中該些第一開孔彼此隔離。
  6. 如申請專利範圍第1項所述先進四方扁平無引腳封裝的表面黏著技術製程，其中該些第一開孔排列為一陣列。
  7. 如申請專利範圍第1項所述先進四方扁平無引腳封裝的表面黏著技術製程，其中該第一液化錫膏的一剩餘部分位於該晶片墊和該印刷電路板之間。
  8. 如申請專利範圍第1項所述先進四方扁平無引腳封裝的表面黏著技術製程，其中該晶片墊的該側壁鄰接該晶片墊的該下表面。
  9. 一種先進四方扁平無引腳封裝的表面黏著技術製程使用的模板，包括：一鋼薄板，具有一中間區域和圍繞該中間區域的一周圍區域；複數個第一開孔，穿過該鋼薄板，且位於該中間區域 中，其中該些第一開孔的位置對應至一先進四方扁平無引腳封裝的一晶片墊的位置，且該些第一開孔和該晶片墊與一印刷電路板接觸的一表面的面積比例介於1：2和1：10之間；以及複數個第二開孔，穿過該鋼薄板，且位於該周圍區域中，其中當該模板架設於該先進四方扁平無引腳封裝的上方時，該些第二開孔的位置分別對應至該先進四方扁平無引腳封裝的複數個接觸端子的位置。
  10. 如申請專利範圍第9項所述先進四方扁平無引腳封裝的表面黏著技術製程使用的模板，其中該些第一開孔彼此隔離。
  11. 如申請專利範圍第9項所述先進四方扁平無引腳封裝的表面黏著技術製程使用的模板，其中該些第一開孔排列為一陣列。
  12. 如申請專利範圍第9項所述先進四方扁平無引腳封裝的表面黏著技術製程使用的模板，其中該些第二開孔的間距等於該些接觸端子的間距。
  13. 如申請專利範圍第9項所述先進四方扁平無引腳封裝的表面黏著技術製程使用的模板，其中該中間區域的一邊界對應至該先進四方扁平無引腳封裝的該晶片墊的一邊界。
  14. 一種先進四方扁平無引腳封裝的表面黏著技術製程，包括下列步驟：提供一印刷電路板；於該印刷電路板的一頂面上架設一模板，其具有複數 個第一開孔；將一錫膏印刷穿過該些第一開孔，以於該印刷電路板的該頂面上形成複數個第一錫膏圖案；移開該模板；進行一零件黏貼製程，將一先進四方扁平無引腳封裝置於該印刷電路板的該頂面上，其中該先進四方扁平無引腳封裝包括：一晶片墊，具有一上表面和一下表面；以及複數個接觸端子，圍繞該晶片墊；其中該些第一錫膏圖案接觸該晶片墊的該下表面，其中該些第一開孔和該晶片墊的該下表面的面積比例介於1：2和1：10之間；以及進行一回焊製程，以熔化該些第一錫膏圖案成為一第一液化錫膏，其中該第一液化錫膏的一部分圍繞該晶片墊的一側壁，其中進行該零件黏貼製程之後，該些第一錫膏圖案位於該晶片墊的該下表面的一邊界內。
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