TWI489599B - 積體電路模組及其製造方法 - Google Patents

積體電路模組及其製造方法 Download PDF

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TWI489599B
TWI489599B TW097120461A TW97120461A TWI489599B TW I489599 B TWI489599 B TW I489599B TW 097120461 A TW097120461 A TW 097120461A TW 97120461 A TW97120461 A TW 97120461A TW I489599 B TWI489599 B TW I489599B
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opening
wafer
integrated circuit
insulating layer
layer
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TW097120461A
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TW200952135A (en
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Lu Chen Hwan
Po Ching Chen
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Mutual Pak Technology Co Ltd
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Description

積體電路模組及其製造方法
本發明係關於一種積體電路模組及其製造方法，更具體地是關於具有載板之積體電路模組及其製造方法。
傳統積體電路元件要對外連接通常是將晶片接合到一導線架上，接著利用搭接器以打線的方式使晶片上的I/O接點與導線架的外部電路接點電相接，之後再進行密封作業而完成封裝。這種打線方式因為引線佔據太多空間，因而漸被另一種無引線搭接技術所取代。
圖1例示習知無引線搭接技術所製得之積體電路模組100。如圖所示，積體電路模組100包含晶片10，晶片10上具有導電凸塊11；及載板12，其上設置外部電路接點13。將晶片10翻轉過來使導電凸塊11與其對應之外部電路接點13接合，再施加異方性導電材料15在晶片10與外部電路接點13之間，即可完成積體電路模組100。
然而，圖1這種習知積體電路模組100仍有結構過於簡單因而對外連接變化性差以及散熱能力不好的缺點，所以需要一種新穎的積體電路模組及其製法來改善習知的結構。
有鑑於上述之需求，本發明提供一種具有更多對外接觸界面的積體電路模組，藉此提昇晶片的散熱效果並增強對外連接的變 化性。
依據一實施例，本發明提供一種積體電路模組，包含一晶片；及一載板，承載該晶片，該載板定義一前側及一後側，該晶片設置於該前側，該載板包含：一第一絕緣層於該後側，該第一絕緣層定義一第一開口；一第二絕緣層於該前側，該第二絕緣層定義一第二開口及一收納晶片開口；及一圖案化導電層夾設於該第一絕緣層與該第二絕緣層之間，該圖案化導體層具有一內接觸部暴露於該收納晶片開口及一外接觸部暴露於該第一開口與該第二開口，其中該內接觸部透過該收納晶片開口連接該晶片，而該外接觸部則供一電子元件選擇性地透過該第一開口及該第二開口電連接該圖案化導體層於該載板之該前側或該後側。
依據另一實施例，本發明提供一種積體電路模組，包含一電路板；一晶片；及一載板，承載該晶片，該載板定義一前側及一後側，該晶片設置於該前側，該載板包含：一第一絕緣層於該後側，該第一絕緣層定義一第一開口；一第二絕緣層於該前側，該第二絕緣層定義一收納晶片開口及一第二開口；及一圖案化導電層夾設於該第一絕緣層與該第二絕緣層之間，該圖案化導體層具有一內接觸部暴露於該收納晶片開口及一外接觸部暴露於該第一開口與該第二開口，其中該晶片透過該收納晶片開口連接該內接觸部，而該電路板則選擇性地透過該第一開口及該第二開口連接該外接觸部於該前側或該後側。
依據更另一實施例，本發明提供一種製造一積體電路模組的方法，包含提供一第一絕緣層，該第一絕緣層定義一第一開口； 形成一圖案化導電層於該第一絕緣層上方，該圖案化導電層具有一外接觸部及一內接觸部，該第一開口暴露該外接觸部；形成一第二絕緣層於圖案化導電層上方，該第二絕緣層定義一第二開口暴露該外接觸部及一收納晶片開口暴露該內接觸部；提供一晶片；及將該晶片透過該收納晶片開口與該內接觸部接合。
以下將參考所附圖式示範本發明之較佳實施例。所附圖式中相似元件係採用相同的元件符號。應注意為清楚呈現本發明，所附圖式中之各元件並非按照實物之比例繪製，而且為避免模糊本發明之內容，以下說明亦省略習知之零組件、相關材料、及其相關處理技術。
圖2係根據一實施例，例示本發明承載晶片之載板200的結構分解圖，據此說明載板200的結構及其製法。如圖所示，製造載板200的方法包含先提供一第一絕緣層210。第一絕緣層210可為聚亞醯胺、聚對苯二甲酸乙二醇酯、環氧樹脂、用於一般印刷電路板之包含玻璃纖維之介電層的各種材料，例如用於FR4 的玻璃纖維板、或以上述之各種材料組合製成。第一絕緣層210係形成至少一個第一開口211，可用雷射鑽孔或沖壓等習知技術來完成此步驟。
接著，同樣參考圖2，形成一圖案化導電層220覆蓋第一絕緣層210。圖案化導電層220係定義一外接觸部221及一內接觸部222。外接觸部221對應第一絕緣層210之第一開口211，因此第一開口211將暴露外接觸部221。內接觸部222則形成複數個 第一電極222a及222b，用以電連接後續所要承載的晶片。除第一電極222a及222b以外，圖案化導電層220更形成複數個第二電極223。第二電極223係電連接第一電極222a。第二電極223用來測試後續所要承載的晶片的效能。此外，圖案化導電層220更定義一導通孔221a於外接觸部221。導通孔221a之用途後續將詳細說明。圖案化導電層220的材料可為銅或任何合適的導電材料。執行此步驟可先提供一銅箔覆蓋第一絕緣層210之表面，接著利用微影蝕刻技術在銅箔上形成需要的圖案，以製作如上述之外接觸部221、導通孔221a、內接觸部222之第一電極222a/222b、及第二電極223等，然不以此為限。形成導通孔221a可用微影蝕刻也可用習知之鑽孔技術。
接著，同樣參考圖2，形成一第二絕緣層230覆蓋圖案化導電層220。第二絕緣層230係定義一第二開口231以暴露外接觸部221；一收納晶片開口232以暴露內接觸部222；及一第三開口233以暴露第二電極223。第二絕緣層230之材質可為一般之防焊綠漆或其他合適之材料，包含聚亞醯胺等。以防焊綠漆作為第二絕緣層230，其形成方法為塗佈防焊綠漆於圖案化導電層220之表面上，然後以習知微影蝕刻技術形成上述之各開口。
參考圖3，顯示結合如上所述之三層結構之載板200的俯視圖。如圖所示，第二絕緣層230之第二開口231暴露圖案化導電層220之外接觸部221；第二絕緣層230之第三開口233暴露圖案化導電層220之第二電極223；第二絕緣層232之收納晶片開口232則暴露出圖案化導電層220之內接觸部222的複數個第一電極222a及222b。由此可知，載板200所承載之晶片將可設置 於收納晶片開口232上以與內接觸部222之複數個第一電極222a及222b接合。
圖4A及圖4B係依據本發明之一實施例分別例示一晶片400之結構剖面圖及俯視圖。如圖所示，一已封裝之晶片400包含一積體電路元件410、複數個I/O接點420、一鈍化層430、複數個延伸接點440、複數個內導電凸塊450、保護層460、外導電凸塊470及表面金屬層480。積體電路元件410可為任一種半導體元件，如發光二極體、光電二極體、雷射二極體或整流型二極體；也可為電晶體，如MOS、CMOS等。複數個I/O接點420及鈍化層430係設在積體電路元件410的上表面。複數個延伸接點440設置於複數個I/O接點420上方，用以延伸擴大複數個I/O接點420之對外接觸面積。I/O接點420及延伸接點440之材料可為任何導電性良好之金屬所製成。鈍化層430則可為氮氧化矽等介電材料製成。複數個內導電凸塊450設置於複數個延伸接點440上。保護層460則環繞積體電路元件410、複數個I/O接點420、鈍化層430、延伸接點440及內導電凸塊450。複數個外導電凸塊470進一步設置位內導電凸塊450上方。外導電凸塊470用以使積體電路元件410電連接至載板200之內接觸部222。內導電凸塊450及外導電凸塊470可為金屬顆粒與高分子化合物之複合材料所組成。保護層460之材料可為環氧樹脂、聚亞醯胺、苯并環丁烷、液晶高分子、或任何其他合適之介電材料。表面金屬層480覆蓋外導電凸塊470。表面金屬層480之材料可為鎳、金、或其組合，或任何其他可幫助晶片400與其他裝置電性接合的材料。有關晶片400之製法可參照中華民國專利申請號96116302，其內容併如本文供參考。然應注意，本發明除了適用如上述之晶片400外， 也適用於其他晶片。
圖5A及圖5B係依據本發明之一實施例分別例示一積體電路模組500的立體透視圖及剖面圖，其中圖5B係沿圖5A之虛線I-I'的剖面。如圖所示，製造積體電路模組500利用如前述之載板200，將晶片400裝設在載板200上，再形成一底填充層(underfill layer)510於載板200之表面並環繞晶片400以使晶片400固定於載板200之第二絕緣層230上。底填充層510之材質包含環氧樹脂、聚丙烯、壓克力樹脂(acrylic resin)、矽膠、或上述之各種組合。詳言之，積體電路模組500包含晶片400及承載晶片400的載板200。載板200係定義一前側A及一後側B，晶片400設置於前側A。載板200包含第一絕緣層210於後側B；第二絕緣層230於前側A；及圖案化導電層220夾設於第一絕緣層210與第二絕緣層230之間。第一絕緣層210定義第一開口211；第二絕緣層230定義第二開口231及收納晶片開口232。圖案化導體層220具有內接觸部222暴露於收納晶片開口232；及外接觸部221暴露於第一開口211與第二開口231。內接觸部222透過收納晶片開口232連接晶片400。在此實施例中，外接觸部221係用以外接一電子元件(未顯示)。由於外接觸部221暴露於第一開口211與第二開口231，故可供使用者選擇性地透過第一開口211及第二開口231使電子元件設置於載板220之前側A或後側B。由圖可知，載板200更包含導通孔221a於外接觸部221，導通孔221a係連通第二開口231及第一開口211，且第二開口231及第一開口211係分別大於導通孔221a。應注意，本實施例之內接觸部222係具有複數個第一電極222b及222a，晶片400具有複數個外導電凸塊470，將晶片400與內接觸部222接合之步驟係包含分別 使複數個第一電極222b及222a接合至複數個外導電凸塊470。
圖6例示本發明之積體電路模組600，其係將電路板650設置於載板200之後側B的實施例。詳言之，積體電路模組600之製作方法包含提供電路板650，電路板650包含基板610及其上之接點620。接著，將電路板650放置於載板200之後側B(即接近第一絕緣層210之側)。然後形成一導電黏著層630填充第一開口211、第二開口231及導通孔221a，並使導電黏著層630黏結到電路板650之接點620上。導電黏著層630之材料可為任何合適的金屬膠。
圖7例示本發明之積體電路模組700，其係為將電路板750設置於載板200之前側A的實施例。詳言之，積體電路模組700之製作方法包含提供電路板700，電路板750包含基板710及其上之接點720。接著，將電路板750放置於載板200之前側A(即接近第二絕緣層230之側)。然後形成一導電黏著層730填充第一開口211、第二開口231及導通孔221a，並使導電黏著層730黏結到電路板750之接點720上。
以上所述僅為本發明之較佳實施例而已，並非用以限定本發明之申請專利範圍；凡其它未脫離本發明所揭示之精神下所完成之等效改變或修飾，均應包含在下述之申請厚度專利範圍內。
100‧‧‧積體電路模組
10‧‧‧晶片
11‧‧‧導電凸塊
12‧‧‧載板
13‧‧‧外部電路接點
15‧‧‧異方性導電材料
200‧‧‧載板
210‧‧‧第一絕緣層
211‧‧‧第一開口
220‧‧‧圖案化導電層
221‧‧‧外接觸部
222‧‧‧內接觸部
222a、222b‧‧‧第一電極
223‧‧‧第二電極
221a‧‧‧導通孔
230‧‧‧第二絕緣層
231‧‧‧第二開口
232‧‧‧收納晶片開口
233‧‧‧第三開口
400‧‧‧晶片
410‧‧‧積體電路元件
420‧‧‧複數個I/O接點
430‧‧‧鈍化層
440‧‧‧延伸接點
450‧‧‧內導電凸塊
460‧‧‧保護層
470‧‧‧外導電凸塊
480‧‧‧表面金屬層
500‧‧‧積體電路模組
510‧‧‧底填充層
A‧‧‧前側
B‧‧‧後側
600, 700‧‧‧積體電路模組
650, 750‧‧‧電路板
610, 710‧‧‧基板
620, 720‧‧‧接點
630, 730‧‧‧導電黏著層
圖1顯示習知之積體電路模組的剖面圖；圖2係依據一實施例顯示本發明之載板的結構分解圖； 圖3係顯示圖2之載板的俯視圖；圖4A係依據一實施例顯示本發明之晶片的剖面圖；圖4B係顯示圖4A之晶片的俯視圖；圖5A係依據一實施例顯示本發明之積體電路模組的透視圖；圖5B係顯示圖5A之積體電路模組的剖面圖；圖6係依據另一實施例顯示本發明積體電路模組的剖面圖；及圖7係依據更另一實施例顯示本發明積體電路模組的剖面圖。
200‧‧‧載板
210‧‧‧第一絕緣層
211‧‧‧第一開口
220‧‧‧圖案化導電層
221‧‧‧外接觸部
222‧‧‧內接觸部
222a、222b‧‧‧第一電極
223‧‧‧第二電極
221a‧‧‧導通孔
230‧‧‧第二絕緣層
231‧‧‧第二開口
232‧‧‧收納晶片開口
233‧‧‧第三開口
400‧‧‧晶片
470‧‧‧外導電凸塊
500‧‧‧積體電路模組
510‧‧‧底填充層

Claims (30)

  1. 一種積體電路模組，包含：一晶片；及一載板，承載該晶片，該載板定義一前側及一後側，該晶片設置於該前側，該載板包含：一第一絕緣層於該後側，該第一絕緣層定義一第一開口；一第二絕緣層於該前側，該第二絕緣層定義一第二開口及一收納晶片開口；及一圖案化導電層夾設於該第一絕緣層與該第二絕緣層之間，該圖案化導體層具有一內接觸部暴露於該收納晶片開口及一外接觸部暴露於該第一開口與該第二開口，其中該內接觸部透過該收納晶片開口連接該晶片，而該外接觸部則供一電子元件選擇性地透過該第一開口及該第二開口電連接該圖案化導體層於該載板之該前側或該後側，其中該圖案化導電層係定義一導通孔於該外接觸部，該導通孔連通該第二開口及該第一開口，用來使一導電黏著層填充該第一開口、該第二開口及該導通孔以使該電子元件與載板連結，其中該導電黏著層直接接觸該圖案化導電層。
  2. 如請求項1所述之積體電路模組，其中該第一絕緣層之材質包含聚亞醯胺、聚對苯二甲酸乙二醇酯、環氧樹脂、玻璃纖維、或上述之各種組合。
  3. 如請求項1所述之積體電路模組，其中該第二開口及該第一開口係分別大於該導通孔。
  4. 如請求項1所述之積體電路模組，其中該內接觸部具有複 數個第一電極供電連接該晶片。
  5. 如請求項4所述之所述之積體電路模組，其中該圖案化導電層更包含一第二電極電連接該第一電極，該第二電極供測試該晶片的效能。
  6. 如請求項5所述之積體電路模組，其中該第二絕緣層係定義一第三開口暴露該第二電極。
  7. 如請求項1所述之積體電路模組，其中該第二絕緣層之材質包含環氧樹脂、聚丙烯、壓克力樹脂、矽膠、或上述之各種組合。
  8. 如請求項1所述之積體電路模組，其中該晶片包含：一積體電路元件；一內導電凸塊電連接該積體電路元件；一保護層環繞該積體電路元件及該內導電凸塊；及一外導電凸塊位於該內導電凸塊上，該外導電凸塊連接於該載板之該內接觸部。
  9. 如請求項1所述之積體電路模組，更包含一底填充層(unfill layer)環繞該晶片，該底填充層使該晶片固定於該載板上。
  10. 一種積體電路模組，包含：一電路板；一晶片；及一載板，承載該晶片，該載板定義一前側及一後側，該晶片設置於該前側，該載板包含： 一第一絕緣層於該後側，該第一絕緣層定義一第一開口；一第二絕緣層於該前側，該第二絕緣層定義一收納晶片開口及一第二開口；及一圖案化導電層夾設於該第一絕緣層與該第二絕緣層之間，該圖案化導體層具有一內接觸部暴露於該收納晶片開口及一外接觸部暴露於該第一開口與該第二開口，其中該晶片透過該收納晶片開口連接該內接觸部，而該電路板則選擇性地透過該第一開口及該第二開口連接該外接觸部於該前側或該後側，其中該圖案化導電層係定義一導通孔於該外接觸部，該導通孔連通該第二開口及該第一開口，用來使一導電黏著層填充該第一開口、該第二開口及該導通孔以使該電路板與該載板連結，其中該導電黏著層直接接觸該圖案化導電層。
  11. 如請求項10所述之積體電路模組，其中該第一絕緣層之材質包含聚亞醯胺、聚對苯二甲酸乙二醇酯、環氧樹脂、玻璃纖維或上述之各種組合。
  12. 如請求項10所述之積體電路模組，其中該第一開口及該第二開口係分別大於該導通孔。
  13. 如請求項10所述之積體電路模組，其中該內接觸部具有複數個第一電極供電連接該晶片。
  14. 如請求項13所述之所述之積體電路模組，其中該圖案化導電層更包含一第二電極電連接該第一電極，該第二電極供測試該晶片的效能。
  15. 如請求項14所述之積體電路模組，其中該第二絕緣層係定義一第三開口暴露該第二電極。
  16. 如請求項10所述之積體電路模組，其中該第二絕緣層之材質包含環氧樹脂、聚丙烯、壓克力樹脂(acrylic resin)、矽膠、或上述之各種組合。
  17. 如請求項10所述之積體電路模組，其中該晶片包含：一積體電路元件；一內導電凸塊電連接該積體電路元件；一保護層環繞該積體電路元件及該內導電凸塊；及一外導電凸塊位於該內導電凸塊上，該外導電凸塊連接該載板之該內接觸部。
  18. 如請求項10所述之積體電路模組，更包含一底填充層(underfill layer)環繞該晶片，該底填充層用以使該晶片固定於該載板上。
  19. 如請求項18所述之積體電路模組，其中該底填充層之材質包含環氧樹脂、聚丙烯、壓克力樹脂(acrylic resin)、矽膠、或上述之各種組合。
  20. 請求項10所述之積體電路模組，更包含一導電黏著層填充該第一開口、該第二開口及該導通孔以連接該電路板與載板。
  21. 一種製造一積體電路模組的方法，包含：提供一第一絕緣層，該第一絕緣層定義一第一開口； 形成一圖案化導電層於該第一絕緣層上方，該圖案化導電層具有一外接觸部及一內接觸部，該第一開口暴露該外接觸部；形成一第二絕緣層於圖案化導電層上方，該第二絕緣層定義一第二開口暴露該外接觸部及一收納晶片開口暴露該內接觸部；形成一導通孔於該外接觸部，該導通孔連通該第一開口及該第二開口；提供一晶片；將該晶片透過該收納晶片開口與該內接觸部接合；提供一電路板；將該電路板放置在接近該第一絕緣層的一側或接近該第二絕緣層之另一側；及形成一導電黏著層填充該第一開口、該第二開口及該導通孔並黏結至該電路板，其中該導電黏著層直接接觸該圖案化導電層。
  22. 如請求項21所述之方法，其中該第一絕緣層之材質包含聚亞醯胺、聚對苯二甲酸乙二醇酯、環氧樹脂、玻璃纖維或上述之各種組合。
  23. 如請求項21所述之方法，其中該第一開口及該第二開口係分別大於該導通孔。
  24. 如請求項21所述之方法，其中該內接觸部具有複數個第一電極，該晶片具有複數個外導電凸塊，將該晶片與該內接觸部接合之步驟包含分別使該複數個第一電極接合至該複數個 外導電凸塊。
  25. 如請求項24所述之方法，其中形成該圖案化導電層之該步驟更包含形成一第二電極電連接該第一電極，該第二電極供測試該晶片的效能。
  26. 如請求項25所述之方法，其中形成該第二絕緣層係包含形成一第三開口暴露該第二電極。
  27. 如請求項21所述之方法，其中該第二絕緣層之材質包含聚亞醯胺。
  28. 如請求項24所述之方法，其中該晶片包含：一積體電路元件；複數個內導電凸塊電連接該積體電路元件；一保護層環繞該積體電路元件及該複數個內導電凸塊，其中該複數個外導電凸塊係分別連接該複數個內導電凸塊。
  29. 如請求項21所述之方法，更包含形成一底填充層(underfill layer)環繞該晶片，該底填充層用以使該晶片固定於該第二絕緣層上。
  30. 如請求項29所述之方法，其中該底填充層之材質包含環氧樹脂、聚丙烯、壓克力樹脂(acrylic resin)、矽膠、或上述之各種組合。
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JP6032768B2 (ja) * 2011-09-06 2016-11-30 フィリップス ライティング ホールディング ビー ヴィ Ｌｅｄマトリクスの製造方法及びｌｅｄマトリクスを有する装置
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