TWM537714U - 平板式半導體封裝結構 - Google Patents

平板式半導體封裝結構 Download PDF

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TWM537714U
TWM537714U TW105215989U TW105215989U TWM537714U TW M537714 U TWM537714 U TW M537714U TW 105215989 U TW105215989 U TW 105215989U TW 105215989 U TW105215989 U TW 105215989U TW M537714 U TWM537714 U TW M537714U
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substrate
layer
dielectric layer
wafer
line
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TW105215989U
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zhao-qing Yu
Lin-Da Zhong
xi-ying Yuan
dong-chuan Wang
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Chip Win Technology Co Ltd
zhao-qing Yu
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Priority to TW105215989U priority Critical patent/TWM537714U/zh
Publication of TWM537714U publication Critical patent/TWM537714U/zh

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    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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Description

平板式半導體封裝結構
本新型係一種半導體封裝結構，尤指一種平板式半導體封裝結構。
半導體封裝結構係一種透過外殼容納、包覆一個或多個半導體元件或積體電路的結構，該外殼的材料可以是金屬、塑料、玻璃或陶瓷。當半導體元件或積體電路從晶圓上刻蝕出來並切割成獨立的晶片後，透過半導體封裝結構能將晶片包覆在其中，並提供一定的衝擊及劃傷保護，且能為晶片提供連接外部電路的接點，並能在晶片工作時將熱量加速散去。
請參閱圖11至圖16所示，一般的半導體封裝結構係先提供一載具90及一第二基板91，載具90的下表面設有對準圖案901，如圖11所示，該第二基板91係具有一第一平面911、一第二平面912及至少一容置空間913，且將該第二基板91之第一平面911面向該載具90，並將該第二基板91第一表面911上的線路9111對準載具90的對準圖案901，並設置於該載具90上。接著，如圖12所示，將一晶片92容置在該第二基板91的容置空間913中，晶片上的鋁墊對準載具90上之對準圖案902，並接觸該載具90，使得該晶片92上的鋁墊921的表面與該第二基板91第一平面911上的線路9111位於同一平面上。
如圖13所示，進一步將一黏膠材料93灌入該第二基板91與該晶片92間的空隙，並覆蓋該第二基板91的第二表面912，使得該晶片92能穩固地設置在該第二基板91的容置空間913中。如圖14所示，接著，將一第一基板94設置在該第二基板91的第二表面912，且透過該黏膠材料93黏著在該第二基板91的第二表面912。此外，該第一基板94表面上的線路941與第二基板91第二表面912上的線路9121對準，並透過在該第一基板94表面的線路941與該第二基板91第二表面912的線路9121上分別塗佈錫膏，再經過焊接程序，使兩個線路經由錫膏連接並能做電性導通。
如圖15所示，然後，透過一薄刀95將該載具90剝除。如圖16所示，最後，再製作線路，將晶片92上的鋁墊921及第二基板91第一表面911上的線路9111連接，並覆蓋一層介電層作保護。
然而，採用上述製程方式製作的半導體封裝結構，需要一個載具90，且載具90上需要製作對準圖案901、902，若需要大量對晶片進行封裝時，因半導體封裝係透過對準圖案的設置，使各個半導體元件能確切的設置於設計時預定的位置，該半導體成品方才能使用，因此，上述製程方式需要準備相當數量之載具90，方才能進行半導體封裝，且需要額外的製程將第二基板91與載具90分離。此外，第一基板與第二基板間需透過4道製程，使第一基板94以及第二基板91間具有導通之功效，且須兩層焊接金屬凸塊，如此一來，等於做到6層線路，因此，上述的封裝結構的製程相當繁複。
有鑑於上述現有技術的半導體封裝結構，其所需要的製程步驟非常繁複，本新型提供一種平板式半導體封裝結構，不需要載具，且減少4層線路製程，以及減少與載具的分離步驟，使製程簡化。
該平板式半導體封裝結構係包含有： 一第一基板； 一第二基板，係設置於該第一基板之上表面，且形成有一容置孔； 一第一膠層，係夾設於該第一基板與該第二基板之間，以黏合該第一基板及該第二基板；其中該第一基板之下表面係形成有一第一層線路，而該第二基板上表面形成有一第二層線路； 至少一第一導通孔，係貫穿形成於該第二基板、第一膠層及該第一基板中，且該至少一第一導通孔內填充有導電材料，而該第一層線路與該第二層線路係透過填充有導電材料的至少一第一導通孔電性連接； 一晶片，係設置於該第二基板的容置孔中，而該晶片之上表面係形成有至少一鋁墊； 一第二膠層，係夾設於該晶片與該第二基板的容置孔內壁之間，以黏合該晶片與該第二基板； 一第一介電層，係設置於該第一基板之下表面，且形成有至少一開孔，以連通該第一層線路； 一第二介電層，係設置於該第二基板之上表面，且貫穿形成有複數第二導通孔，而該些第二導通孔係分別連通該第二層線路及該晶片之鋁墊，並於該些第二導通孔中填充有導電材料；其中該第二介電層之上表面係形成有一第三層線路，且該第三層線路與該第二層線路及該晶片之鋁墊係透過填充有導電材料的該些第二導通孔電性連接； 一第三介電層，係設置於該第二介電層之上表面，且覆蓋該第三層線路。
透過本新型提供的平板式半導體封裝結構，令該晶片可被完整的封裝在結構內部不會外露，且該晶片之鋁墊能透過填充有導電材料的該些第二導通孔電性連接至該第三層線路，再透過該第三層線路及其他填充有導電材料的第二導通孔電性連接至該第二層線路，進一步透過填充有導電材料的該第一導通孔電性連接至該第一層線路。如此一來，該晶片的鋁墊便可透過該第一介電層之至少一開孔連通該第一層線路的部分與其他外部電路電性連接，且該晶片係被完整封裝在該平板式半導體封裝結構中，未有外露部分，提供更佳的耐衝擊保護。此外，本新型提供的平板式半導體封裝結構，在製作過程中，不需要設置載具，且能減少多層線路製程數量，以及減少與載具的分離步驟，使製程簡化。
以下配合圖式及本新型較佳實施例，進一步闡述本新型為達成預定目的所採取的技術手段。
請參閱圖1所示，本新型係一種平板式半導體封裝結構，包含有一第一基板11、一第二基板12、一第一膠層21、至少一第一導通孔31、一晶片40、一第二膠層22、一第一介電層51、一第二介電層52及一第三介電層53。
該第一基板11。
該第二基板12係設置於該第一基板11之上表面，且形成有一容置孔121。
該第一膠層21係夾設於該第一基板11與該第二基板12之間，以黏合該第一基板11及該第二基板21。該第一基板11下表面係形成有一第一層線路61，而該第二基板12上表面係形成有一第二層線路62。
該至少一第一導通孔31係貫穿該第一基板11、該第一膠層21及該第二基板12中，且該至少一第一導通孔31內填充有導電材料，而該第一層線路61與該第二層線路62係透過填充有導電材料的該至少一第一導通孔31電性連接。
該晶片40係設置於該第二基板12的容置孔121中，而該晶片40之上表面係形成有至少一鋁墊41。在本較佳實施例中，該第一基板11係形成有一對準圖案111，且該晶片40係對準該第一基板11的對準圖案111設置。
該第二膠層22係夾設於該晶片40與該第二基板12的容置孔121內壁之間，以黏合該晶片40與該第二基板12。
該第一介電層51係設置於該第一基板11下表面，且形成有至少一開孔511，以提供外部電路電性連接該第一層線路61。
該第二介電層52係設置於該第二基板12上表面，且貫穿形成有複數第二導通孔32，並填充有導電材料。而該些第二導通孔32係分別連通該第二層線路62及該晶片40之鋁墊41。該第二介電層52上表面係形成有一第三層線路63，且該第三層線路63與該第二層線路62及該晶片40之鋁墊41係透過填充有導電材料的該些第二導通孔32電性連接。
該第三介電層53係設置於該第二介電層52之上表面，且覆蓋該第三層線路63。
藉由本新型提供的平板式半導體封裝結構，可將該晶片40完整地封裝在該平板式半導體封裝結構內部，且不會有任何表面外露。而該晶片40之鋁墊41能透過填充有導電材料的該些第二導通孔32電性連接至該第三層線路63，並透過該第三層線路63及其他填充有導電材料的第二導通孔32電性連接至該第二層線路62，進一步透過填充有導電材料的該第一導通孔31電性連接至該第一層線路61。如此一來，該晶片40的鋁墊41便可透過該第一介電層51開孔511連通該第一層線路61的部分與其他外部電路電性連接，且該晶片40被完整封裝在平板式半導體封裝結構中，提供更佳的耐衝擊保護。此外，本新型提供的平板式半導體封裝結構在製作過程中，不需要設置載具，且能減少多層線路製程數量，以及減少與載具的分離步驟，使製程簡化。
請參閱圖2至圖7所示，係本新型平板式半導體封裝結構的製作方法流程示意圖。如圖2所示，該平板式半導體封裝結構的製作方法係先提供該第一基板11及該第二基板12，並在該第一基板11及該第二基板12之間設置有該第一膠層21。如圖3所示，接著利用該第一膠層21黏合該第一基板11及該第二基板12。
如圖4所示，然後貫穿黏合後的該第一基板11、該第一膠層21及該第二基板12以形成該至少一第一導通孔31，並於該至少一第一導通孔31填充有導電材料。接著透過金屬鍍著、曝光、顯影、蝕刻等製程技術在該第一基板11下表面形成該第一層線路61，並在該第二基板12上表面形成該第二層線路62。且該第一層線路61及該第二層線路62係透過填充有導電材料的該至少一第一導通孔31電性連接。如圖5所示，將該晶片40設置於該第二基板12的容置孔121中且對準該第一基板11的對準圖案111，而該晶片40之上表面係形成有該至少一鋁墊41。而該第二膠層22係夾設於該晶片40與該第二基板12的容置孔121內壁之間，以黏合該晶片40與該第二基板12。並將該第一介電層51設置於該第一基板11下表面，且形成有至少一開孔511，以提供外部電路電性連接該第一層線路61。
如圖6所示，將該第二介電層52設置於該第二基板12之上表面，且貫穿形成有複數第二導通孔32，並在該些第二導通孔32中填充有導電材料，而該些第二導通孔32係分別連通該第二層線路62及該晶片40之鋁墊41。且於該第二介電層52之上表面形成該第三層線路63，而該第三層線路63係透過填充有導電材料的該些第二導通孔32與該第二層線路62及該晶片40之鋁墊41電性連接。接著將該第三介電層53設置於該第二介電層52之上表面，並覆蓋該第三層線路63。
透過上述製作流程即可完成本新型之平板式半導體封裝結構，令該晶片40完整封裝在平板式半導體封裝結構中，且未有外露部分，提供更佳的耐衝擊保護。且本新型提供的平板式半導體封裝結構在製作過程中，不需要設置載具，且能減少多層線路製程數量，以及減少與載具的分離步驟，使製程簡化。
進一步而言，如圖7所示，形成一錫球70或導電銲材在該第一介電層51的至少一開孔511中，且該錫球70或該導電銲材凸出該第一介電層51的表面。而該錫球70或該導電銲材係通過該第一介電層51的至少一開孔511電性連接該第一層線路61。由於該錫球70或該導電銲材係凸出該第一介電層51的表面，如此一來，該第一層線路61即可透過該凸出的錫球70或該導電銲材更容易地與外部電路電性連接。
請參閱圖8所示，此外，該第三介電層53係進一步貫穿形成有複數第三導通孔33以連通該第三層線路63，並在該第三導通孔33中填充有導電材料。如此一來，該第三介電層53上即可供設置其他電路元件80，且該些電路元件80可透過該第三介電層53中填充有導電材料的該些第三導通孔33電性連接該第三層線路63，使得該些電路元件80與該平板式半導體封裝結構整體形成一系統級封裝(System in package；SIP)模組。該電路元件80係覆晶技術積體電路(flip-chip IC)或被動元件。
請參閱圖9所示，再者，該第三介電層53之上表面還進一步形成有一第四介電層54。且該第四介電層54係貫穿形成有複數開孔541，以連通填充有導電材料的該些第三導通孔33。如此一來，該第四介電層54上即可供另一個平板式半導體封裝結構設置，且另一個平板式半導體封裝結構的錫球70’可透過該第四介電層54的開孔541電性連接至填充有導電材料的該些第三導通孔33，進而使得兩個平板式半導體封裝結構相互電性連接，形成一疊層封裝(Package on Package；PoP)結構。
請參閱圖10所示，在本較佳實施例中，該晶片40係一指紋辨識晶片，且該晶片40之上表面係具有一感應區域42。而該第二介電層52對應該感應區域的位置係形成有一開孔521，以連通該晶片40的感應區域，令該晶片40的感應區域露出。且該第三介電層係耐磨材料，並覆蓋該第二介電層52之開孔521。如此一來，當需要進行指紋辨識時，使用者即可將手指放置到該第三介電層53上對應該第二介電層52開孔521的位置，讓該晶片40的感應區域42能感應到使用者的手指，進而進行指紋辨識。
以上所述僅是本新型的較佳實施例而已，並非對本新型做任何形式上的限制，雖然本新型已以較佳實施例揭露如上，然而並非用以限定本新型，任何熟悉本專業的技術人員，在不脫離本新型技術方案的範圍內，當可利用上述揭示的技術內容做出些許更動或修飾為等同變化的等效實施例，但凡是未脫離本新型技術方案的內容，依據本新型的技術實質對以上實施例所作的任何簡單修改、等同變化與修飾，均仍屬於本新型技術方案的範圍內。
11‧‧‧第一基板
111‧‧‧對準圖案
12‧‧‧第二基板
121‧‧‧容置孔
21‧‧‧第一膠層
22‧‧‧第二膠層
31‧‧‧第一導通孔
32‧‧‧第二導通孔
33‧‧‧第三導通孔
40‧‧‧晶片
41‧‧‧鋁墊
42‧‧‧感應區域
51‧‧‧第一介電層
511‧‧‧開孔
52‧‧‧第二介電層
521‧‧‧開孔
53‧‧‧第三介電層
54‧‧‧第四介電層
541‧‧‧開孔
61‧‧‧第一層線路
62‧‧‧第二層線路
63‧‧‧第三層線路
70‧‧‧錫球
80‧‧‧電路元件
90‧‧‧載具
901‧‧‧對準圖案
902‧‧‧對準圖案
91‧‧‧第二基板
911‧‧‧第一平面
9111‧‧‧線路
912‧‧‧第二平面
9121‧‧‧線路
913‧‧‧容置空間
92‧‧‧晶片
921‧‧‧鋁墊
93‧‧‧黏膠材料
94‧‧‧第一基板
941‧‧‧線路
95‧‧‧薄刀
圖1係本新型第一較佳實施例之剖面示意圖。 圖2~圖7係本新型第一較佳實施例之製作流程示意圖。 圖8係本新型第二較佳實施例之剖面示意圖。 圖9係本新型第三較佳實施例之剖面示意圖。 圖10係本新型第四較佳實施例之剖面示意圖。 圖11~圖16係一般的半導體封裝結構之製作流程示意圖。
11‧‧‧第一基板
111‧‧‧對準圖案
12‧‧‧第二基板
121‧‧‧容置孔
21‧‧‧第一膠層
22‧‧‧第二膠層
31‧‧‧第一導通孔
32‧‧‧第二導通孔
40‧‧‧晶片
41‧‧‧鋁墊
51‧‧‧第一介電層
511‧‧‧開孔
52‧‧‧第二介電層
53‧‧‧第三介電層
61‧‧‧第一層線路
62‧‧‧第二層線路
63‧‧‧第三層線路
70‧‧‧錫球

Claims (6)

  1. 一種平板式半導體封裝結構，係包含有： 一第一基板； 一第二基板，係設置於該第一基板之上表面，且形成有一容置孔； 一第一膠層，係夾設於該第一基板與該第二基板之間，以黏合該第一基板及該第二基板；其中該第一基板之下表面係形成有一第一層線路，而該第二基板上表面形成有一第二層線路； 至少一第一導通孔，係貫穿形成於該第二基板、第一膠層及該第一基板中，且該至少一第一導通孔內填充有導電材料，而該第一層線路與該第二層線路係透過填充有導電材料的至少一第一導通孔電性連接； 一晶片，係設置於該第二基板的容置孔中，而該晶片之上表面係形成有至少一鋁墊； 一第二膠層，係夾設於該晶片與該第二基板的容置孔內壁之間，以黏合該晶片與該第二基板； 一第一介電層，係設置於該第一基板之下表面，且形成有至少一開孔，以連通該第一層線路； 一第二介電層，係設置於該第二基板之上表面，且貫穿形成有複數第二導通孔，而該些第二導通孔係分別連通該第二層線路及該晶片之鋁墊，並於該些第二導通孔中填充有導電材料；其中該第二介電層之上表面係形成有一第三層線路，且該第三層線路與該第二層線路及該晶片之鋁墊係透過填充有導電材料的該些第二導通孔電性連接； 一第三介電層，係設置於該第二介電層之上表面，且覆蓋該第三層線路。
  2. 如請求項1所述之平板式半導體封裝結構，其中： 該第一基板係形成有一對準圖案； 該晶片係對準該第一基板的對準圖案設置。
  3. 如請求項1所述之平板式半導體封裝結構，其中該第一介電層的至少一開孔中係進一步形成有一錫球或導電銲材，且該錫球或該導電銲材凸出該第一介電層的表面，而該錫球或該導電銲材係通過該第一介電層的至少一開孔電性連接該第一層線路。
  4. 如請求項1至3中任一項所述之平板式半導體封裝結構，其中該第三介電層係進一步貫穿形成有複數第三導通孔以連通該第三層線路，且該第三導通孔中填充有導電材料。
  5. 如請求項4所述之平板式半導體封裝結構，其中： 該第三介電層之上表面係進一步形成有一第四介電層； 該第四介電層係貫穿形成有複數開孔，以連通填充有導電材料的該些第三導通孔。
  6. 如請求項1至3中任一項所述之平板式半導體封裝結構，其中： 該晶片係一指紋辨識晶片，且該晶片之上表面係具有一感應區域； 該第二介電層對應該感應區域的位置係形成有一開孔，以連通該晶片的感應區域； 該第三介電層係耐磨材料，並覆蓋該第二介電層之開孔。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111769110A (zh) * 2020-08-06 2020-10-13 谭小春 双面芯片

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111769110A (zh) * 2020-08-06 2020-10-13 谭小春 双面芯片

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