TWI476889B - 在堆疊多晶片封裝中穿矽介層之重組態 - Google Patents

在堆疊多晶片封裝中穿矽介層之重組態 Download PDF

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Publication number
TWI476889B
TWI476889B TW099128670A TW99128670A TWI476889B TW I476889 B TWI476889 B TW I476889B TW 099128670 A TW099128670 A TW 099128670A TW 99128670 A TW99128670 A TW 99128670A TW I476889 B TWI476889 B TW I476889B
Authority
TW
Taiwan
Prior art keywords
integrated circuit
die
layers
signal
vias
Prior art date
Application number
TW099128670A
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English (en)
Chinese (zh)
Other versions
TW201126682A (en
Inventor
羅蘭 舒茲
Original Assignee
考文森智財管理公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 考文森智財管理公司 filed Critical 考文森智財管理公司
Publication of TW201126682A publication Critical patent/TW201126682A/zh
Application granted granted Critical
Publication of TWI476889B publication Critical patent/TWI476889B/zh

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G11C29/808—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout using a flexible replacement scheme
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/297—Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
TW099128670A 2009-10-19 2010-08-26 在堆疊多晶片封裝中穿矽介層之重組態 TWI476889B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US25286509P 2009-10-19 2009-10-19
US12/773,340 US8604593B2 (en) 2009-10-19 2010-05-04 Reconfiguring through silicon vias in stacked multi-die packages

Publications (2)

Publication Number Publication Date
TW201126682A TW201126682A (en) 2011-08-01
TWI476889B true TWI476889B (zh) 2015-03-11

Family

ID=43878833

Family Applications (1)

Application Number Title Priority Date Filing Date
TW099128670A TWI476889B (zh) 2009-10-19 2010-08-26 在堆疊多晶片封裝中穿矽介層之重組態

Country Status (7)

Country Link
US (2) US8604593B2 (https=)
EP (1) EP2491589A4 (https=)
JP (1) JP2013508941A (https=)
KR (1) KR20120085650A (https=)
CN (1) CN102227806A (https=)
TW (1) TWI476889B (https=)
WO (1) WO2011047470A1 (https=)

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US8086913B2 (en) 2008-09-11 2011-12-27 Micron Technology, Inc. Methods, apparatus, and systems to repair memory
US9123552B2 (en) * 2010-03-30 2015-09-01 Micron Technology, Inc. Apparatuses enabling concurrent communication between an interface die and a plurality of dice stacks, interleaved conductive paths in stacked devices, and methods for forming and operating the same
US8362602B2 (en) * 2010-08-09 2013-01-29 Headway Technologies, Inc. Layered chip package and method of manufacturing same
US8916910B2 (en) * 2010-12-13 2014-12-23 Research Foundation Of State University Of New York Reconfigurable RF/digital hybrid 3D interconnect
KR101817156B1 (ko) * 2010-12-28 2018-01-10 삼성전자 주식회사 관통 전극을 갖는 적층 구조의 반도체 장치, 반도체 메모리 장치, 반도체 메모리 시스템 및 그 동작방법
KR101208962B1 (ko) * 2011-02-22 2012-12-06 에스케이하이닉스 주식회사 반도체 장치
US8624626B2 (en) 2011-11-14 2014-01-07 Taiwan Semiconductor Manufacturing Co., Ltd. 3D IC structure and method
US20130159587A1 (en) * 2011-12-15 2013-06-20 Aaron Nygren Interconnect Redundancy for Multi-Interconnect Device
US8933715B2 (en) 2012-04-08 2015-01-13 Elm Technology Corporation Configurable vertical integration
US9448947B2 (en) * 2012-06-01 2016-09-20 Qualcomm Incorporated Inter-chip memory interface structure
US9478502B2 (en) * 2012-07-26 2016-10-25 Micron Technology, Inc. Device identification assignment and total device number detection
US9026872B2 (en) * 2012-08-16 2015-05-05 Xilinx, Inc. Flexible sized die for use in multi-die integrated circuit
KR102058101B1 (ko) * 2012-12-20 2019-12-20 에스케이하이닉스 주식회사 반도체 집적회로
KR102190382B1 (ko) 2012-12-20 2020-12-11 삼성전자주식회사 반도체 패키지
US9612988B2 (en) * 2013-07-23 2017-04-04 International Business Machines Corporation Donor cores to improve integrated circuit yield
US20150155039A1 (en) * 2013-12-02 2015-06-04 Silicon Storage Technology, Inc. Three-Dimensional Flash NOR Memory System With Configurable Pins
US9245825B2 (en) 2014-01-23 2016-01-26 Sandisk Technologies Inc. I/O pin capacitance reduction using TSVS
US9501603B2 (en) 2014-09-05 2016-11-22 International Business Machines Corporation Integrated circuit design changes using through-silicon vias
US10002653B2 (en) 2014-10-28 2018-06-19 Nxp Usa, Inc. Die stack address bus having a programmable width
KR102290020B1 (ko) * 2015-06-05 2021-08-19 삼성전자주식회사 스택드 칩 구조에서 소프트 데이터 페일 분석 및 구제 기능을 제공하는 반도체 메모리 장치
US9871020B1 (en) * 2016-07-14 2018-01-16 Globalfoundries Inc. Through silicon via sharing in a 3D integrated circuit
US10249590B2 (en) 2017-06-06 2019-04-02 Globalfoundries Inc. Stacked dies using one or more interposers
US11055167B2 (en) * 2018-05-14 2021-07-06 Micron Technology, Inc. Channel-scope proximity disturb and defect remapping scheme for non-volatile memory
US10838831B2 (en) * 2018-05-14 2020-11-17 Micron Technology, Inc. Die-scope proximity disturb and defect remapping scheme for non-volatile memory
US11048597B2 (en) * 2018-05-14 2021-06-29 Micron Technology, Inc. Memory die remapping
CN112102862B (zh) * 2020-09-22 2023-03-07 武汉新芯集成电路制造有限公司 芯片结构、数据读取处理方法及芯片结构制造方法
US11226767B1 (en) * 2020-09-30 2022-01-18 Micron Technology, Inc. Apparatus with access control mechanism and methods for operating the same
US11468945B2 (en) * 2020-10-15 2022-10-11 Arm Limited 3D storage architecture with tier-specific controls
US20250209027A1 (en) * 2023-12-22 2025-06-26 Intel Corporation Resilient i/o interconnect

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Also Published As

Publication number Publication date
CN102227806A (zh) 2011-10-26
EP2491589A1 (en) 2012-08-29
TW201126682A (en) 2011-08-01
US20140097891A1 (en) 2014-04-10
EP2491589A4 (en) 2015-07-22
US20110090004A1 (en) 2011-04-21
US9117685B2 (en) 2015-08-25
WO2011047470A1 (en) 2011-04-28
US8604593B2 (en) 2013-12-10
JP2013508941A (ja) 2013-03-07
KR20120085650A (ko) 2012-08-01

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