WO2008026388A1 - Multi-chip type semiconductor device - Google Patents

Multi-chip type semiconductor device Download PDF

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Publication number
WO2008026388A1
WO2008026388A1 PCT/JP2007/063834 JP2007063834W WO2008026388A1 WO 2008026388 A1 WO2008026388 A1 WO 2008026388A1 JP 2007063834 W JP2007063834 W JP 2007063834W WO 2008026388 A1 WO2008026388 A1 WO 2008026388A1
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WIPO (PCT)
Prior art keywords
semiconductor chip
chip
semiconductor device
semiconductor
pad
Prior art date
Application number
PCT/JP2007/063834
Other languages
French (fr)
Japanese (ja)
Inventor
Masaya Matsunaga
Masanori Hirofuji
Hiroyuki Noda
Yutaka Yamada
Tomomi Takebayashi
Yasuo Sogawa
Daisuke Ozawa
Norihiko Ohtomo
Original Assignee
Panasonic Corporation
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Publication date
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Publication of WO2008026388A1 publication Critical patent/WO2008026388A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/62—Protection against overvoltage, e.g. fuses, shunts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/642—Capacitive arrangements
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/647—Resistive arrangements
    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
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    • H01L2924/01005—Boron [B]
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    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
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    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
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    • H01L2924/30—Technical effects
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    • H01L2924/3011—Impedance

Definitions

  • the present invention relates to a structure of a multichip (a plurality of semiconductor chips) existing in a package of a semiconductor device.
  • Patent Document 1 Japanese Patent Laid-Open No. 10-41458 (Page 1, Figure 1)
  • the present invention moves or shares a function in one semiconductor chip in a multi-chip into another semiconductor chip that has a free area inside or has a low chip cost. Make it.
  • the force S can be reduced to reduce the manufacturing cost of the entire semiconductor chip in the multichip.
  • FIG. 1 is a diagram showing a configuration example of a multichip semiconductor device according to an embodiment of the present invention.
  • FIG. 2 is a diagram showing a form of a semiconductor device before transferring a function (capacitance element).
  • FIG. 3 is a diagram showing a form of the semiconductor device after the function (capacitance element) is transferred. 4] FIG. 4 is a diagram showing the form of the semiconductor device before the function (capacitance element) is transferred. 5] FIG. 5 is a diagram showing the form of the semiconductor device after the function (capacitance element) is transferred.
  • FIG. 6 is a diagram showing a form of a semiconductor device in which a capacitive element is coupled.
  • FIG. 7 is a diagram showing a form of a semiconductor device in which an option that can change a capacitive element by an element that forms a mask is formed.
  • FIG. 8 is a diagram showing a configuration of the semiconductor device in which the capacitive element can be switched by changing the wire.
  • FIG. 9 is a diagram showing the configuration of the semiconductor device in which the output of the capacitive element can be switched by the selector.
  • FIG. 10 is a diagram showing a form of the semiconductor device before the function (resistive element) is transferred.
  • FIG. 11 is a diagram showing the form of the semiconductor device after the function (resistive element) is transferred.
  • FIG. 12 is a diagram showing a structural example of the resistance element to be transferred.
  • FIG. 13 is a diagram showing a structure example of the resistance element to be transferred.
  • FIG. 14 is a diagram showing a pull-down resistor circuit.
  • FIG. 15 is a diagram showing a pull-up resistor circuit.
  • FIG. 16 is a diagram showing a resistor circuit including a circuit forming a plurality of pull-up resistors and a circuit forming a plurality of pull-down resistors.
  • FIG. 17 is a diagram showing a damping resistance circuit having a plurality of resistance values.
  • FIG. 18 is a diagram showing a configuration of the semiconductor device before the function (protection circuit) is transferred.
  • FIG. 19 is a diagram showing the form of the semiconductor device after the function (protection circuit) is transferred.
  • FIG. 20 is a diagram showing the configuration of the semiconductor device before the function (IO cell not directly connected to the end of the external package with a wire) is transferred.
  • FIG. 21 is a diagram showing the form of the semiconductor device after the function (IO cell not directly connected to the end of the external package with a wire) is transferred.
  • FIG. 22 is a diagram showing an arrangement form in a case where there is no space for additional IO cells in the IO cell area of the second semiconductor chip and there is a space in the internal area.
  • Fig. 23 is a diagram showing a form of the semiconductor device to which the function (fuse element) is transferred.
  • FIG. 24 is a diagram showing a form of a semiconductor device to which a function (fuse element) is transferred.
  • FIG. 25 is a diagram showing a form of a semiconductor device to which a function (fuse element) is transferred.
  • FIG. 26 is a diagram showing a form of a semiconductor device to which a function (fuse element) is transferred.
  • FIG. 27 is a diagram showing a form of a semiconductor device to which a function (power supply wiring) is transferred.
  • FIG. 28 is a diagram showing a form of a semiconductor device to which a function (power supply wiring) is transferred.
  • FIG. 29 is a diagram showing a form of a semiconductor device to which a function (dummy cell) is transferred.
  • FIG. 30 is a diagram showing a form of a semiconductor device to which functions (dummy cells) are transferred.
  • 31] FIG. 31 is a diagram showing a form of a semiconductor device to which functions (dummy cells) are transferred.
  • FIG. 32 is a diagram showing a form of a semiconductor device to which a function (dummy cell) is transferred.
  • FIG. 33 is a diagram showing a form of a semiconductor device to which a function (dummy cell) is transferred.
  • FIG. 34 is a diagram showing a configuration of a semiconductor device to which functions (dummy cells) are transferred.
  • 35 is a diagram showing a form of a semiconductor device to which the function (delay adjustment circuit) is transferred.
  • FIG. 36 is a diagram illustrating an example of a delay adjustment circuit.
  • FIG. 37 is a diagram showing a form of a semiconductor device to which the function (delay adjustment circuit) is transferred.
  • FIG. 38 is a diagram showing a form of a semiconductor device to which the function (delay adjustment circuit) is transferred.
  • FIG. 39 is a diagram showing a form of a semiconductor device to which a function (spare circuit) is transferred.
  • FIG. 40 is a diagram showing the configuration of the semiconductor device before the function (test circuit) is transferred
  • FIG. 40 (b) is a diagram showing the form of the semiconductor device after the function (test circuit) is transferred.
  • FIG. 41 (a) shows the configuration of the semiconductor device before the function (BIST circuit) is transferred
  • FIG. 41 (b) shows the configuration of the semiconductor device after the function (BIST circuit) is transferred.
  • FIG. 42 (a) is a diagram showing the configuration of the semiconductor device before the function (boundary scan circuit) is transferred
  • FIG. 42 (b) is a diagram showing the semiconductor device after the function (boundary scan circuit) is transferred.
  • Capacitance element 7-05
  • FIG. 1 A configuration example of a semiconductor device according to an embodiment of the present invention is shown in FIG.
  • the semiconductor device according to the present embodiment is a multi-chip type semiconductor device having two or more semiconductor chips in a semiconductor package.
  • the arrangement of the semiconductor chips is a force S having a parallel arrangement type and a stacked arrangement type, and FIG. 1 shows the parallel arrangement type.
  • connection between the semiconductor package and the semiconductor chip is configured such that the lead frame of the semiconductor package and the pad of the semiconductor chip are electrically connected by wire bonding.
  • the pad is electrically connected by wire bonding (L, so-called MCM configuration)!
  • the semiconductor device allows a certain semiconductor chip (first semiconductor chip 1-01) in a package to function with another semiconductor chip (second semiconductor chip 1) under various predetermined conditions. -02) is moved to a certain area (1-03), and the transferred functions are shared.
  • Functions to be transferred include capacitive elements, resistance elements, electrostatic withstand voltage protection circuits, protection circuits between power supplies, electrical fuse elements, power supply wiring, dummy cells, delay cells, spare circuits, and test circuits. Will be described in detail later.
  • transfer source and transfer destination semiconductor chips are not limited to one. In package If there are three or more semiconductor chips, the functions can be transferred from multiple transfer sources to multiple transfer destinations.
  • the second semiconductor chip 1-02 is in the IO risk state (chip size is determined by the IO cell placement area) and has a free area inside the chip, the first semiconductor chip 1-01 to the second semiconductor chip 1-02 Move function to the free space.
  • IO Ritsoku occurs when there are many IO cells connected to external pins by consolidating a multifunctional system on one chip (SOC). This also occurs when the internal sig- nal of the semiconductor chip is reduced due to the miniaturization of the diffusion process, and the io cell cannot be reduced in order to maintain its characteristics.
  • SOC system on one chip
  • IO cell placement restrictions due to package assembly restrictions that cause a problem even if wire flow occurs in order to prevent wire shorts in the package, restrictions that allow the IO cells to be widened), or due to needle contact during probe inspection tests
  • Due to IO cell placement restrictions when the probe of the inspection device is probed to the semiconductor chip pad at the time of probe inspection, the needle cannot be applied due to the shape of the inspection device, so that the IO cells are physically widened) Affects.
  • the first semiconductor chip 1-01 to the second semiconductor Move the function to the free space in chip 1-02.
  • the mask layer area ratio (ratio of the mask layer area occupied in the semiconductor chip area) is too small or too large during wafer polishing in the mask diffusion process, there is a difference in film thickness in polishing. And process characteristics may deviate from target values. In order to avoid this, it is necessary to keep the area ratio during layout design.
  • the space factor is larger than the specified value, there may be a case where an area where nothing is arranged in the area inside the chip is secured in order to protect this area ratio. For example, reducing the area ratio of the gate (polysilicon) of memory (Flash, SRAM, ROM, DRAM) Therefore, a free area is secured. Put the standard cell with a small gate area in this empty area and transfer the function.
  • the first semiconductor chip 1-01 to the empty area of the second semiconductor chip 1-02 Move function.
  • the second semiconductor chip 1-02 has a configuration with a lower manufacturing cost due to a larger manufacturing process size or fewer diffusion layers than the first semiconductor chip 1-01, the first semiconductor chip The function is transferred from 1-01 to the second semiconductor chip 1-02.
  • the second semiconductor chip 1-02 has a configuration in which the mask reticle cost is low due to a larger manufacturing process size (larger photographic dimensions) than the first semiconductor chip 1-01, The function is transferred from the semiconductor chip 1-01 to the second semiconductor chip 1-02.
  • the function is transferred from the first semiconductor chip 1-01 to the second semiconductor chip 1-02.
  • the second semiconductor chip 1-02 When the second semiconductor chip 1-02 has a configuration with high timing convergence due to the high current capability (speed) of the transistor due to the difference in manufacturing process compared to the first semiconductor chip 1-01, the first semiconductor chip 1-02 The function is transferred from the semiconductor chip 1-01 to the second semiconductor chip 1-02.
  • the second semiconductor chip 1-02 has a configuration with high duty guarantee accuracy due to the difference in current capability of the Pch transistor and Nch transistor due to the difference in the manufacturing process compared to the first semiconductor chip 1-01, The function is transferred from the first semiconductor chip 1-01 to the second semiconductor chip 1-02.
  • the adjustment buffer and the function itself can be replaced with the second semiconductor chip 1-02 with high duty guarantee accuracy. Make up.
  • FIG. 2 shows the form of the semiconductor device before the function is transferred.
  • the first semiconductor chip 1-02 has a vacant area or the LSI manufacturing cost is low.
  • the capacitive element 2-03 of the body chip 1-01 is transferred to the second semiconductor chip 1-02.
  • the area of the first semiconductor chip 1-01 is reduced, and the empty area of the second semiconductor chip 1-02 is effectively utilized.
  • FIG. 4 shows the form of the semiconductor device before the function is transferred.
  • the capacitive element 4-03 of the first semiconductor chip 1-01 is moved to the second semiconductor chip 1-02. .
  • the area of the first semiconductor chip 1-01 is reduced, and the empty area of the second semiconductor chip 1-02 is effectively utilized.
  • the second semiconductor chip 1-02 has a free space.
  • the capacitive element 2-03 of the first semiconductor chip 1-01 is coupled to the capacitive element 2-04 of the second semiconductor chip 1-02.
  • the area of the first semiconductor chip 1-01 is reduced, and the empty area of the second semiconductor chip 1-02 is effectively utilized.
  • FIG. 7 As shown in FIG. 7, several types of capacitive elements 7-03, 7-04, etc. are arranged in advance in the empty area of the second semiconductor chip 1-02. At this time, options 7-07, 7-08, etc., in which the capacitive element 7-03 and the capacitive element 7-04 can be changed by the elements forming the mask, are formed. In this way, by adopting a configuration that can make effective use of the vacant area and a configuration that can correct the elements forming the mask with the minimum number of elements, the configuration can be improved with ease and can be corrected at low cost.
  • capacitors 9-03 and 9-04 are configured such that the output can be switched by the selector 9-08 in accordance with the output of the register 9-09.
  • FIG. 10 shows a form of the semiconductor device before the function is transferred.
  • FIG. 10 shows an example of a stacked multi-chip semiconductor device in which the first semiconductor chip 1-01 is disposed on the upper surface and the second semiconductor chip 1-02 is disposed on the lower surface.
  • the resistor 10-03 when the resistor 10-03 is in the IO cell area of the first semiconductor chip 1-01 and the resistor 10-04 is in the internal area, these resistive elements are not connected to the first area.
  • 1 Move to the second semiconductor chip 1-0 2 which is lower in manufacturing cost than the semiconductor chip 1-01. As a result, it is possible to reduce useless areas and costs.
  • FIG. 11 as the configuration when moving to the second semiconductor chip 1-02, for example, it is moved to the IO cell region like the resistor 10-03, or placed in the internal region like the resistor 10-04. Can be considered.
  • the structure of the resistor elements 10-03 and 10-04 to be transferred is not limited to the structure as shown in 12-01 of FIG. 12, but a pull-down resistor as shown in 12-02 of FIG. Pull-up resistors as shown in 13-13-01 are also included.
  • pull-down resistor As the pull-down resistor, as shown in the pull-down resistor circuit 14-01 in Figure 14, multiple pull-down resistors with different resistance values are prepared, and the location where the via 14-02 that connects the resistor and the main line is generated is selected. By changing it, it becomes possible to obtain the pull-down resistance value as needed.
  • the pull-up resistor As the pull-up resistor, a plurality of pull-up resistors having different resistance values are prepared as shown in the pull-up resistor circuit 15-01 in FIG. 15, and a via 15-02 connecting the resistor and the main line is generated. By selecting and changing the location, it is possible to obtain a pull-up resistance value as required.
  • a resistor circuit including a circuit 14-01 that constitutes a plurality of pull-up resistors and a circuit 15-01 that constitutes a plurality of pull-down resistors is configured, and vias 16- By making it possible to change the location where 03 is generated, the required pull-up and pull-down functions It is also possible to obtain a resistance value.
  • a method for selecting an arbitrary pull-up resistor and pull-down resistor it is possible to adopt a configuration similar to that shown in the above functions 4 to 6 (FIGS. 7 to 9).
  • a damping resistor circuit 17-01 having a plurality of resistance values is prepared, and the location where the via 17-02 that connects the damping resistor and the main signal line is generated is changed. You may do it. As a result, a desired damping resistance value can be obtained by generating the via 17-02 at an arbitrary location.
  • a method for selecting an arbitrary damping resistor it is possible to adopt a configuration similar to that shown in the above functions 4 to 6 (FIGS. 7 to 9).
  • FIG. 18 illustrates a semiconductor device before the function is transferred.
  • FIG. 18 shows an example of a stacked multi-chip semiconductor device in which the first semiconductor chip 1-01 is disposed on the upper surface and the second semiconductor chip 1-02 is disposed on the lower surface.
  • the right side of the second semiconductor chip 1-02 has no connection to the outside of the multi-chip semiconductor device and the IO cell region 18-04 is empty.
  • the circuit configuration of the protection circuit 18-06 which has a large electrostatic withstand voltage and latch-up withstand voltage of the IO cell 18-03, is transferred to the IO cell empty area of the second semiconductor chip 1-02.
  • the semiconductor device of FIG. 19 can be obtained, and the area of the first semiconductor chip 1-01 can be reduced by effectively utilizing the empty area of the second semiconductor chip 1-02.
  • the protection circuit 18-06 listed here is an example, and electrostatic withstand voltage and latch-up withstand voltage.
  • FIG. 20 As shown in Fig. 20, there is an IO cell 20-02 in the IO cell area of the first semiconductor chip 1-01, not directly connected to the end of the external package! /, This IO cell 20-02 exists Thus, when the length L1 of one side of the first semiconductor chip 1-01 cannot be further reduced, and there is an empty area without IO cells on one side of the second semiconductor chip 1-02, FIG. As shown in FIG. 2, the configuration of the IO cell 20-02 is moved as an IO cell in the region of the second semiconductor chip 1-02. As a result, the IO cell 20-02 can be reduced from the first semiconductor chip 1-01, and as a result, one side of the first semiconductor chip 1-01 can be shortened (L1 ⁇ L2). The area can be reduced.
  • IO cell 20-02 Note that the internal structure of the IO cell 20-02 is not a problem here.
  • An example is an IO cell with an inter-power protection circuit 20-03 as shown in Figs.
  • an electrically cuttable fuse element (hereinafter referred to as “electric fuse”) 23-4 for controlling the circuit 23-3 of the first semiconductor chip 1-01 is connected to the second semiconductor chip 1 Place in the -02 free space.
  • the first semiconductor chip 1-01 and the second semiconductor chip 1-02 are connected to the signal input / output pad 23-5 of the circuit 23-3, the signal input / output pad 23-6 of the electric fuse 23-4, and the wire 23- By connecting at 7, it is electrically connected.
  • the power of circuit 23-3 While maintaining the control function by the air fuse 23-4, it is possible to reduce the chip size of the first semiconductor chip 1-01 and to effectively use the empty area of the second semiconductor chip 1-02.
  • the electrical fuse 24-4 is a fuse element that controls the power supply potential of the internal power supply potential adjustment circuit 24-3 of the first semiconductor chip 1-01.
  • the second semiconductor chip 1- Arranged in 02 free space.
  • the pad 24-5 and the pad 24-6 are electrically connected by the wire 24-7, and the control signal of the internal power supply potential adjustment circuit 24-3 is the pad 24-5, the wire 24-7, the pad 24- 6 is input to the electrical fuse 24-4.
  • pad 24-8 and pad 24-9 are electrically connected by wire 24-10, and the output signal of electric fuse 24-4 is pad 24-9, wire 24-10, pad 24- 8 is input as a control signal to the internal power supply potential adjustment circuit 24-3.
  • the electrical fuse 25-5 is a fuse element that selectively controls the functional circuit 25-3 and the functional circuit 25-4 of the first semiconductor chip 1-01, and the second semiconductor chip 1 It is placed in the free space of -02.
  • Pad 25-6 and pad 25-7 are electrically connected by wire 25-8, and the output signal or input signal of functional circuit 25-3 is pad 25-6, wire 25-8, pad 25- 7 is input to or output from the electrical fuse 25-5.
  • pad 25-9 and pad 25-10 are electrically connected by wire 25-11, and the output signal or input signal of functional circuit 25-4 is pad 25-9, wire 25-1 1, Input to or output from electrical fuse 25-5 via pad 25-10.
  • the function circuit 25-3 and the function circuit 25-4 can be selected and controlled by the electric fuse 25-5, and the function of the first semiconductor chip 1-01 can be adjusted. In this way, while maintaining the function adjustment function of the first semiconductor chip 1-01, it is possible to reduce the chip size of the first semiconductor chip 1-01 and effectively use the free space of the second semiconductor chip 1-02. It becomes feasible.
  • the electric fuse 26-3 is an electric fuse group having a plurality of outputs, and is a fuse element that controls pull-up and pull-down of the pad group 26-4.
  • the pad group 26-4 is electrically connected to the lead end group 26-6 by a wire group 26-5.
  • the chip of the first semiconductor chip 1-01 is connected from the lead end 26-6 via the wire group 26-5.
  • An identification signal is output. In this way, while maintaining the chip identification function of the first semiconductor chip 1-01, the chip size of the first semiconductor chip 1-01 is reduced and the free space of the second semiconductor chip 1-02 is effectively utilized. Is possible.
  • power is supplied to the pad 27-06 of the second semiconductor chip 1-02 via the lead end 27-11 and the wire 27-04.
  • the pad 27-06 is connected to the pad 27-05 of the second semiconductor chip 1-02 by the power wiring 27-08. Furthermore, connect pad 27-05 of the second semiconductor chip 1-02 and pad 27-07 of the first semiconductor chip 1-01 using wire 2 7-03, and connect the power supply wiring 27-09 to module 27-10. To supply power to modules 27-10. In this way, the power wiring area of the first semiconductor chip 1-01 in the conventional method can be reduced, and the chip size of the first semiconductor chip 1-01 can be reduced.
  • the second semiconductor chip 1-02 is used for power supply wiring.
  • the second semiconductor chip 1-02 is used for power supply wiring.
  • the wiring impedance can be lowered by wiring the power supply wiring 27-08 in multiple layers, which is minimal when supplying power to the module 27-10. Power supply can be realized by the power supply voltage effect.
  • FIG. 28 shows a power supply connection method when the first semiconductor chip 1-01 and the second semiconductor chip 1-02 operate at the same potential.
  • Lead end on pad 28-05 of second semiconductor chip 1-02 The power supplied from 28-12 is connected to pad 28-06 of the second semiconductor chip 1_02 using power wiring 28-08.
  • the power supply wiring 28-08 also supplies power to the module 28-10 in the second semiconductor chip 1-02 or the semiconductor element in the second semiconductor chip 1-02.
  • Connect pad 28-06 on the second semiconductor chip 1-02 to pad 28-07 on the first semiconductor chip 1-01 with wire 2 8-04, and connect power supply wiring 28-09 to module 28-11 1 Power is supplied to the first semiconductor chip 1-01 by connecting to the semiconductor elements in the semiconductor chip 1-01.
  • the power supply wiring area of the first semiconductor chip 1-01 or the second semiconductor chip 1-02 It is possible to reduce the chip size of the first semiconductor chip 1-01 or the second semiconductor chip 1-02.
  • FIG. 29 shows an example of a stacked multi-chip semiconductor device in which the first semiconductor chip 1-01 is disposed on the upper surface and the second semiconductor chip 1-02 is disposed on the lower surface.
  • the first semiconductor chip 1-01 is disposed on the upper surface and the second semiconductor chip 1-02 is disposed on the lower surface.
  • this is used for the first semiconductor chip 1-0 and the second semiconductor chip 1-02 having a low manufacturing cost.
  • free space 29-04 it is possible to reduce wasteful space and reduce costs.
  • the signal 31-03 in the first semiconductor chip 1-01 is connected to the dummy pad 31-05, and the dummy pad 31-05 is connected to the second semiconductor chip by the wire 31-09. Connected to pad 31-06 of 1-02. Pad 31-06 and pad 31-07 are connected by wiring 31-04. The pad 31-07 is connected to the dummy pad 31-08 of the first semiconductor chip 1-01 by the wire 31-10.
  • pad 31-07 is a signal whose logic has been corrected using dummy cell 31-11 in which wiring 31-04 is moved to second semiconductor chip 1-02.
  • the first semiconductor chip 1-01 does not need to be modified by changing the configuration to connect to the first semiconductor chip 1-01. By doing so, it can be corrected with the second semiconductor chip 1-02, which has low cost for slicing and mask production, which is effective for cost reduction.
  • the signal 31-03 in the first semiconductor chip 1-01 Is connected to the pad 31-05, and the pad 31-05 is connected to the node 31-06 of the second semiconductor chip 1-02 by the wire 31-08.
  • Pad 31-06 and pad 31-07 are connected by wiring 31-04.
  • Node 31-07 is connected to lead end 31-10 by wire 31-09.
  • the second semiconductor chip 1-02 which has a low slicing cost and mask manufacturing cost, can be corrected, which is effective for cost reduction.
  • the first semiconductor chip 1-01 Since it is only necessary to provide one dummy pad on the chip, the chip size can be reduced.
  • FIG. 32 shows an example of a stacked multi-chip semiconductor device in which the first semiconductor chip 1-01 is disposed on the upper surface and the second semiconductor chip 1-02 is disposed on the lower surface.
  • Signal 32-03 in the first semiconductor chip 1-01 is connected to pad 32-05 and dummy pad 32-06, and pad 32-05 is connected to lead end 32-12 by wire 32-09. .
  • Pad 32-06 is connected to pad 32-07 of second semiconductor chip 1-02 by wire 32-10.
  • Pads 32-07 and 32-08 are connected by wiring 32-04.
  • the pad 32-08 is connected to the lead end 32-13 by the wire 32-11, and the wire 32-09 is deleted, so that the first semiconductor chip 1-01 need not be modified.
  • the slice cost and the mask manufacturing cost are expensive.
  • the force that had to be corrected with the first semiconductor chip 1-01 The slice cost and the mask manufacturing cost were low. It is possible to correct with semiconductor chip 1-02, which is effective for cost reduction. In addition, it is possible to switch between before and after modification using the wire bonding option.
  • FIG. 33 shows an example of a stacked multi-chip semiconductor device in which the first semiconductor chip 1-01 is disposed on the upper surface and the second semiconductor chip 1-02 is disposed on the lower surface.
  • Signal 33-03 in first semiconductor chip 1-01 is connected to pad 33-05 and dummy pad 33-06, and pad 33-05 is connected to lead end 33-12 by wire 33-09. .
  • Pad 33-06 is connected to the second semiconductor chip by wire 33-10.
  • Pad 33-07 and pad 33-08 are connected by wiring 33-04.
  • the signal whose logic is corrected via the dummy cell 33-14 in which the wiring 33-04 is moved to the second semiconductor chip 1-02 is connected to the pads 33-0 8
  • wire 33-09 is deleted
  • pad 33-08 is connected to lead end 33-12 by wire 33-11, so that it is not necessary to modify the first semiconductor chip 1-01 Become.
  • the slice cost and the mask manufacturing cost are expensive.
  • the force that had to be corrected with the first semiconductor chip 1-01 The slice cost and the mask manufacturing cost were low.
  • the semiconductor chip 1-02 can be modified, which is effective for cost reduction, and the lead ends of the first semiconductor chip 1-01 and the second semiconductor chip 1-02 can be shared. The number of package terminals can be reduced.
  • FIG. 34 shows an example of a stacked multi-chip semiconductor device in which the first semiconductor chip 1-01 is disposed on the upper surface and the second semiconductor chip 1-02 is disposed on the lower surface.
  • the signal 34-03 in the first semiconductor chip 1-01 is connected to the pad 34-05, and the pad 34-05 is connected to the lead end 34-11 by the wire 34-08.
  • the pad 34-06 and the pad 34-07 of the second semiconductor chip 1-02 are connected by the wiring 34-04.
  • wire 34-08 is deleted, pad 34-05 and pad 34-06 are connected by wire 34-09, and wiring 34-04 is the first semiconductor Change the logic corrected signal using dummy cell 34-12 transferred from chip 1-01 to connect to pad 34-07, and connect pad 34-07 and lead end 34-11 with wire 34-10 Change to configuration.
  • This makes it possible to modify the logic without modifying the first semiconductor chip 1-01, which has a high slicing cost and mask manufacturing cost, which is effective for cost reduction, and is provided with a dummy on the first semiconductor chip 1-01.
  • the number of terminals can be reduced, and the lead ends of the first semiconductor chip 1-01 and the second semiconductor chip 1-02 can be shared, and the number of package terminals can be reduced. Become.
  • connection method of the first semiconductor chip 1-01 and the second semiconductor chip 1-02 is as follows.
  • the signal output from pad 35-03 of the first semiconductor chip 1-01 is connected to pad 35-04 using wire 35-08, and the signal is delayed.
  • the signal input to circuit 35-07 and adjusted for delay is connected to pad 35-05, and the signal output from pad 35_05 is connected to pad 35-06 using wire 35-09. Return the signal to -01.
  • FIG. 36 shows details of the delay adjustment circuit 35-07 shown in FIG. As a method for adjusting the delay, the connection position of the output signal wiring 36-06 connected to the output of the delay cell 36-01 to the delay cell 36-05 is changed to adjust the amount of delay!
  • the circuit 35-07 capable of adjusting the delay amount as shown in FIG. 36 is transferred from the first semiconductor chip 1-01 shown in FIG. 35 to the second semiconductor chip 1-02, and the first semiconductor chip 1- It is possible to reduce the area of 01. In this way, in the conventional method, the power required to be corrected by the first semiconductor chip 1-01, which is expensive in slicing cost and mask manufacturing cost. The second semiconductor whose slicing cost and mask manufacturing cost is low. This can be corrected with chip 1-02, which is effective for cost reduction. At the same time, it is possible to reduce the chip size of the first semiconductor chip 1-01.
  • the signal output from the first semiconductor chip 1-01 is sent to the second semiconductor chip 1-02 using the wire 37-10 from the pad 37-03 of the first semiconductor chip 1-01.
  • the signal output from the delay adjustment circuit 37-09 can adjust the delay amount by selecting the output location of the delay cell, and the output of each delay cell is the pad 37 of the second semiconductor chip 1-02. -05 to 37_08 are connected.
  • the selection method of the delay amount can be selected according to the presence / absence of wire bonding of the wires 37_11 to 37-14. In this way, the amount of delay without modifying the inside of the chip can be adjusted, and cost reduction can be realized.
  • the signal output from the first semiconductor chip 1-01 is sent to the second semiconductor chip 1-02 using the wire 38-06 from the pad 38-03 of the first semiconductor chip 1-01. To pad 38-04, and pad 38-04 to delay adjustment circuit 38-05.
  • the amount of delay of the signal output from the delay adjustment circuit 38-05 can be adjusted by selecting the output location of the delay cell, and the output of each delay cell is sent to the multiplexer 38-08. It is connected.
  • the multiplexer selection signal 38-09 is input to the multiplexer 38-08, the output location of the delay cell is selected, and the delay amount is adjusted.
  • FIG. 39 shows an example of a stacked multi-chip semiconductor device in which the first semiconductor chip 1-01 is disposed on the upper surface and the second semiconductor chip 1-02 is disposed on the lower surface.
  • the signal output from the circuit 39-03 in the first semiconductor chip 1-01 is connected to the pad 39-05 and the pad 39-06, and the pad 39-05 is connected to the lead end 39-12 by the wire 39-09.
  • the pad 39-06 is connected to the pad 39-07 of the second semiconductor chip 1-02 by the wire 39-10.
  • the spare circuit 39-04 of the circuit 39-03 in the first semiconductor chip 1-01 is mounted in the second semiconductor chip 1-02, and the pad 39-07 is connected to the spare circuit 39-04.
  • the output from the spare circuit 39-04 is connected to the pad 39-08.
  • the pad 39-08 is connected to the lead end 39-13 by a wire 39-11.
  • the spare circuit 39-04 it is possible to switch to the spare circuit 39-04 by simply switching the lead end 39-12 and the lead end 39-13 by wire bonding, and the second semiconductor chip 1-02 Chip size can be reduced by making effective use of free space.
  • the mask manufacturing cost is not required for the correction, and the cost can be reduced.
  • As an example of how to use the spare circuit 39-04 there are cases where a circuit with a different function and a different configuration is implemented as an insurance circuit, or when a specification change is realized by implementing a circuit with a different specification. Conceivable.
  • FIG. 40 shows an example of a stacked multi-chip semiconductor device in which the first semiconductor chip 1-01 is disposed on the upper surface and the second semiconductor chip 1-02 is disposed on the lower surface. It is assumed that the manufacturing cost of the second semiconductor chip 1-02 is lower than that of the first semiconductor chip 1-01. In Fig. 40 (a), the test circuit 40-03 in the internal region of the first semiconductor chip 1-01 can be easily transferred to the second semiconductor chip 1-02 as shown in Fig. 40 (b). Can be reduced.
  • FIG. 41 shows an example of a stacked multi-chip semiconductor device in which a first semiconductor chip 1-01 is disposed on the upper surface and a second semiconductor chip 1-02 is disposed on the lower surface. It is assumed that the manufacturing cost of the second semiconductor chip 1-02 is lower than that of the first semiconductor chip 1-01.
  • Fig. 41 (b) shows part or all of the BIST circuit 41-03 (having a test pattern generation function and a judgment function) in the internal region of the first semiconductor chip 1-01 in Fig. 41 (a)
  • the manufacturing cost can be easily reduced by moving to the second semiconductor chip 1-02.
  • FIG. 42 shows an example of a stacked multi-chip semiconductor device in which the first semiconductor chip 1-01 is disposed on the upper surface and the second semiconductor chip 1-02 is disposed on the lower surface. It is assumed that the manufacturing cost of the second semiconductor chip 1-02 is lower than that of the first semiconductor chip 1-01. In FIG. 42 (a), a part or all of the boundary scan circuit 42-03 in the internal region of the first semiconductor chip 1-01 is replaced with the second semiconductor chip 1-02 as shown in FIG. 42 (b). This makes it possible to easily reduce manufacturing costs.
  • the present invention is particularly useful when the process sizes of the semiconductor chips in the multichip are different, or the size of the empty area inside the chip is large.

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Abstract

In a multi-chip in a semiconductor package, the functions of a semiconductor chip (1-01) are moved to or shared by another semiconductor chip (1-02) which can be manufactured at low cost or a semiconductor chip (1-02) having a free region (1-03) in the chip. The functions include a dummy cell, a test circuit, a capacitor cell, a damping resistor, an ESD protection cell, a power supply separation cell, power supply wiring, and an electric fuse. When these functions are moved or shared, chip size of an expensive semiconductor chip can be reduced and the manufacturing cost of the multi-chip can be reduced as a whole.

Description

明 細 書  Specification
マルチチップ型半導体装置  Multi-chip type semiconductor device
技術分野  Technical field
[0001] 本発明は、半導体装置のパッケージ内に存在するマルチチップ (複数の半導体チッ プ)の構造に関するものである。  The present invention relates to a structure of a multichip (a plurality of semiconductor chips) existing in a package of a semiconductor device.
背景技術  Background art
[0002] 従来のマルチチップを構成する半導体装置では、半導体チップに必要な機能は、 その半導体チップ内に搭載するか、新たにサブチップを設けている (例えば、特許文 献 1参照)。  [0002] In a conventional semiconductor device constituting a multichip, functions necessary for a semiconductor chip are mounted in the semiconductor chip or a new subchip is provided (for example, see Patent Document 1).
特許文献 1 :特開平 10— 41458号公報 (第 1頁、第一図）  Patent Document 1: Japanese Patent Laid-Open No. 10-41458 (Page 1, Figure 1)
発明の開示  Disclosure of the invention
発明が解決しょうとする課題  Problems to be solved by the invention
[0003] しかしながら、従来の技術では、製造プロセスの高価な半導体チップの面積を増加 させたり、新たにサブチップを設けるためのチップコストが発生したりする課題が出て くる。 [0003] However, in the conventional technology, there are problems such as increasing the area of an expensive semiconductor chip in the manufacturing process and generating a chip cost for newly providing a subchip.
課題を解決するための手段  Means for solving the problem
[0004] 上記課題を解決するために、本発明は、マルチチップ内のある半導体チップ内の 機能を、内部に空き領域を有するもしくはチップコストが安価である別の半導体チッ プ内に移動または共有化させる。 [0004] In order to solve the above problems, the present invention moves or shares a function in one semiconductor chip in a multi-chip into another semiconductor chip that has a free area inside or has a low chip cost. Make it.
発明の効果  The invention's effect
[0005] 本発明によれば、マルチチップ内にある半導体チップ全体としての製造コストを削 減させること力 Sでさる。  [0005] According to the present invention, the force S can be reduced to reduce the manufacturing cost of the entire semiconductor chip in the multichip.
図面の簡単な説明  Brief Description of Drawings
[0006] [図 1]図 1は、本発明の実施形態によるマルチチップ型半導体装置の構成例を示す 図である。  [0006] FIG. 1 is a diagram showing a configuration example of a multichip semiconductor device according to an embodiment of the present invention.
[図 2]図 2は、機能 (容量素子）を移す前の半導体装置の形態を示す図である。  FIG. 2 is a diagram showing a form of a semiconductor device before transferring a function (capacitance element).
[図 3]図 3は、機能 (容量素子）を移した後の半導体装置の形態を示す図である。 園 4]図 4は、機能 (容量素子）を移す前の半導体装置の形態を示す図である。 園 5]図 5は、機能 (容量素子）を移した後の半導体装置の形態を示す図である。 FIG. 3 is a diagram showing a form of the semiconductor device after the function (capacitance element) is transferred. 4] FIG. 4 is a diagram showing the form of the semiconductor device before the function (capacitance element) is transferred. 5] FIG. 5 is a diagram showing the form of the semiconductor device after the function (capacitance element) is transferred.
[図 6]図 6は、容量素子を結合した半導体装置の形態を示す図である。 FIG. 6 is a diagram showing a form of a semiconductor device in which a capacitive element is coupled.
園 7]図 7は、容量素子をマスクを形成する素子で変更可能なオプションを形成した 半導体装置の形態を示す図である。 7] FIG. 7 is a diagram showing a form of a semiconductor device in which an option that can change a capacitive element by an element that forms a mask is formed.
園 8]図 8は、容量素子をワイヤの変更により切り替え可能にした半導体装置の形態 を示す図である。 8] FIG. 8 is a diagram showing a configuration of the semiconductor device in which the capacitive element can be switched by changing the wire.
園 9]図 9は、容量素子をセレクタによって出力切り替え可能にした半導体装置の形 態を示す図である。 9] FIG. 9 is a diagram showing the configuration of the semiconductor device in which the output of the capacitive element can be switched by the selector.
園 10]図 10は、機能 (抵抗素子）を移す前の半導体装置の形態を示す図である。 園 11]図 11は、機能 (抵抗素子)を移した後の半導体装置の形態を示す図である。 園 12]図 12は、移す抵抗素子の構造例を示す図である。 10] FIG. 10 is a diagram showing a form of the semiconductor device before the function (resistive element) is transferred. 11] FIG. 11 is a diagram showing the form of the semiconductor device after the function (resistive element) is transferred. 12] FIG. 12 is a diagram showing a structural example of the resistance element to be transferred.
園 13]図 13は、移す抵抗素子の構造例を示す図である。 13] FIG. 13 is a diagram showing a structure example of the resistance element to be transferred.
[図 14]図 14は、プルダウン抵抗回路を示す図である。 FIG. 14 is a diagram showing a pull-down resistor circuit.
[図 15]図 15は、プルアップ抵抗回路を示す図である。 FIG. 15 is a diagram showing a pull-up resistor circuit.
[図 16]図 16は、複数のプルアップ抵抗を構成する回路や複数のプルダウン抵抗を構 成する回路で構成された抵抗回路を示す図である。  [FIG. 16] FIG. 16 is a diagram showing a resistor circuit including a circuit forming a plurality of pull-up resistors and a circuit forming a plurality of pull-down resistors.
[図 17]図 17は、複数の抵抗値を持つダンピング抵抗回路を示す図である。  FIG. 17 is a diagram showing a damping resistance circuit having a plurality of resistance values.
園 18]図 18は、機能 (保護回路)を移す前の半導体装置の形態を示す図である。 園 19]図 19は、機能 (保護回路)を移した後の半導体装置の形態を示す図である。 園 20]図 20は、機能（直接外部パッケージ端とワイヤで接続しない IOセル)を移す前 の半導体装置の形態を示す図である。 18] FIG. 18 is a diagram showing a configuration of the semiconductor device before the function (protection circuit) is transferred. 19] FIG. 19 is a diagram showing the form of the semiconductor device after the function (protection circuit) is transferred. 20] FIG. 20 is a diagram showing the configuration of the semiconductor device before the function (IO cell not directly connected to the end of the external package with a wire) is transferred.
園 21]図 21は、機能（直接外部パッケージ端とワイヤで接続しない IOセル)を移した 後の半導体装置の形態を示す図である。 21] FIG. 21 is a diagram showing the form of the semiconductor device after the function (IO cell not directly connected to the end of the external package with a wire) is transferred.
[図 22]図 22は、第 2半導体チップの IOセル領域にはすでに IOセルを追加で配置す るスペースがなく内部領域に空きがある場合の配置形態を示す図である。  [FIG. 22] FIG. 22 is a diagram showing an arrangement form in a case where there is no space for additional IO cells in the IO cell area of the second semiconductor chip and there is a space in the internal area.
園 23]図 23は、機能 (ヒューズ素子）を移した半導体装置の形態を示す図である。 Fig. 23 is a diagram showing a form of the semiconductor device to which the function (fuse element) is transferred.
[図 24]図 24は、機能 (ヒューズ素子）を移した半導体装置の形態を示す図である。 [図 25]図 25は、機能（ヒューズ素子）を移した半導体装置の形態を示す図である。 FIG. 24 is a diagram showing a form of a semiconductor device to which a function (fuse element) is transferred. FIG. 25 is a diagram showing a form of a semiconductor device to which a function (fuse element) is transferred.
[図 26]図 26は、機能（ヒューズ素子）を移した半導体装置の形態を示す図である。 園 27]図 27は、機能（電源配線)を移した半導体装置の形態を示す図である。 FIG. 26 is a diagram showing a form of a semiconductor device to which a function (fuse element) is transferred. 27] FIG. 27 is a diagram showing a form of a semiconductor device to which a function (power supply wiring) is transferred.
園 28]図 28は、機能（電源配線)を移した半導体装置の形態を示す図である。 28] FIG. 28 is a diagram showing a form of a semiconductor device to which a function (power supply wiring) is transferred.
[図 29]図 29は、機能（ダミーセル)を移した半導体装置の形態を示す図である。 園 30]図 30は、機能（ダミーセル)を移した半導体装置の形態を示す図である。 園 31]図 31は、機能（ダミーセル)を移した半導体装置の形態を示す図である。 FIG. 29 is a diagram showing a form of a semiconductor device to which a function (dummy cell) is transferred. 30] FIG. 30 is a diagram showing a form of a semiconductor device to which functions (dummy cells) are transferred. 31] FIG. 31 is a diagram showing a form of a semiconductor device to which functions (dummy cells) are transferred.
[図 32]図 32は、機能（ダミーセル)を移した半導体装置の形態を示す図である。 FIG. 32 is a diagram showing a form of a semiconductor device to which a function (dummy cell) is transferred.
[図 33]図 33は、機能（ダミーセル)を移した半導体装置の形態を示す図である。 園 34]図 34は、機能（ダミーセル)を移した半導体装置の形態を示す図である。 園 35]図 35は、機能 (遅延調整回路)を移した半導体装置の形態を示す図である。 FIG. 33 is a diagram showing a form of a semiconductor device to which a function (dummy cell) is transferred. 34] FIG. 34 is a diagram showing a configuration of a semiconductor device to which functions (dummy cells) are transferred. 35] FIG. 35 is a diagram showing a form of a semiconductor device to which the function (delay adjustment circuit) is transferred.
[図 36]図 36は、遅延調整回路の例を示す図である。 FIG. 36 is a diagram illustrating an example of a delay adjustment circuit.
園 37]図 37は、機能 (遅延調整回路)を移した半導体装置の形態を示す図である。 園 38]図 38は、機能 (遅延調整回路)を移した半導体装置の形態を示す図である。 37] FIG. 37 is a diagram showing a form of a semiconductor device to which the function (delay adjustment circuit) is transferred. 38] FIG. 38 is a diagram showing a form of a semiconductor device to which the function (delay adjustment circuit) is transferred.
[図 39]図 39は、機能（予備回路）を移した半導体装置の形態を示す図である。 FIG. 39 is a diagram showing a form of a semiconductor device to which a function (spare circuit) is transferred.
[図 40]図 40 (a)は機能（テスト回路）を移す前、図 40 (b)は機能（テスト回路）を移した 後の半導体装置の形態を示す図である。 [FIG. 40] FIG. 40 (a) is a diagram showing the configuration of the semiconductor device before the function (test circuit) is transferred, and FIG. 40 (b) is a diagram showing the form of the semiconductor device after the function (test circuit) is transferred.
園 41]図 41 (a)は機能（BIST回路）を移す前、図 41 (b)は機能（BIST回路）を移し た後の半導体装置の形態を示す図である。 41] FIG. 41 (a) shows the configuration of the semiconductor device before the function (BIST circuit) is transferred, and FIG. 41 (b) shows the configuration of the semiconductor device after the function (BIST circuit) is transferred.
[図 42]図 42 (a)は機能 (バウンダリスキャン用回路）を移す前、図 42 (b)は機能 (バウ ンダリスキャン用回路)を移した後の半導体装置の形態を示す図である。  [FIG. 42] FIG. 42 (a) is a diagram showing the configuration of the semiconductor device before the function (boundary scan circuit) is transferred, and FIG. 42 (b) is a diagram showing the semiconductor device after the function (boundary scan circuit) is transferred.
符号の説明 Explanation of symbols
(1-01) 第 1半導体チップ (1-01) 1st semiconductor chip
(1-02) 第 2半導体チップ (1-02) Second semiconductor chip
(1-03) 配置領域 (1-03) Placement area
(2-03〜04) 容量素子 (2-03 ~ 04) Capacitance element
(2-05〜06) リード端 (2-05 to 06) Lead end
(2- 07〜08) ワイヤ (3-03〜04) 容量素子 (3-05〜06) リード端 (3- 07〜08) ワイヤ (2- 07 ~ 08) Wire (3-03 ~ 04) Capacitance element (3-05 ~ 06) Lead end (3- 07 ~ 08) Wire
(4-03) 容量素子 (4-03) Capacitance element
(4-04) リード端 (4-04) Lead end
〔4-05) ワイヤ [4-05] Wire
〔5- 05〜06) ワイヤ [5- 05-06] Wire
:6-03) 容量素子 : 6-03) Capacitance element
:6- 04〜07) リード端 :6- 08〜11) ワイヤ : 6-04 ~ 07) Lead end: 6-08 ~ 11) Wire
:7_03〜04) 容量素子 :7-05) リード端 : 7_03 ~ 04) Capacitance element: 7-05) Lead end
:7-06) ワイヤ : 7-06) Wire
:7-07〜08) マスクオプション : 7-07 ~ 08) Mask option
:8-03〜04) 容量素子: 8-03〜04) Capacitance element
:8-05) リード端 : 8-05) Lead end
:8- 06〜07) ワイヤ  : 8-06-07) Wire
:9_03〜04) 容量素子 : 9_03 ~ 04) Capacitance element
:9-05) リード端 : 9-05) Lead end
:9- 06〜07) ワイヤ  : 9-06-07) Wire
:9-08) セレクタ  : 9-08) Selector
9-09) レジスタ  9-09) Register
:10 - 03〜04) 抵抗  : 10-03 ~ 04) Resistance
12 - 01) 抵抗  12-01) Resistance
12- 02) プノレダウン抵抗 12- 02) Punole down resistor
13 - 01) プルアップ抵抗13-01) Pull-up resistor
14 - 01) プルダウン抵抗回路 14 - 02) ビア (15-01) プルアップ抵抗回路 14-01) Pull-down resistor circuit 14-02) Via (15-01) Pull-up resistor circuit
(15-02) ビア (15-02) Via
(16-03) ビア (16-03) Via
(17-01) 複数の抵抗値を持つダンピング抵抗回路  (17-01) Damping resistor circuit with multiple resistance values
(17-02) ビア  (17-02) Via
(18-03) IOセル  (18-03) IO cell
(18-04) IOセル領域  (18-04) IO cell area
(18-06) 保護回路  (18-06) Protection circuit
(19-04) IOセル  (19-04) IO cell
(20-02) 直接外部パッケージ端とワイヤで接続しな!/、IOセル (20-02) Do not connect directly to the end of the external package with wires!
(20-03) 保護回路 (20-03) Protection circuit
(20-04) 電源 A  (20-04) Power supply A
(20-05) 電源 B  (20-05) Power supply B
(21-04) 電源 A  (21-04) Power supply A
(21-05) 電源 B  (21-05) Power supply B
(23-03) 回路  (23-03) Circuit
(23-04) 電気ヒューズ  (23-04) Electrical fuse
(23- 05〜06) パッド  (23- 05-06) Pad
(23-07) ワイヤ  (23-07) Wire
(24-03) 内部電源電位調整回路  (24-03) Internal power supply potential adjustment circuit
(24-04) 電気ヒューズ (24-04) Electrical fuse
(24-05〜06) パッド (24-05-06) Pad
(24-07) ワイヤ (24-07) Wire
(24- 08〜09) パッド (24- 08-09) Pad
(24-10) ワイヤ (24-10) Wire
(25_03〜04) 機能回路 (25_03 ~ 04) Functional circuit
(25-05) 電気ヒューズ (25-05) Electrical fuse
(25- 06〜07) パッド (25-08) ワイヤ (25-06-07) Pad (25-08) Wire
(25- 09〜10) パッド (25-11) ワイヤ (25- 09 to 10) Pad (25-11) Wire
(26-03) 電気ヒューズ (26-04) パッド群 (26-03) Electrical fuse (26-04) Pad group
(26-05) ワイヤ群 (26-05) Wire group
(26-06) リード端群 (27- 03〜04) ワイヤ (27- 05〜07) パッド (27-08〜09) 電源配線(26-06) Lead end group (27-03 to 04) Wire (27-05 to 07) Pad (27-08 to 09) Power supply wiring
(27- -10) モ ユーノレ(27- -10) Mo Yunore
(27- -11) 'ド端 (27- -11)
(28- -03〜04) ワイヤ  (28--03 ~ 04) Wire
(28- - 05〜07) ノ^、  (28--05-07) No ^,
(28- - 08〜09) 電源配線 (28--08 ~ 09) Power supply wiring
(28- - 10〜11) モシュール(28--10-11) Mossur
(28- -12) トド端 (28- -12) Todo end
(29- -03) ダミ一セル (29- -03) Dami cell
(29- -04) ロジ ：ック部 き領:(29- -04) Logistics:
(30- -03〜04) 配線 (30- -03 to 04) Wiring
(30- -05〜08) ノ、、  (30- -05 to 08)
(30- -09〜10) ワイヤ  (30- -09 to 10) Wire
(30- -11) ダミーセノレ (30- -11) Dummy Senore
(31- -03〜04) 酉己糸泉 (31- -03-04) Izumi Izumi
(31- - 05〜07) パッド (31--05-07) Pad
(31- - 08〜09) ワイヤ (31--08 ~ 09) Wire
(31- -10) リード端  (31- -10) Lead end
(31 - -11) ダミ一セル (32-03〜04) 配線 (31--11) Damisel cell (32-03 ~ 04) Wiring
(32- 05〜08) パッド  (32- 05-08) Pad
(32- 09〜11) ワイヤ  (32-09-11) Wire
(32- 12〜13) リード端  (32-12 to 13) Lead end
(32-14) ダミーセノレ  (32-14) Dummy Senore
(33- 03〜04) 配線  (33-03 to 04) Wiring
(33- 05〜08) パッド  (33- 05-08) Pad
(33- 09〜11) ワイヤ  (33-09-11) Wire
(33-12) リード端  (33-12) Lead end
(33-13) ダミーセル  (33-13) Dummy cell
(34-03〜04) 配線  (34-03 ~ 04) Wiring
(34-05〜07) パッド  (34-05-07) Pad
(34-08〜10) ワイヤ  (34-08 ~ 10) Wire
(34-11) リード端  (34-11) Lead end
(34-12) ダミーセノレ  (34-12) Dummy Senore
(35- 03〜06) パッド  (35-03 to 06) Pad
(35-07) 遅延調整回路  (35-07) Delay adjustment circuit
(35- 08〜09) ワイヤ  (35- 08 ~ 09) Wire
(36-01〜05) 遅延セノレ  (36-01 ~ 05) Delay Senor
(36-06) 出力信号配線  (36-06) Output signal wiring
(37- 03〜08) パッド  (37-03-08) Pad
(37-09) 遅延調整回路  (37-09) Delay adjustment circuit
(37- 10〜14) ワイヤ  (37-10-14) Wire
(38- 03〜04) パッド  (38- 03-04) Pad
(38-05) 遅延調整回路  (38-05) Delay adjustment circuit
(38- 06〜07) ワイヤ  (38-06-07) Wire
(38-08) マルチプレクサ  (38-08) Multiplexer
(38-09) マルチプレクサ選択信号 (39-03) 回路 (38-09) Multiplexer selection signal (39-03) Circuit
(39-04) 予備回路  (39-04) Preliminary circuit
(39- 05〜08) パッド  (39- 05 ~ 08) Pad
(39- 09〜11) ワイヤ  (39-09-11) Wire
(39- 12〜13) リード端  (39-12 to 13) Lead end
(40-03) テスト回路  (40-03) Test circuit
(41-03) BIST回路  (41-03) BIST circuit
(42-03) ノ ゥンダリスキャン用回路  (42-03) Noundari scan circuit
発明を実施するための最良の形態  BEST MODE FOR CARRYING OUT THE INVENTION
[0008] 以下、本発明の実施の形態を図面を参照して詳しく説明する。なお、図面において 実質的に同一の部分には同じ参照符号を付してその説明は繰り返さない。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, substantially the same parts are denoted by the same reference numerals, and the description thereof will not be repeated.
[0009] <半導体装置の概略構成〉 <Schematic Configuration of Semiconductor Device>
本発明の実施形態による半導体装置の構成例を図 1に示す。本実施形態による半 導体装置は、半導体パッケージ内に 2つ以上の半導体チップを有するマルチチップ 型半導体装置である。半導体チップの配置は、並列配置型や積層配置型の構成が ある力 S、図 1では並列配置型を記載している。  A configuration example of a semiconductor device according to an embodiment of the present invention is shown in FIG. The semiconductor device according to the present embodiment is a multi-chip type semiconductor device having two or more semiconductor chips in a semiconductor package. The arrangement of the semiconductor chips is a force S having a parallel arrangement type and a stacked arrangement type, and FIG. 1 shows the parallel arrangement type.
[0010] 半導体パッケージと半導体チップの接続は、半導体パッケージのリードフレームと 半導体チップのパッドとで電気的にワイヤボンディングで接続される構成になってお り、半導体チップ同士の接続は、半導体チップのパッドをワイヤボンディングで電気 的に接続する構成 (レ、わゆる MCMの構成)になって!/、る。 [0010] The connection between the semiconductor package and the semiconductor chip is configured such that the lead frame of the semiconductor package and the pad of the semiconductor chip are electrically connected by wire bonding. The pad is electrically connected by wire bonding (L, so-called MCM configuration)!
[0011] 本実施形態による半導体装置は、パッケージ内のある半導体チップ (第 1半導体チ ップ 1-01)のある機能を、所定の各種条件下で、別の半導体チップ (第 2半導体チップ 1-02)内のある領域 (1-03)に移したり、移した機能を共有化したりすることを特徴として いる。 [0011] The semiconductor device according to the present embodiment allows a certain semiconductor chip (first semiconductor chip 1-01) in a package to function with another semiconductor chip (second semiconductor chip 1) under various predetermined conditions. -02) is moved to a certain area (1-03), and the transferred functions are shared.
[0012] 移す機能は、項目として容量素子、抵抗素子、静電耐圧保護回路、電源間保護回 路、電気ヒューズ素子、電源配線、ダミーセル、遅延セル、予備回路、テスト回路があ り、詳細については後に詳細に説明する。  [0012] Functions to be transferred include capacitive elements, resistance elements, electrostatic withstand voltage protection circuits, protection circuits between power supplies, electrical fuse elements, power supply wiring, dummy cells, delay cells, spare circuits, and test circuits. Will be described in detail later.
[0013] なお、移設元及び移設先の半導体チップは 1つには限定されない。パッケージ内 に 3つ以上の半導体チップが存在する構成の場合には、複数の移設元から複数の 移設先へ機能を移すこともありえる。 Note that the transfer source and transfer destination semiconductor chips are not limited to one. In package If there are three or more semiconductor chips, the functions can be transferred from multiple transfer sources to multiple transfer destinations.
[0014] <機能を移す条件〉 [0014] <Conditions for transferring functions>
次に、機能を移す条件にっレ、て以下に列挙して!/、く。  Next, list the conditions below to transfer the functions!
[0015] (条件 1) [0015] (Condition 1)
第 2半導体チップ 1-02が IOリツソク (IOセル配置領域でチップサイズが決定する)状 態となりチップ内部に空き領域を有する場合、第 1半導体チップ 1-01から第 2半導体 チップ 1-02の当該空き領域へ機能を移す。  If the second semiconductor chip 1-02 is in the IO risk state (chip size is determined by the IO cell placement area) and has a free area inside the chip, the first semiconductor chip 1-01 to the second semiconductor chip 1-02 Move function to the free space.
[0016] IOリツソクは多機能なシステムを 1チップに集約すること (SOC)で外部ピンに接続す る IOセルが多数存在するときに起こる。また、拡散プロセスの微細化により、半導体 チップの内部デジタル回路が縮小化する力 s、 ioセルは特性を維持するために縮小 化できない場合にも起こる。半導体チップ内部回路が少なぐ IOセルが多いとチップ 外周に配置するだけで縦横のチップ辺が決まってしまう。さらに、パッケージ組立て による IOセル配置制約 (パッケージ内のワイヤショートを防止するためにワイヤ流れが 起きても問題なレ、よう IOセル間を広げておく制約)、またはプローブ検査テスト時の針 当てによる IOセル配置制約 (プローブ検査時に検査装置の針を半導体チップパッド ヘプローブする際、検査装置の形状上、針あてができなくなるため、物理的に IOセ ル間を広げておく制約)によって、さらにリツソクサイズに影響する。 [0016] IO Ritsoku occurs when there are many IO cells connected to external pins by consolidating a multifunctional system on one chip (SOC). This also occurs when the internal sig- nal of the semiconductor chip is reduced due to the miniaturization of the diffusion process, and the io cell cannot be reduced in order to maintain its characteristics. When there are many IO cells with few internal circuits on the semiconductor chip, the vertical and horizontal chip sides are determined simply by placing them on the outer periphery of the chip. In addition, IO cell placement restrictions due to package assembly (restrictions that cause a problem even if wire flow occurs in order to prevent wire shorts in the package, restrictions that allow the IO cells to be widened), or due to needle contact during probe inspection tests Due to IO cell placement restrictions (when the probe of the inspection device is probed to the semiconductor chip pad at the time of probe inspection, the needle cannot be applied due to the shape of the inspection device, so that the IO cells are physically widened) Affects.
[0017] (条件 2)  [0017] (Condition 2)
第 2半導体チップ 1-02が、拡散工程の歩留まり改善目的で、マスクレイヤの面積率 確保のため、チップ内部に空き領域が必要な構成を持つ場合、第 1半導体チップ 1- 01から第 2半導体チップ 1-02の当該空き領域へ機能を移す。  If the second semiconductor chip 1-02 has a configuration that requires an empty area in the chip to secure the area ratio of the mask layer for the purpose of improving the yield of the diffusion process, the first semiconductor chip 1-01 to the second semiconductor Move the function to the free space in chip 1-02.
[0018] マスク拡散工程のウェハー研磨時にマスクレイヤの面積率 (半導体チップ面積に占 めるマスクレイヤ面積の割合)が少なすぎたり、多すぎたりする場合、研磨での膜厚の ノ ラつきが生じ、プロセス特性が目標値から外れる場合がある。それを回避するため に、レイアウト設計時に面積率を守る必要がある。 占積率が規定値より大きい場合、こ の面積率を守るためにチップ内部の面積に何も配置しない領域を確保する場合があ る。例えば、メモリ (Flash, SRAM, ROM, DRAM)のゲート (ポリシリコン)の面積率を下げ るために、空き領域を確保する。この空き領域にゲート面積の小さいスタンダードセ ルを入れて機能を移す。 [0018] When the mask layer area ratio (ratio of the mask layer area occupied in the semiconductor chip area) is too small or too large during wafer polishing in the mask diffusion process, there is a difference in film thickness in polishing. And process characteristics may deviate from target values. In order to avoid this, it is necessary to keep the area ratio during layout design. When the space factor is larger than the specified value, there may be a case where an area where nothing is arranged in the area inside the chip is secured in order to protect this area ratio. For example, reducing the area ratio of the gate (polysilicon) of memory (Flash, SRAM, ROM, DRAM) Therefore, a free area is secured. Put the standard cell with a small gate area in this empty area and transfer the function.
[0019] (条件 3) [Condition 3]
第 2半導体チップ 1-02が、チップ内部のマクロセルの配置形状によって発生する空 き領域が必要な構成を持つ場合、第 1半導体チップ 1-01から第 2半導体チップ 1-02 の当該空き領域へ機能を移す。  When the second semiconductor chip 1-02 has a configuration that requires an empty area generated by the arrangement shape of the macro cell inside the chip, the first semiconductor chip 1-01 to the empty area of the second semiconductor chip 1-02 Move function.
[0020] 半導体チップは、 SOCにより大規模化され多数のマクロセル (ロジックマクロ、メモリ 、アナログ)を搭載する傾向にある。さらに大規模な半導体チップの製造コストを削減 するため、拡散プロセスの微細化を取り入れる。そうなると、デジタル回路は縮小化さ れるカ アナログ回路は特性上縮小化困難であるため、巨大アナログマクロが多数 占める半導体チップができる。そのような半導体チップをレイアウト設計する場合、巨 大マクロ間に空き領域ができてしまう。この空き領域に機能を移す。  [0020] Semiconductor chips are scaled up by SOC and tend to have a large number of macro cells (logic macro, memory, analog). In order to reduce the manufacturing cost of large-scale semiconductor chips, miniaturization of the diffusion process will be adopted. If this happens, the digital circuit will be scaled down. Because the analog circuit is difficult to scale down due to its characteristics, a semiconductor chip with a large number of huge analog macros will be created. When such a semiconductor chip is designed for layout, an empty area is created between large macros. Move functions to this free space.
[0021] (条件 4)  [0021] (Condition 4)
第 2半導体チップ 1-02が、第 1半導体チップ 1-01に比べ、製造プロセスサイズが大 きい、もしくは、拡散レイヤが少ない理由により、製造コストが安価である構成を持つ 場合、第 1半導体チップ 1-01から第 2半導体チップ 1-02へ機能を移す。  If the second semiconductor chip 1-02 has a configuration with a lower manufacturing cost due to a larger manufacturing process size or fewer diffusion layers than the first semiconductor chip 1-01, the first semiconductor chip The function is transferred from 1-01 to the second semiconductor chip 1-02.
[0022] 製造プロセスが小さくなるとそのための拡散装置や検査装置の投資が必要になり、 1ウェハーあたりの製造コストが高くなる。多層配線や DRAM混載プロセス等で拡散 レイヤが増えるとマスクのレチクル枚数が増加し、拡散過程も増加するため、 1ウエノ、 一あたりの製造コストが高くなる。また、製造プロセスが小さいと拡散層が増加する傾 向にある。  [0022] As the manufacturing process becomes smaller, it becomes necessary to invest in a diffusion device and an inspection device for that purpose, and the manufacturing cost per wafer increases. As the number of diffusion layers increases due to multi-layer wiring and DRAM mixed processes, the number of mask reticles increases and the diffusion process also increases, which increases the manufacturing cost per wafer. In addition, the diffusion layer tends to increase if the manufacturing process is small.
[0023] (条件 5)  [0023] (Condition 5)
第 2半導体チップ 1-02が、第 1半導体チップ 1-01に比べ、製造プロセスサイズが大 きい (フォトグラフィー寸法が大きい)ことにより、マスクのレチクル費が安価である構成 を持つ場合、第 1半導体チップ 1-01から第 2半導体チップ 1-02へ機能を移す。  If the second semiconductor chip 1-02 has a configuration in which the mask reticle cost is low due to a larger manufacturing process size (larger photographic dimensions) than the first semiconductor chip 1-01, The function is transferred from the semiconductor chip 1-01 to the second semiconductor chip 1-02.
[0024] プロセスの微細化により、マスク製作装置及びマスク出来上がり検査装置の費用が 上がっており、マスクのレチクル費もそれに合わせて高価になっている。このため、半 導体チップ内の不具合修正時のマスク費用が問題になってきている。 [0025] (条件 6) With the miniaturization of the process, the cost of the mask manufacturing apparatus and the mask completion inspection apparatus has increased, and the mask cost of the mask has increased accordingly. For this reason, the mask cost when correcting defects in the semiconductor chip has become a problem. [Condition 6]
第 2半導体チップ 1-02が、第 1半導体チップ 1-01に比べ、オフリーク電流の少ない 構成を持つ場合、第 1半導体チップ 1-01から第 2半導体チップ 1-02へ機能を移す。  When the second semiconductor chip 1-02 has a configuration with less off-leakage current than the first semiconductor chip 1-01, the function is transferred from the first semiconductor chip 1-01 to the second semiconductor chip 1-02.
[0026] 携帯電話は、待機電力を抑えることが重要であり、そのためにオフリーク電流を小さ く抑える必要がある。そこで、オフリーク電流を製造プロセス (Vt調整)や基盤制御等 により抑えている。オフリークを抑えたい機能を第 2半導体チップ 1-02へ移すことで待 機電力を小さく抑えることが可能になる。  [0026] In mobile phones, it is important to reduce standby power, and for that purpose, it is necessary to keep off-leakage current small. Therefore, the off-leakage current is suppressed by the manufacturing process (Vt adjustment) and substrate control. It is possible to reduce the standby power by moving the function that wants to suppress off-leakage to the second semiconductor chip 1-02.
[0027] (条件 7)  [0027] (Condition 7)
第 2半導体チップ 1-02が、第 1半導体チップ 1-01に比べ、製造プロセスの違いによ り、トランジスタの電流能力 (スピード)の高いことによるタイミング収束性の高い構成を 持つ場合、第 1半導体チップ 1-01から第 2半導体チップ 1-02へ機能を移す。  When the second semiconductor chip 1-02 has a configuration with high timing convergence due to the high current capability (speed) of the transistor due to the difference in manufacturing process compared to the first semiconductor chip 1-01, the first semiconductor chip 1-02 The function is transferred from the semiconductor chip 1-01 to the second semiconductor chip 1-02.
[0028] (条件 8) [0028] (Condition 8)
第 2半導体チップ 1-02が、第 1半導体チップ 1-01に比べ、製造プロセスの違いによ り、 Pchトランジスタと Nchトランジスタの電流能力バラつきが少ないことによる Duty保証 精度の高い構成を持つ場合、第 1半導体チップ 1-01から第 2半導体チップ 1-02へ機 能を移す。  When the second semiconductor chip 1-02 has a configuration with high duty guarantee accuracy due to the difference in current capability of the Pch transistor and Nch transistor due to the difference in the manufacturing process compared to the first semiconductor chip 1-01, The function is transferred from the first semiconductor chip 1-01 to the second semiconductor chip 1-02.
[0029] 外部へのタイミング調整時に信号パルスの High区間と Low区間を同一に保証する 規定がある場合、調整用のバッファや機能そのものを Duty保証精度の高い第 2半導 体チップ 1-02で構成させる。  [0029] If there is a provision that guarantees the same high and low periods of the signal pulse during external timing adjustment, the adjustment buffer and the function itself can be replaced with the second semiconductor chip 1-02 with high duty guarantee accuracy. Make up.
[0030] (条件 9)  [0030] (Condition 9)
第 2半導体チップ 1-02が、第 1半導体チップ 1-01に比べ、製造プロセスの違いによ り、配線インピーダンスが小さ!/、(シート抵抗が小、線幅制約が大)構成を持つ場合、 第 1半導体チップ 1-01から第 2半導体チップ 1-02へ機能を移す。  When the second semiconductor chip 1-02 has a lower wiring impedance than the first semiconductor chip 1-01 due to the difference in the manufacturing process! /, (Sheet resistance is small, line width constraint is large) The function is transferred from the first semiconductor chip 1-01 to the second semiconductor chip 1-02.
[0031] <移す機能〉 [0031] <Transfer function>
次に、移す機能について以下に列挙していく。  Next, the functions to be transferred are listed below.
[0032] (機能 1 :容量素子） [0032] (Function 1: Capacitance element)
図 2は、機能を移す前の半導体装置の形態を示している。図 2において、第 2半導 体チップ 1-02に空き領域がある場合や、 LSI製造コストが安価な場合等に、第 1半導 体チップ 1-01の容量素子 2-03を第 2半導体チップ 1-02に移す。これにより、図 3のよ うに、第 1半導体チップ 1-01の面積削減や、第 2半導体チップ 1-02の空き領域を有 効活用する構成をとつている。 FIG. 2 shows the form of the semiconductor device before the function is transferred. In Fig. 2, the first semiconductor chip 1-02 has a vacant area or the LSI manufacturing cost is low. The capacitive element 2-03 of the body chip 1-01 is transferred to the second semiconductor chip 1-02. As a result, as shown in FIG. 3, the area of the first semiconductor chip 1-01 is reduced, and the empty area of the second semiconductor chip 1-02 is effectively utilized.
[0033] (機能 2 :容量素子）  [0033] (Function 2: Capacitance element)
図 4は、機能を移す前の半導体装置の形態を示している。図 4において、第 2半導 体チップ 1-02の IOセル配置領域に空き領域がある場合等に、第 1半導体チップ 1-01 の容量素子 4-03を第 2半導体チップ 1-02に移す。これにより、図 5のように第 1半導 体チップ 1-01の面積削減や、第 2半導体チップ 1-02の空き領域を有効活用する構成 をとつている。  FIG. 4 shows the form of the semiconductor device before the function is transferred. In FIG. 4, when there is an empty area in the IO cell placement area of the second semiconductor chip 1-02, the capacitive element 4-03 of the first semiconductor chip 1-01 is moved to the second semiconductor chip 1-02. . As a result, as shown in FIG. 5, the area of the first semiconductor chip 1-01 is reduced, and the empty area of the second semiconductor chip 1-02 is effectively utilized.
[0034] (機能 3 :容量素子）  [0034] (Function 3: Capacitance element)
図 2において、第 1半導体チップ 1-01の容量素子 2-03と、第 2半導体チップ 1-02の 容量素子 2-04が同じ用途等の場合において、第 2半導体チップ 1-02に空き領域が ある場合や、 LSI製造コストが安価な場合等に、第 1半導体チップ 1-01の容量素子 2- 03を第 2半導体チップ 1-02の容量素子 2-04と結合する。これにより、図 6のように、第 1半導体チップ 1-01の面積削減や、第 2半導体チップ 1-02の空き領域を有効活用す る構成をとつている。  In FIG. 2, when the capacitive element 2-03 of the first semiconductor chip 1-01 and the capacitive element 2-04 of the second semiconductor chip 1-02 are used for the same purpose, the second semiconductor chip 1-02 has a free space. In the case where there is a chip or when the LSI manufacturing cost is low, the capacitive element 2-03 of the first semiconductor chip 1-01 is coupled to the capacitive element 2-04 of the second semiconductor chip 1-02. As a result, as shown in FIG. 6, the area of the first semiconductor chip 1-01 is reduced, and the empty area of the second semiconductor chip 1-02 is effectively utilized.
[0035] (機能 4 :容量素子）  [0035] (Function 4: Capacitance element)
図 7に示すように、第 2半導体チップ 1-02の空き領域等に数種類の容量素子 7-03,7 -04等をあらかじめ配置しておく。このとき容量素子 7-03と容量素子 7-04とをマスクを 形成する素子で変更可能なオプション 7-07や 7-08等を形成しておく。このように、空 き領域を有効に活用できる構成、マスクを形成する素子を最小の枚数で修正可能な 構成とすることで、修正の容易性の向上と安価に修正できる構成をとつている。  As shown in FIG. 7, several types of capacitive elements 7-03, 7-04, etc. are arranged in advance in the empty area of the second semiconductor chip 1-02. At this time, options 7-07, 7-08, etc., in which the capacitive element 7-03 and the capacitive element 7-04 can be changed by the elements forming the mask, are formed. In this way, by adopting a configuration that can make effective use of the vacant area and a configuration that can correct the elements forming the mask with the minimum number of elements, the configuration can be improved with ease and can be corrected at low cost.
[0036] (機能 5 :容量素子）  [0036] (Function 5: Capacitance element)
図 8に示すように、第 2半導体チップ 1-02の空き領域等に数種類の容量素子 8-03,8 -04等をあらかじめ配置しておく。このとき容量素子 8-03と容量素子 8-04とをワイヤ 8- 06,8-07の変更により切り替え可能にしておく。このようにすることで、空き領域を有効 に活用できる構成、容量素子をマスクで形成する素子で変更することなくワイヤリング のみの修正できる構成をとつて!/、る。 [0037] (機能 6 :容量素子） As shown in FIG. 8, several types of capacitive elements 8-03, 8-04, etc. are arranged in advance in the empty area of the second semiconductor chip 1-02. At this time, the capacitive element 8-03 and the capacitive element 8-04 can be switched by changing the wires 8-06 and 8-07. In this way, a configuration that can make effective use of the free space and a configuration that can modify only the wiring without changing the capacitance element with an element formed with a mask! [0037] (Function 6: Capacitance element)
図 9に示すように、第 2半導体チップ 1-02の空き領域等に数種類の容量素子 9-03,9 -04等をあら力、じめ配置しておく。このとき、容量素子 9-03,9-04をレジスタ 9-09の出 力に応じてセレクタ 9-08によって出力を切り替え可能な構成をとつている。  As shown in FIG. 9, several types of capacitive elements 9-03, 9-04, etc. are preliminarily arranged in the empty area of the second semiconductor chip 1-02. At this time, the capacitors 9-03 and 9-04 are configured such that the output can be switched by the selector 9-08 in accordance with the output of the register 9-09.
[0038] (機能 7 :抵抗素子）  [0038] (Function 7: Resistance element)
図 10は、機能を移す前の半導体装置の形態を示している。図 10では、上面に第 1 半導体チップ 1-01、下面に第 2半導体チップ 1-02を配置した積層型のマルチチップ 半導体装置の例を示している。図 10に示すように、第 1半導体チップ 1-01の IOセル 領域に抵抗 10-03や内部領域に抵抗 10-04があった場合、これらの抵抗素子を、空き 領域が存在したり、第 1半導体チップ 1-01より製造コストが低い第 2半導体チップ 1-0 2に移す。これにより、無駄な領域の削減やコスト削減を図ることが可能である。図 11 に示すように、第 2半導体チップ 1-02に移す際の構成としては、例えば、抵抗 10-03 のように IOセル領域に移したり、抵抗 10-04のように内部領域に配置したりすることが 考えられる。  FIG. 10 shows a form of the semiconductor device before the function is transferred. FIG. 10 shows an example of a stacked multi-chip semiconductor device in which the first semiconductor chip 1-01 is disposed on the upper surface and the second semiconductor chip 1-02 is disposed on the lower surface. As shown in FIG. 10, when the resistor 10-03 is in the IO cell area of the first semiconductor chip 1-01 and the resistor 10-04 is in the internal area, these resistive elements are not connected to the first area. 1 Move to the second semiconductor chip 1-0 2 which is lower in manufacturing cost than the semiconductor chip 1-01. As a result, it is possible to reduce useless areas and costs. As shown in FIG. 11, as the configuration when moving to the second semiconductor chip 1-02, for example, it is moved to the IO cell region like the resistor 10-03, or placed in the internal region like the resistor 10-04. Can be considered.
[0039] なお、移す抵抗素子 10-03,10-04の構造は、図 12の 12-01に示すような構造には 限られず、図 12の 12-02に示すようなプルダウン抵抗や、図 13の 13-01に示すような プルアップ抵抗も含まれる。  [0039] Note that the structure of the resistor elements 10-03 and 10-04 to be transferred is not limited to the structure as shown in 12-01 of FIG. 12, but a pull-down resistor as shown in 12-02 of FIG. Pull-up resistors as shown in 13-13-01 are also included.
[0040] プルダウン抵抗として、図 14のプルダウン抵抗回路 14-01に示すように複数の抵抗 値の異なるプルダウン抵抗を用意し、抵抗と本線を接続するビア 14-02を生成させる 箇所を選択して変更することで、必要に応じたプルダウン抵抗値を得ることが可能と なる。  [0040] As the pull-down resistor, as shown in the pull-down resistor circuit 14-01 in Figure 14, multiple pull-down resistors with different resistance values are prepared, and the location where the via 14-02 that connects the resistor and the main line is generated is selected. By changing it, it becomes possible to obtain the pull-down resistance value as needed.
[0041] また、プルアップ抵抗として、図 15のプルアップ抵抗回路 15-01に示すように複数 の抵抗値の異なるプルアップ抵抗を用意し、抵抗と本線を接続するビア 15-02を生成 させる箇所を選択して変更することで、必要に応じたプルアップ抵抗値を得ることが 可能となる。  [0041] As the pull-up resistor, a plurality of pull-up resistors having different resistance values are prepared as shown in the pull-up resistor circuit 15-01 in FIG. 15, and a via 15-02 connecting the resistor and the main line is generated. By selecting and changing the location, it is possible to obtain a pull-up resistance value as required.
[0042] さらには、図 16に示すように、複数のプルアップ抵抗を構成する回路 14-01や複数 のプルダウン抵抗を構成する回路 15-01で構成された抵抗回路を構成し、ビア 16-03 を発生させる場所を変更可能とすることで、必要とするプルアップ、プルダウンの機能 及び抵抗値を得ることも可能である。任意のプルアップ抵抗、プルダウン抵抗を選択 する方式としては上記機能 4〜6(図 7〜9)に示したのと同様の構成をとることも可能 である。 [0042] Further, as shown in FIG. 16, a resistor circuit including a circuit 14-01 that constitutes a plurality of pull-up resistors and a circuit 15-01 that constitutes a plurality of pull-down resistors is configured, and vias 16- By making it possible to change the location where 03 is generated, the required pull-up and pull-down functions It is also possible to obtain a resistance value. As a method for selecting an arbitrary pull-up resistor and pull-down resistor, it is possible to adopt a configuration similar to that shown in the above functions 4 to 6 (FIGS. 7 to 9).
[0043] (機能 8 :抵抗素子）  [0043] (Function 8: Resistance element)
第 1半導体チップ 1-01に存在する抵抗回路を第 2半導体チップ 1-02へと移すだけ でなぐ半導体装置外部に接続される外付けのダンピング抵抗を第 2半導体チップ 1 -02へ移すことも可能である。これにより、第 1半導体チップ 1-01の面積削減及び第 2 半導体チップ 1-02の空き領域を有効に活用し、また、外部ダンピング抵抗を取り込む ことで部品数の削減が可能となりシステムを構築する上でのコスト削減が見込まれる It is also possible to transfer an external damping resistor connected to the outside of the semiconductor device to the second semiconductor chip 1-02 simply by transferring the resistor circuit existing in the first semiconductor chip 1-01 to the second semiconductor chip 1-02. Is possible. As a result, the area of the first semiconductor chip 1-01 and the free area of the second semiconductor chip 1-02 can be effectively utilized, and the number of parts can be reduced by incorporating an external damping resistor to construct a system. Cost reduction is expected
〇 Yes
[0044] この際、図 17に示すように、複数の抵抗値を持つダンピング抵抗回路 17-01を用意 し、ダンピング抵抗と信号本線とを接続するビア 17-02を発生させる箇所を変更するよ うにしてもよい。これによりビア 17-02を任意の箇所に発生することにより所望のダンピ ング抵抗値を得ることが可能となる。任意のダンピング抵抗を選択する方式としては 上記機能 4〜6(図 7〜9)に示したのと同様の構成をとることも可能である。  At this time, as shown in FIG. 17, a damping resistor circuit 17-01 having a plurality of resistance values is prepared, and the location where the via 17-02 that connects the damping resistor and the main signal line is generated is changed. You may do it. As a result, a desired damping resistance value can be obtained by generating the via 17-02 at an arbitrary location. As a method for selecting an arbitrary damping resistor, it is possible to adopt a configuration similar to that shown in the above functions 4 to 6 (FIGS. 7 to 9).
[0045] (機能 9 :保護回路）  [0045] (Function 9: protection circuit)
図 18は、機能を移す前の半導体装置の形態を示している。図 18では、上面に第 1 半導体チップ 1-01、下面に第 2半導体チップ 1-02を配置した積層型のマルチチップ 半導体装置の例を示している。図 18に示すように、第 2半導体チップ 1-02の右辺に はマルチチップ半導体装置の外部へと繋がる箇所がなく IOセル領域 18-04が空いて いる場合、第 1半導体チップ 1-01の IOセル 18-03がもつ静電耐圧及びラッチアップ耐 圧の大きい保護回路 18-06を第 2半導体チップ 1-02の IOセル空き領域に回路構成を 移す。これにより、図 19の半導体装置を得、第 2半導体チップ 1-02の空き領域を有 効に活用し、第 1半導体チップ 1-01の面積が削減可能である。  FIG. 18 illustrates a semiconductor device before the function is transferred. FIG. 18 shows an example of a stacked multi-chip semiconductor device in which the first semiconductor chip 1-01 is disposed on the upper surface and the second semiconductor chip 1-02 is disposed on the lower surface. As shown in FIG. 18, the right side of the second semiconductor chip 1-02 has no connection to the outside of the multi-chip semiconductor device and the IO cell region 18-04 is empty. The circuit configuration of the protection circuit 18-06, which has a large electrostatic withstand voltage and latch-up withstand voltage of the IO cell 18-03, is transferred to the IO cell empty area of the second semiconductor chip 1-02. As a result, the semiconductor device of FIG. 19 can be obtained, and the area of the first semiconductor chip 1-01 can be reduced by effectively utilizing the empty area of the second semiconductor chip 1-02.
[0046] また、第 2半導体チップ 1-02に空き領域がなぐ第 1半導体チップ 1-01から削減した 分、第 2半導体チップ 1-02の面積が増加した場合において、第 1半導体チップ 1-01 の製造コスト削減が第 2半導体チップ 1-02の製造コスト増加を上回れば、全体として はコスト面で効果が得られる。 [0047] なお、ここで挙げている保護回路 18-06は一例であり、静電耐圧及びラッチアップ耐
Figure imgf000016_0001
[0046] Further, when the area of the second semiconductor chip 1-02 is increased by the amount reduced from the first semiconductor chip 1-01 in which the second semiconductor chip 1-02 has an empty area, the first semiconductor chip 1- If the manufacturing cost reduction of 01 exceeds the manufacturing cost increase of the second semiconductor chip 1-02, the overall cost effect can be obtained. [0047] Note that the protection circuit 18-06 listed here is an example, and electrostatic withstand voltage and latch-up withstand voltage.
Figure imgf000016_0001
[0048] (機能 10：直接外部パッケージ端とワイヤで接続しな!/、IOセル） [0048] (Function 10: Do not connect directly to the external package end with a wire! /, IO cell)
図 20に示すように、第 1半導体チップ 1-01の IOセル領域に、直接外部パッケージ 端とワイヤで接続しな!/、IOセル 20-02が存在し、この IOセル 20-02が存在することで 第 1半導体チップ 1-01の一辺の長さ L1をそれ以上縮めることができない場合におい て、第 2半導体チップ 1-02の一辺に IOセルのない空き領域が存在する場合、図 21 に示すように、前記 IOセル 20-02を第 2半導体チップ 1-02の領域の IOセルとしてその 構成を移す。これにより、第 1半導体チップ 1-01から IOセル 20-02を削減でき、その 結果、第 1半導体チップ 1-01の一辺を縮めることができ (L1→L2)、第 1半導体チップ 1-01の面積削減が可能となる。  As shown in Fig. 20, there is an IO cell 20-02 in the IO cell area of the first semiconductor chip 1-01, not directly connected to the end of the external package! /, This IO cell 20-02 exists Thus, when the length L1 of one side of the first semiconductor chip 1-01 cannot be further reduced, and there is an empty area without IO cells on one side of the second semiconductor chip 1-02, FIG. As shown in FIG. 2, the configuration of the IO cell 20-02 is moved as an IO cell in the region of the second semiconductor chip 1-02. As a result, the IO cell 20-02 can be reduced from the first semiconductor chip 1-01, and as a result, one side of the first semiconductor chip 1-01 can be shortened (L1 → L2). The area can be reduced.
[0049] なお、前記 IOセル 20-02の内部構造はここでは問題としない。一例としては図 20, 21に挙げているように内部に電源間保護回路 20-03を持った IOセルが挙げられる。  Note that the internal structure of the IO cell 20-02 is not a problem here. An example is an IO cell with an inter-power protection circuit 20-03 as shown in Figs.
[0050] 上記機能 9,10の説明においては、第 2半導体チップ 1-02の IOセル領域に第 1半 導体チップ 1-01の保護回路構成を移した力 その際、第 2半導体チップ 1-02の IOセ ル領域にはすでに IOセルを追加で配置するスペースがなく内部領域に空きがある 場合には、図 22に示すように、第 2半導体チップ 1-02の内部領域に保護回路 20_02( 19-04)を配置する。 [0050] In the description of the functions 9 and 10, the force that moves the protection circuit configuration of the first semiconductor chip 1-01 to the IO cell region of the second semiconductor chip 1-02. If the IO cell area of 02 already has no space to place additional IO cells and there is space in the internal area, as shown in Fig. 22, the protection circuit 20_02 in the internal area of the second semiconductor chip 1-02 Place (19-04).
[0051] また、第 1半導体チップ 1-01から第 2半導体チップ 1-02へと構成を移した保護回路 等において、同じ用途、構成で用いられている回路がすでに第 2半導体チップ 1-02 にある場合は、共有化することで、上述の構成を移した回路 (20-02や 19-04)はそのま ま削減可能となり、第 2半導体チップ 1-02の面積削減が可能となる。  [0051] Further, in a protection circuit or the like whose configuration has been changed from the first semiconductor chip 1-01 to the second semiconductor chip 1-02, a circuit used for the same application and configuration has already been used. In this case, by sharing the circuit, the circuits (20-02 and 19-04) to which the above configuration is transferred can be reduced as they are, and the area of the second semiconductor chip 1-02 can be reduced.
[0052] (機能 11 :ヒューズ素子） [0052] (Function 11: Fuse element)
図 23に示すように、第 1半導体チップ 1-01の回路 23-3を制御する電気的に切断可 能なヒューズ素子 (以下「電気ヒューズ」と示す) 23-4を、第 2半導体チップ 1-02の空き 領域に配置する。第 1半導体チップ 1-01と第 2半導体チップ 1-02は、回路 23-3の信 号入出力パッド 23-5と、電気ヒューズ 23-4の信号入出力パッド 23-6を、ワイヤ 23-7で 接続することにより、電気的に接続されている。このようにすることで、回路 23-3の電 気ヒューズ 23-4による制御機能を保持しつつ、第 1半導体チップ 1-01のチップサイズ 削減及び、第 2半導体チップ 1-02の空き領域の有効活用が実現可能となる。 As shown in FIG. 23, an electrically cuttable fuse element (hereinafter referred to as “electric fuse”) 23-4 for controlling the circuit 23-3 of the first semiconductor chip 1-01 is connected to the second semiconductor chip 1 Place in the -02 free space. The first semiconductor chip 1-01 and the second semiconductor chip 1-02 are connected to the signal input / output pad 23-5 of the circuit 23-3, the signal input / output pad 23-6 of the electric fuse 23-4, and the wire 23- By connecting at 7, it is electrically connected. In this way, the power of circuit 23-3 While maintaining the control function by the air fuse 23-4, it is possible to reduce the chip size of the first semiconductor chip 1-01 and to effectively use the empty area of the second semiconductor chip 1-02.
[0053] (機能 12 :ヒューズ素子）  [0053] (Function 12: Fuse element)
図 24のマルチチップ半導体装置において、電気ヒューズ 24-4は、第 1半導体チッ プ 1-01の内部電源電位調整回路 24-3の電源電位を制御するヒューズ素子であり、 第 2半導体チップ 1-02の空き領域に配置される。パッド 24-5とパッド 24-6は、ワイヤ 24 -7で電気的に接続されており、内部電源電位調整回路 24-3の制御信号は、パッド 24 -5、ワイヤ 24-7、パッド 24-6を介して、電気ヒューズ 24-4に入力されている。また、パッ ド 24-8とパッド 24-9は、ワイヤ 24-10で電気的に接続されており、電気ヒューズ 24-4の 出力信号は、パッド 24-9、ワイヤ 24-10、パッド 24-8を介して、内部電源電位調整回 路 24-3に制御信号として入力されている。このようにすることで、内部電源電位調整 回路 24-3の電源ヒューズ 24-4による電源電位調整機能を保持しつつ、第 1半導体チ ップ 1-01のチップサイズ削減及び、第 2半導体チップ 1-02の空き領域の有効活用が 実現可能となる。  In the multichip semiconductor device of FIG. 24, the electrical fuse 24-4 is a fuse element that controls the power supply potential of the internal power supply potential adjustment circuit 24-3 of the first semiconductor chip 1-01. The second semiconductor chip 1- Arranged in 02 free space. The pad 24-5 and the pad 24-6 are electrically connected by the wire 24-7, and the control signal of the internal power supply potential adjustment circuit 24-3 is the pad 24-5, the wire 24-7, the pad 24- 6 is input to the electrical fuse 24-4. Also, pad 24-8 and pad 24-9 are electrically connected by wire 24-10, and the output signal of electric fuse 24-4 is pad 24-9, wire 24-10, pad 24- 8 is input as a control signal to the internal power supply potential adjustment circuit 24-3. By doing so, while maintaining the power supply potential adjustment function by the power supply fuse 24-4 of the internal power supply potential adjustment circuit 24-3, the chip size of the first semiconductor chip 1-01 can be reduced and the second semiconductor chip can be reduced. Effective use of 1-02 free space becomes feasible.
[0054] (機能 13 :ヒューズ素子）  [0054] (Function 13: Fuse element)
図 25のマルチチップ半導体装置において、電気ヒューズ 25-5は、第 1半導体チッ プ 1-01の機能回路 25-3及び機能回路 25-4を選択制御するヒューズ素子であり、第 2 半導体チップ 1-02の空き領域に配置される。パッド 25-6とパッド 25-7は、ワイヤ 25-8 で電気的に接続されており、機能回路 25-3の出力信号または入力信号は、パッド 25 -6、ワイヤ 25-8、パッド 25-7を介して、電気ヒューズ 25-5へ入力または電気ヒューズ 25 -5から出力されている。またパッド 25-9とパッド 25-10は、ワイヤ 25-11で電気的に接 続されており、機能回路 25-4の出力信号または入力信号は、パッド 25-9、ワイヤ 25-1 1、パッド 25-10を介して、電気ヒューズ 25-5へ入力または電気ヒューズ 25-5から出力 されている。電気ヒューズ 25-5により機能回路 25-3と機能回路 25-4を選択制御でき、 第 1半導体チップ 1-01の機能を調整することが可能である。このようにすることで、第 1半導体チップ 1-01の機能調整機能を保持しつつ、第 1半導体チップ 1-01のチップ サイズ削減及び、第 2半導体チップ 1-02の空き領域の有効活用が実現可能となる。  In the multichip semiconductor device of FIG. 25, the electrical fuse 25-5 is a fuse element that selectively controls the functional circuit 25-3 and the functional circuit 25-4 of the first semiconductor chip 1-01, and the second semiconductor chip 1 It is placed in the free space of -02. Pad 25-6 and pad 25-7 are electrically connected by wire 25-8, and the output signal or input signal of functional circuit 25-3 is pad 25-6, wire 25-8, pad 25- 7 is input to or output from the electrical fuse 25-5. Also, pad 25-9 and pad 25-10 are electrically connected by wire 25-11, and the output signal or input signal of functional circuit 25-4 is pad 25-9, wire 25-1 1, Input to or output from electrical fuse 25-5 via pad 25-10. The function circuit 25-3 and the function circuit 25-4 can be selected and controlled by the electric fuse 25-5, and the function of the first semiconductor chip 1-01 can be adjusted. In this way, while maintaining the function adjustment function of the first semiconductor chip 1-01, it is possible to reduce the chip size of the first semiconductor chip 1-01 and effectively use the free space of the second semiconductor chip 1-02. It becomes feasible.
[0055] (機能 14 :ヒューズ素子） 図 26のマルチチップ半導体装置において、電気ヒューズ 26-3は複数の出力を持 つ電気ヒューズ群であり、パッド群 26-4のプルアップ、プルダウンを制御するヒューズ 素子である。パッド群 26-4は、ワイヤ群 26-5により、リード端群 26-6と電気的に接続さ れている。電気ヒューズ 26-3でパッド端子群 26-4のプルアップ、プルダウンを制御す ることにより、ワイヤ群 26-5を介して、リード端 26-6から、第 1半導体チップ 1-01のチッ プ識別信号を出力する。このようにすることで、第 1半導体チップ 1-01のチップ識別 機能を保持しつつ、第 1半導体チップ 1-01のチップサイズ削減及び、第 2半導体チッ プ 1-02の空き領域の有効活用が可能となる。 [0055] (Function 14: Fuse element) In the multichip semiconductor device of FIG. 26, the electric fuse 26-3 is an electric fuse group having a plurality of outputs, and is a fuse element that controls pull-up and pull-down of the pad group 26-4. The pad group 26-4 is electrically connected to the lead end group 26-6 by a wire group 26-5. By controlling the pull-up and pull-down of the pad terminal group 26-4 with the electrical fuse 26-3, the chip of the first semiconductor chip 1-01 is connected from the lead end 26-6 via the wire group 26-5. An identification signal is output. In this way, while maintaining the chip identification function of the first semiconductor chip 1-01, the chip size of the first semiconductor chip 1-01 is reduced and the free space of the second semiconductor chip 1-02 is effectively utilized. Is possible.
[0056] (機能 15 :電源配線） [0056] (Function 15: Power supply wiring)
図 27のマルチチップ半導体装置において、第 2半導体チップ 1-02のパッド 27-06に は、リード端 27-11およびワイヤ 27-04を介して電源が供給される。パッド 27-06は、電 源配線 27-08により、第 2半導体チップ 1-02のパッド 27-05に接続されている。さらに 第 2半導体チップ 1-02のパッド 27-05と第 1半導体チップ 1-01のパッド 27-07をワイヤ 2 7-03を用いて接続し、電源配線 27-09をモジュール 27-10に接続することでモジユー ル 27-10に電源を供給する。このようにすることで、従来手法における第 1半導体チッ プ 1-01の電源配線領域を削減でき、第 1半導体チップ 1-01のチップサイズ削減が実 現可能となる。  In the multichip semiconductor device of FIG. 27, power is supplied to the pad 27-06 of the second semiconductor chip 1-02 via the lead end 27-11 and the wire 27-04. The pad 27-06 is connected to the pad 27-05 of the second semiconductor chip 1-02 by the power wiring 27-08. Furthermore, connect pad 27-05 of the second semiconductor chip 1-02 and pad 27-07 of the first semiconductor chip 1-01 using wire 2 7-03, and connect the power supply wiring 27-09 to module 27-10. To supply power to modules 27-10. In this way, the power wiring area of the first semiconductor chip 1-01 in the conventional method can be reduced, and the chip size of the first semiconductor chip 1-01 can be reduced.
[0057] なお、第 1半導体チップ 1-01よりも第 2半導体チップ 1-02のスライス費、マスク製作 費が低価である場合には、第 2半導体チップ 1-02で、電源配線用のマスクレイヤを 1 層以上追加し、この追加したマスクレイヤを電源配線 27-08として使用することで、ス ライス費、マスク製作費の削減、さらには第 1半導体チップ 1-01のチップサイズの削 減を実現することが可能である。また、 1層以上のマスクレイヤを追加しているため、 電源配線 27-08を多層化して配線することで、配線インピーダンスの降下が可能であ り、モジュール 27-10への電源供給時に最小限の電源電圧効果で、電源を供給する ことが実現可能となる。  [0057] When the slice cost and mask manufacturing cost of the second semiconductor chip 1-02 are lower than the first semiconductor chip 1-01, the second semiconductor chip 1-02 is used for power supply wiring. By adding one or more mask layers and using this added mask layer as power supply wiring 27-08, it is possible to reduce the slice cost and mask manufacturing cost, and further reduce the chip size of the first semiconductor chip 1-01. Reduction can be realized. In addition, since one or more mask layers are added, the wiring impedance can be lowered by wiring the power supply wiring 27-08 in multiple layers, which is minimal when supplying power to the module 27-10. Power supply can be realized by the power supply voltage effect.
[0058] (機能 16 :電源配線）  [0058] (Function 16: Power supply wiring)
図 28は、第 1半導体チップ 1-01と第 2半導体チップ 1-02が同電位で動作する場合 の電源接続方法を示したものである。第 2半導体チップ 1-02のパッド 28-05にリード端 28-12から供給された電源を、電源配線 28-08を用いて、第 2半導体チップ 1_02のパ ッド 28-06と接続する。電源配線 28-08は第 2半導体チップ 1-02内のモジュール 28-10 もしくは第 2半導体チップ 1-02内の半導体素子にも電源を供給しているものとする。 第 2半導体チップ 1-02のパッド 28-06と第 1半導体チップ 1-01のパッド 28-07をワイヤ 2 8-04で接続し、電源配線 28-09をモジュール 28-11に接続、もしくは第 1半導体チップ 1-01内の半導体素子に接続することで第 1半導体チップ 1-01へ電源を供給する。こ のように第 1半導体チップ 1-01と第 2半導体チップ 1-02の電源の共有化を実施するこ とで、第 1半導体チップ 1-01もしくは第 2半導体チップ 1-02の電源配線領域を削減で き、第 1半導体チップ 1-01もしくは第 2半導体チップ 1-02のチップサイズ削減が実現 可能となる。 FIG. 28 shows a power supply connection method when the first semiconductor chip 1-01 and the second semiconductor chip 1-02 operate at the same potential. Lead end on pad 28-05 of second semiconductor chip 1-02 The power supplied from 28-12 is connected to pad 28-06 of the second semiconductor chip 1_02 using power wiring 28-08. It is assumed that the power supply wiring 28-08 also supplies power to the module 28-10 in the second semiconductor chip 1-02 or the semiconductor element in the second semiconductor chip 1-02. Connect pad 28-06 on the second semiconductor chip 1-02 to pad 28-07 on the first semiconductor chip 1-01 with wire 2 8-04, and connect power supply wiring 28-09 to module 28-11 1 Power is supplied to the first semiconductor chip 1-01 by connecting to the semiconductor elements in the semiconductor chip 1-01. Thus, by sharing the power supply of the first semiconductor chip 1-01 and the second semiconductor chip 1-02, the power supply wiring area of the first semiconductor chip 1-01 or the second semiconductor chip 1-02 It is possible to reduce the chip size of the first semiconductor chip 1-01 or the second semiconductor chip 1-02.
[0059] (機能 17 :ダミーセル）  [0059] (Function 17: Dummy cell)
図 29は、上面に第 1半導体チップ 1-01、下面に第 2半導体チップ 1-02を配置した 積層型のマルチチップ半導体装置の例を示している。図 29に示すように、第 1半導 体チップ 1-01内部領域にダミーセル 29-03があった場合、これを第 1半導体チップ 1- 0はり製造コストが低い第 2半導体チップ 1-02の空き領域 29-04に移すことで無駄な 領域の削減やコスト削減を図ることが可能である。  FIG. 29 shows an example of a stacked multi-chip semiconductor device in which the first semiconductor chip 1-01 is disposed on the upper surface and the second semiconductor chip 1-02 is disposed on the lower surface. As shown in FIG. 29, when there is a dummy cell 29-03 in the inner region of the first semiconductor chip 1-01, this is used for the first semiconductor chip 1-0 and the second semiconductor chip 1-02 having a low manufacturing cost. By moving to free space 29-04, it is possible to reduce wasteful space and reduce costs.
[0060] (機能 18 :ダミーセル）  [0060] (Function 18: Dummy cell)
図 31のマルチチップ半導体装置において、第 1半導体チップ 1-01内の信号 31-03 はダミー用パッド 31-05に接続され、ダミー用パッド 31-05はワイヤ 31-09により第 2半 導体チップ 1-02のパッド 31-06に接続される。パッド 31-06とパッド 31-07は配線 31-04 により接続される。パッド 31-07はワイヤ 31-10により第 1半導体チップ 1-01のダミー用 パッド 31-08に接続される。上記構成により、信号 31-03の不具合修正を実施する際 に、配線 31-04を第 2半導体チップ 1-02に移したダミーセル 31-11を利用して論理修 正した信号をパッド 31-07と接続する構成に変更する事で、第 1半導体チップ 1-01の 修正が不要となる。このようにすることで、スライス費用、マスク製作費が低価である第 2半導体チップ 1-02で修正することができ、コスト削減に有効である。  In the multichip semiconductor device of FIG. 31, the signal 31-03 in the first semiconductor chip 1-01 is connected to the dummy pad 31-05, and the dummy pad 31-05 is connected to the second semiconductor chip by the wire 31-09. Connected to pad 31-06 of 1-02. Pad 31-06 and pad 31-07 are connected by wiring 31-04. The pad 31-07 is connected to the dummy pad 31-08 of the first semiconductor chip 1-01 by the wire 31-10. With the above configuration, when correcting the malfunction of signal 31-03, pad 31-07 is a signal whose logic has been corrected using dummy cell 31-11 in which wiring 31-04 is moved to second semiconductor chip 1-02. The first semiconductor chip 1-01 does not need to be modified by changing the configuration to connect to the first semiconductor chip 1-01. By doing so, it can be corrected with the second semiconductor chip 1-02, which has low cost for slicing and mask production, which is effective for cost reduction.
[0061] (機能 19 :ダミーセル）  [0061] (Function 19: Dummy cell)
図 31のマルチチップ半導体装置において、第 1半導体チップ 1-01内の信号 31-03 はパッド 31-05に接続され、パッド 31-05はワイヤ 31-08により第 2半導体チップ 1-02の ノ ッド 31-06に接続される。パッド 31-06とパッド 31-07は配線 31-04により接続される。 ノ ッド 31-07はワイヤ 31-09によりリード端 31-10に接続される。上記構成により、信号 3 1-03の修正を実施する際に、配線 31-04を第 2半導体チップ 1-02に移したダミーセル 31-11を利用して論理修正した信号をパッド 31-07と接続する構成に変更する事で、 第 1半導体チップ 1-01の修正が不要となる。このようにすることで、スライス費用、マス ク製作費が低価である第 2半導体チップ 1-02で修正することができ、コスト削減に有 効であり、同時に、第 1半導体チップ 1-01にダミー用パッドを一つ設けるだけで良い ため、チップサイズの削減が可能である。 In the multichip semiconductor device of FIG. 31, the signal 31-03 in the first semiconductor chip 1-01 Is connected to the pad 31-05, and the pad 31-05 is connected to the node 31-06 of the second semiconductor chip 1-02 by the wire 31-08. Pad 31-06 and pad 31-07 are connected by wiring 31-04. Node 31-07 is connected to lead end 31-10 by wire 31-09. With the above configuration, when the signal 3 1-03 is corrected, the signal whose logic is corrected using the dummy cell 31-11 in which the wiring 31-04 is moved to the second semiconductor chip 1-02 is used as the pad 31-07. By changing the connection configuration, the first semiconductor chip 1-01 need not be modified. In this way, the second semiconductor chip 1-02, which has a low slicing cost and mask manufacturing cost, can be corrected, which is effective for cost reduction. At the same time, the first semiconductor chip 1-01 Since it is only necessary to provide one dummy pad on the chip, the chip size can be reduced.
[0062] (機能 20 :ダミーセル）  [0062] (Function 20: Dummy cell)
図 32は、上面に第 1半導体チップ 1-01、下面に第 2半導体チップ 1-02を配置した 積層型のマルチチップ半導体装置の例を示している。第 1半導体チップ 1-01内の信 号 32-03はパッド 32-05とダミー用パッド 32-06とに接続され、パッド 32-05はワイヤ 32- 09によりリード端 32-12と接続される。パッド 32-06はワイヤ 32-10により第 2半導体チッ プ 1-02のパッド 32-07と接続される。パッド 32-07とパッド 32-08は配線 32-04により接 続される。上記構成により、信号 32-03の論理修正を実施する際に、配線 32-04を第 2 半導体チップ 1-02に移したダミーセル 32-14を介して論理修正した信号をパッド 32-0 8と接続する構成に変更し、パッド 32-08をワイヤ 32-11によりリード端 32-13と接続し、 ワイヤ 32-09を削除する事で、第 1半導体チップ 1-01の修正が不要となる。このように することで、従来手法では、スライス費用、マスク製作費が高価である第 1半導体チッ プ 1-01で修正する必要があった力 スライス費用、マスク製作費が低価である第 2半 導体チップ 1-02で修正することが可能となり、コスト削減に有効である。また、修正前 後をワイヤーボンディングオプションによる切り替えが可能となる。  FIG. 32 shows an example of a stacked multi-chip semiconductor device in which the first semiconductor chip 1-01 is disposed on the upper surface and the second semiconductor chip 1-02 is disposed on the lower surface. Signal 32-03 in the first semiconductor chip 1-01 is connected to pad 32-05 and dummy pad 32-06, and pad 32-05 is connected to lead end 32-12 by wire 32-09. . Pad 32-06 is connected to pad 32-07 of second semiconductor chip 1-02 by wire 32-10. Pads 32-07 and 32-08 are connected by wiring 32-04. With the above configuration, when the logic correction of the signal 32-03 is performed, the signal whose logic is corrected via the dummy cell 32-14 in which the wiring 32-04 is moved to the second semiconductor chip 1-02 is connected to the pads 32-0-8. By changing the configuration to connect, the pad 32-08 is connected to the lead end 32-13 by the wire 32-11, and the wire 32-09 is deleted, so that the first semiconductor chip 1-01 need not be modified. In this way, in the conventional method, the slice cost and the mask manufacturing cost are expensive. The force that had to be corrected with the first semiconductor chip 1-01 The slice cost and the mask manufacturing cost were low. It is possible to correct with semiconductor chip 1-02, which is effective for cost reduction. In addition, it is possible to switch between before and after modification using the wire bonding option.
[0063] (機能 21 :ダミーセル）  [0063] (Function 21: Dummy cell)
図 33は、上面に第 1半導体チップ 1-01、下面に第 2半導体チップ 1-02を配置した 積層型のマルチチップ半導体装置の例を示している。第 1半導体チップ 1-01内の信 号 33-03はパッド 33-05とダミー用パッド 33-06とに接続され、パッド 33-05はワイヤ 33- 09によりリード端 33-12と接続される。パッド 33-06はワイヤ 33-10により第 2半導体チッ プ 1-02のパッド 33-07と接続される。パッド 33-07とパッド 33-08は配線 33-04により接 続される。上記構成により、信号 33-03の論理修正を実施する際に、配線 33-04を第 2 半導体チップ 1-02に移したダミーセル 33-14を介して論理修正した信号をパッド 33-0 8と接続する構成に変更し、ワイヤ 33-09を削除し、パッド 33-08をワイヤ 33-11によりリ ード端 33-12と接続する事で、第 1半導体チップ 1-01の修正が不要となる。このように することで、従来手法では、スライス費用、マスク製作費が高価である第 1半導体チッ プ 1-01で修正する必要があった力 スライス費用、マスク製作費が低価である第 2半 導体チップ 1-02で修正することが可能となり、コスト削減に有効であるとともに、第 1半 導体チップ 1-01と第 2半導体チップ 1-02のリード端を共有化する事が可能となり、パ ッケージ端子数削減が可能となる。 FIG. 33 shows an example of a stacked multi-chip semiconductor device in which the first semiconductor chip 1-01 is disposed on the upper surface and the second semiconductor chip 1-02 is disposed on the lower surface. Signal 33-03 in first semiconductor chip 1-01 is connected to pad 33-05 and dummy pad 33-06, and pad 33-05 is connected to lead end 33-12 by wire 33-09. . Pad 33-06 is connected to the second semiconductor chip by wire 33-10. Connected to pad 33-07 of plug 1-02. Pad 33-07 and pad 33-08 are connected by wiring 33-04. With the above configuration, when the logic of the signal 33-03 is corrected, the signal whose logic is corrected via the dummy cell 33-14 in which the wiring 33-04 is moved to the second semiconductor chip 1-02 is connected to the pads 33-0 8 By changing to the configuration to be connected, wire 33-09 is deleted, and pad 33-08 is connected to lead end 33-12 by wire 33-11, so that it is not necessary to modify the first semiconductor chip 1-01 Become. In this way, in the conventional method, the slice cost and the mask manufacturing cost are expensive. The force that had to be corrected with the first semiconductor chip 1-01 The slice cost and the mask manufacturing cost were low. The semiconductor chip 1-02 can be modified, which is effective for cost reduction, and the lead ends of the first semiconductor chip 1-01 and the second semiconductor chip 1-02 can be shared. The number of package terminals can be reduced.
[0064] (機能 22 :ダミーセル）  [0064] (Function 22: Dummy cell)
図 34は、上面に第 1半導体チップ 1-01、下面に第 2半導体チップ 1-02を配置した 積層型のマルチチップ半導体装置の例を示している。第 1半導体チップ 1-01内の信 号 34-03はパッド 34-05と接続され、パッド 34-05はワイヤ 34-08によりリード端 34-11と 接続される。第 2半導体チップ 1-02のパッド 34-06とパッド 34-07は配線 34-04により接 続される。上記構成で信号 34-03の論理修正を実施する際に、ワイヤ 34-08を削除し 、パッド 34-05とパッド 34-06をワイヤ 34-09で接続し、配線 34-04を第 1半導体チップ 1 -01から移したダミーセル 34-12を利用して論理修正した信号をパッド 34-07と接続す るよう変更し、パッド 34-07とリード端 34-11をワイヤ 34-10により接続する構成に変更 する。こうすることにより、スライス費用、マスク製作費が高価である第 1半導体チップ 1 -01を修正することなぐ論理修正が可能となり、コスト削減に有効であるとともに、第 1 半導体チップ 1-01にダミー用パッドが不要となり端子数削減が可能であるとともに、 第 1半導体チップ 1-01と第 2半導体チップ 1-02のリード端を共有化する事が可能とな り、パッケージ端子数削減が可能となる。  FIG. 34 shows an example of a stacked multi-chip semiconductor device in which the first semiconductor chip 1-01 is disposed on the upper surface and the second semiconductor chip 1-02 is disposed on the lower surface. The signal 34-03 in the first semiconductor chip 1-01 is connected to the pad 34-05, and the pad 34-05 is connected to the lead end 34-11 by the wire 34-08. The pad 34-06 and the pad 34-07 of the second semiconductor chip 1-02 are connected by the wiring 34-04. When performing logic correction of signal 34-03 with the above configuration, wire 34-08 is deleted, pad 34-05 and pad 34-06 are connected by wire 34-09, and wiring 34-04 is the first semiconductor Change the logic corrected signal using dummy cell 34-12 transferred from chip 1-01 to connect to pad 34-07, and connect pad 34-07 and lead end 34-11 with wire 34-10 Change to configuration. This makes it possible to modify the logic without modifying the first semiconductor chip 1-01, which has a high slicing cost and mask manufacturing cost, which is effective for cost reduction, and is provided with a dummy on the first semiconductor chip 1-01. The number of terminals can be reduced, and the lead ends of the first semiconductor chip 1-01 and the second semiconductor chip 1-02 can be shared, and the number of package terminals can be reduced. Become.
[0065] (機能 23：遅延調整用回路）  [0065] (Function 23: Delay adjustment circuit)
図 35のマルチチップ半導体装置において、第 1半導体チップ 1-01と第 2半導体チ ップ 1-02の接続方法は以下の通りである。第 1半導体チップ 1-01のパッド 35-03から 出力された信号をワイヤ 35-08を用いてパッド 35-04と接続し、その信号は遅延調整 回路 35-07に入力され、遅延調整後の信号はパッド 35-05と接続し、パッド 35_05から 出力した信号は、ワイヤ 35-09を用いてパッド 35-06と接続し、第 1半導体チップ 1-01 へ信号を戻す。 In the multichip semiconductor device of FIG. 35, the connection method of the first semiconductor chip 1-01 and the second semiconductor chip 1-02 is as follows. The signal output from pad 35-03 of the first semiconductor chip 1-01 is connected to pad 35-04 using wire 35-08, and the signal is delayed. The signal input to circuit 35-07 and adjusted for delay is connected to pad 35-05, and the signal output from pad 35_05 is connected to pad 35-06 using wire 35-09. Return the signal to -01.
[0066] 図 36は、図 35に示す遅延調整回路 35-07の詳細を示すものである。遅延調整の 手法としては、遅延セル 36-01〜遅延セル 36-05の出力と接続する出力信号配線 36- 06の接続箇所を変更し、遅延量を調整する仕組みとして!/、る。  FIG. 36 shows details of the delay adjustment circuit 35-07 shown in FIG. As a method for adjusting the delay, the connection position of the output signal wiring 36-06 connected to the output of the delay cell 36-01 to the delay cell 36-05 is changed to adjust the amount of delay!
[0067] 図 36で示すような遅延量を調整可能な回路 35-07を、図 35で示す第 1半導体チッ プ 1-01から第 2半導体チップ 1-02へ移し、第 1半導体チップ 1-01の面積削減を実現 可能とする。このようにすることで、従来手法では、スライス費用、マスク製作費が高価 である第 1半導体チップ 1-01で修正する必要があった力 スライス費用、マスク製作 費が低価である第 2半導体チップ 1-02で修正することができ、コスト削減に有効であ り、同時に、第 1半導体チップ 1-01のチップサイズの削減が実現可能である。  [0067] The circuit 35-07 capable of adjusting the delay amount as shown in FIG. 36 is transferred from the first semiconductor chip 1-01 shown in FIG. 35 to the second semiconductor chip 1-02, and the first semiconductor chip 1- It is possible to reduce the area of 01. In this way, in the conventional method, the power required to be corrected by the first semiconductor chip 1-01, which is expensive in slicing cost and mask manufacturing cost. The second semiconductor whose slicing cost and mask manufacturing cost is low. This can be corrected with chip 1-02, which is effective for cost reduction. At the same time, it is possible to reduce the chip size of the first semiconductor chip 1-01.
[0068] (機能 24：遅延調整用回路）  [0068] (Function 24: Delay adjustment circuit)
図 37のマルチチップ半導体装置において、第 1半導体チップ 1-01から出力された 信号は第 1半導体チップ 1-01のパッド 37-03からワイヤ 37-10を用いて第 2半導体チッ プ 1-02のパッド 37-04へ接続され、パッド 37-04から遅延調整回路 37-09へ接続される 。遅延調整回路 37-09から出力される信号は、遅延セルの出力箇所を選択することに よって、遅延量を調整することができ、各遅延セルの出力は第 2半導体チップ 1-02の パッド 37-05〜37_08に接続されている。遅延量の選択手法としては、ワイヤ 37_11〜 ワイヤ 37-14のワイヤボンディングの有無によって選択することができる。このようにす ることで、チップ内部を修正することなぐ遅延量を調整することができ、コスト削減が 実現可能となる。  In the multi-chip semiconductor device of FIG. 37, the signal output from the first semiconductor chip 1-01 is sent to the second semiconductor chip 1-02 using the wire 37-10 from the pad 37-03 of the first semiconductor chip 1-01. To pad 37-04, and pad 37-04 to delay adjustment circuit 37-09. The signal output from the delay adjustment circuit 37-09 can adjust the delay amount by selecting the output location of the delay cell, and the output of each delay cell is the pad 37 of the second semiconductor chip 1-02. -05 to 37_08 are connected. The selection method of the delay amount can be selected according to the presence / absence of wire bonding of the wires 37_11 to 37-14. In this way, the amount of delay without modifying the inside of the chip can be adjusted, and cost reduction can be realized.
[0069] (機能 25：遅延調整用回路）  [0069] (Function 25: Delay adjustment circuit)
図 38のマルチチップ半導体装置において、第 1半導体チップ 1-01から出力された 信号は第 1半導体チップ 1-01のパッド 38-03からワイヤ 38-06を用いて第 2半導体チッ プ 1-02のパッド 38-04へ接続され、パッド 38-04から遅延調整回路 38-05へ接続される 。遅延調整回路 38-05から出力される信号は、遅延セルの出力箇所を選択することに よって、遅延量を調整することができ、各遅延セルの出力はマルチプレクサ 38-08に 接続されている。遅延量の選択手法としては、マルチプレクサ選択信号 38-09をマル チプレクサ 38-08に入力することにより遅延セルの出力箇所を選択し、遅延量を調整 する。また、マルチプレクサ 38-08の選択信号 38-09の変更方法としては、上記機能 4 (図 7)や機能 6 (図 9)に示した方式により可能であるものとする。このようにすることで 、遅延量の調整が必要な場合に、最小限のマスクレイヤで修正が可能となり、コスト 削減が実現可能となる。 In the multichip semiconductor device of FIG. 38, the signal output from the first semiconductor chip 1-01 is sent to the second semiconductor chip 1-02 using the wire 38-06 from the pad 38-03 of the first semiconductor chip 1-01. To pad 38-04, and pad 38-04 to delay adjustment circuit 38-05. The amount of delay of the signal output from the delay adjustment circuit 38-05 can be adjusted by selecting the output location of the delay cell, and the output of each delay cell is sent to the multiplexer 38-08. It is connected. As a method for selecting the delay amount, the multiplexer selection signal 38-09 is input to the multiplexer 38-08, the output location of the delay cell is selected, and the delay amount is adjusted. In addition, as a method of changing the selection signal 38-09 of the multiplexer 38-08, it is possible to use the method shown in the function 4 (FIG. 7) and the function 6 (FIG. 9). In this way, when the delay amount needs to be adjusted, the correction can be made with the minimum mask layer, and the cost can be reduced.
[0070] (機能 26 :予備回路） [0070] (Function 26: Reserve circuit)
図 39は、上面に第 1半導体チップ 1-01、下面に第 2半導体チップ 1-02を配置した 積層型のマルチチップ半導体装置の例を示している。第 1半導体チップ 1-01内の回 路 39-03から出力された信号はパッド 39-05とパッド 39-06とに接続され、パッド 39-05 はワイヤ 39-09によりリード端 39-12と接続され、パッド 39-06はワイヤ 39-10により、第 2 半導体チップ 1-02のパッド 39-07と接続される。第 2半導体チップ 1-02内には、第 1半 導体チップ 1-01内の回路 39-03の予備回路 39-04を実装させておき、パッド 39-07は その予備回路 39-04と接続され、予備回路 39-04からの出力はパッド 39-08と接続され る。パッド 39-08はワイヤ 39-11により、リード端 39-13と接続される。このような構成によ り、リード端 39-12とリード端 39-13とをワイヤボンディングで切り替えるだけで、予備回 路 39-04への切り替えが可能となり、かつ第 2半導体チップ 1-02の空き領域を有効活 用する事で、チップサイズ削減が可能となる。また、修正にマスク製作費が不要となり コスト削減が可能である。予備回路 39-04の利用方法の一例として、同様の機能を持 つ異なる構成の回路を保険用回路として実装する場合や、異なる仕様の回路を実装 する事で、仕様変更を実現する場合等が考えられる。  FIG. 39 shows an example of a stacked multi-chip semiconductor device in which the first semiconductor chip 1-01 is disposed on the upper surface and the second semiconductor chip 1-02 is disposed on the lower surface. The signal output from the circuit 39-03 in the first semiconductor chip 1-01 is connected to the pad 39-05 and the pad 39-06, and the pad 39-05 is connected to the lead end 39-12 by the wire 39-09. The pad 39-06 is connected to the pad 39-07 of the second semiconductor chip 1-02 by the wire 39-10. The spare circuit 39-04 of the circuit 39-03 in the first semiconductor chip 1-01 is mounted in the second semiconductor chip 1-02, and the pad 39-07 is connected to the spare circuit 39-04. The output from the spare circuit 39-04 is connected to the pad 39-08. The pad 39-08 is connected to the lead end 39-13 by a wire 39-11. With such a configuration, it is possible to switch to the spare circuit 39-04 by simply switching the lead end 39-12 and the lead end 39-13 by wire bonding, and the second semiconductor chip 1-02 Chip size can be reduced by making effective use of free space. In addition, the mask manufacturing cost is not required for the correction, and the cost can be reduced. As an example of how to use the spare circuit 39-04, there are cases where a circuit with a different function and a different configuration is implemented as an insurance circuit, or when a specification change is realized by implementing a circuit with a different specification. Conceivable.
[0071] (機能 27 :テスト回路）  [0071] (Function 27: Test circuit)
図 40は、上面に第 1半導体チップ 1-01、下面に第 2半導体チップ 1-02を配置した 積層型のマルチチップ半導体装置の例を示している。第 1半導体チップ 1-01に比べ て第 2半導体チップ 1-02の製造コストが安いとする。図 40(a)において第 1半導体チッ プ 1-01の内部領域にあるテスト回路 40-03を、図 40(b)に示すように第 2半導体チップ 1-02に移すことで容易に製造コストを削減することが可能である。  FIG. 40 shows an example of a stacked multi-chip semiconductor device in which the first semiconductor chip 1-01 is disposed on the upper surface and the second semiconductor chip 1-02 is disposed on the lower surface. It is assumed that the manufacturing cost of the second semiconductor chip 1-02 is lower than that of the first semiconductor chip 1-01. In Fig. 40 (a), the test circuit 40-03 in the internal region of the first semiconductor chip 1-01 can be easily transferred to the second semiconductor chip 1-02 as shown in Fig. 40 (b). Can be reduced.
[0072] (機能 28 : BIST回路） 図 41は、上面に第 1半導体チップ 1-01、下面に第 2半導体チップ 1-02を配置した 積層型のマルチチップ半導体装置の例を示している。第 1半導体チップ 1-01に比べ て第 2半導体チップ 1-02の製造コストが安いとする。図 41(a)において第 1半導体チッ プ 1-01の内部領域にある BIST回路 41-03(テストパターン発生機能と判定機能を有 する)の一部もしくは全てを、図 41(b)に示すように第 2半導体チップ 1-02に移すことで 容易に製造コストを削減することが可能である。 [0072] (Function 28: BIST circuit) FIG. 41 shows an example of a stacked multi-chip semiconductor device in which a first semiconductor chip 1-01 is disposed on the upper surface and a second semiconductor chip 1-02 is disposed on the lower surface. It is assumed that the manufacturing cost of the second semiconductor chip 1-02 is lower than that of the first semiconductor chip 1-01. Fig. 41 (b) shows part or all of the BIST circuit 41-03 (having a test pattern generation function and a judgment function) in the internal region of the first semiconductor chip 1-01 in Fig. 41 (a) Thus, the manufacturing cost can be easily reduced by moving to the second semiconductor chip 1-02.
[0073] (機能 29 :バウンダリスキャン用回路） [0073] (Function 29: Boundary scan circuit)
図 42は、上面に第 1半導体チップ 1-01、下面に第 2半導体チップ 1-02を配置した 積層型のマルチチップ半導体装置の例を示している。第 1半導体チップ 1-01に比べ て第 2半導体チップ 1-02の製造コストが安いとする。図 42(a)において第 1半導体チッ プ 1-01の内部領域にあるバウンダリスキャン用回路 42-03の一部もしくは全てを、図 4 2(b)に示すように第 2半導体チップ 1-02に移すことで容易に製造コストを削減するこ とが可能である。  FIG. 42 shows an example of a stacked multi-chip semiconductor device in which the first semiconductor chip 1-01 is disposed on the upper surface and the second semiconductor chip 1-02 is disposed on the lower surface. It is assumed that the manufacturing cost of the second semiconductor chip 1-02 is lower than that of the first semiconductor chip 1-01. In FIG. 42 (a), a part or all of the boundary scan circuit 42-03 in the internal region of the first semiconductor chip 1-01 is replaced with the second semiconductor chip 1-02 as shown in FIG. 42 (b). This makes it possible to easily reduce manufacturing costs.
産業上の利用可能性  Industrial applicability
[0074] 本発明は、マルチチップ内の半導体チップのプロセスサイズが異なっていたり、チッ プ内部の空き領域のサイズが大きかったりする場合に特に有用である。 The present invention is particularly useful when the process sizes of the semiconductor chips in the multichip are different, or the size of the empty area inside the chip is large.

Claims

請求の範囲 The scope of the claims
[1] -ジ内に複数の半導体チップを有一 '型半導体装置であって 前記複数の半導体チップのうちの第 1半導体チップの機能を前記複数の半導体チ ップのうちの第 2半導体チップに移す、または、移した機能を前記第 1半導体チップと 前記第 2半導体チップとで共有化させる構成を有する、  [1] A semiconductor device having a plurality of semiconductor chips in a die and having a function of a first semiconductor chip of the plurality of semiconductor chips as a second semiconductor chip of the plurality of semiconductor chips. Or having the transferred function shared by the first semiconductor chip and the second semiconductor chip,
ことを特徴とするマルチチップ型半導体装置。  A multi-chip type semiconductor device characterized by the above.
[2] 請求項 1において、 [2] In claim 1,
前記第 1半導体チップおよび前記第 2半導体チップの各々は、 1つまたは複数のチ ップを含む、  Each of the first semiconductor chip and the second semiconductor chip includes one or more chips.
ことを特徴  That features
[3] 請求項 1において、 [3] In claim 1,
前記第 2半導体：  Said second semiconductor:
外部ピンに接続する多数の IOセル、パッケージ組立てによる IOセル配置制約、ま たは、プローブ検査テスト時の針当てによる IOセル配置制約によって、 IOリツソク（IO セル配置領域でチップサイズが決定する）状態となり、チップ内部に空き領域を有す る、  Depending on the number of IO cells connected to external pins, IO cell placement restrictions due to package assembly, or IO cell placement restrictions due to needle contact during probe inspection tests, IO Ritsoku (chip size is determined in the IO cell placement area) And there is an empty area inside the chip.
ことを特徴  That features
[4] 請求項 1において、  [4] In claim 1,
前記第 2半導体：  Said second semiconductor:
拡散工程の歩留まり改善目的で、マスクレイヤの面積率確保のため、チップ内部 空き領域を有する、  For the purpose of improving the yield of the diffusion process, in order to secure the area ratio of the mask layer, it has a free area inside the chip
ことを特徴  That features
[5] 請求項 1において、 [5] In claim 1,
前記第 2半導体：  Said second semiconductor:
チップ内部のマクロセルの配置形状によって発生する空き領域を有する、 ことを特徴  It has a vacant area generated by the arrangement shape of the macro cell inside the chip.
[6] 請求項 1において、 前記第 2半導体チップは、 [6] In claim 1, The second semiconductor chip is
前記第 1半導体チップに比べ、製造プロセスサイズが大きい、もしくは、拡散レイヤ が少ない理由により、製造コストが安価である構成を有する、  Compared to the first semiconductor chip, the manufacturing process size is large, or the manufacturing cost is low due to the small number of diffusion layers.
ことを特徴とするマルチチップ型半導体装置。  A multi-chip type semiconductor device characterized by the above.
[7] 請求項 1において、 [7] In claim 1,
前記第 2半導体チップは、  The second semiconductor chip is
前記第 1半導体チップに比べ、フォトグラフィー寸法が大きぐマスク製作費用が安 価である構成を有する、  Compared to the first semiconductor chip, it has a configuration in which the mask manufacturing cost is large and the mask manufacturing cost is low.
ことを特徴とするマルチチップ型半導体装置。  A multi-chip type semiconductor device characterized by the above.
[8] 請求項 1において、 [8] In claim 1,
前記第 2半導体チップは、  The second semiconductor chip is
前記第 1半導体チップに比べ、製造プロセス (Vt調整）の違!/、及び基盤制御の有 無により、オフリーク電流の少ない構成を有する、  Compared to the first semiconductor chip, it has a structure with less off-leakage current due to the difference in manufacturing process (Vt adjustment)!
ことを特徴とするマルチチップ型半導体装置。  A multi-chip type semiconductor device characterized by the above.
[9] 請求項 1において、 [9] In claim 1,
前記第 2半導体チップは、  The second semiconductor chip is
前記第 1半導体チップに比べ、製造プロセスの違いにより、トランジスタの電流能力 ( スピード)の高いことによるタイミング収束性の高い構成を有する、  Compared to the first semiconductor chip, due to the difference in manufacturing process, it has a configuration with high timing convergence due to the high current capability (speed) of the transistor,
ことを特徴とするマルチチップ型半導体装置。  A multi-chip type semiconductor device characterized by the above.
[10] 請求項 1において、 [10] In claim 1,
前記第 2半導体チップは、  The second semiconductor chip is
前記第 1半導体チップに比べ、製造プロセスの違いにより、 Pchトランジスタと Nchトラ ンジスタの電流能力バラつきが少ないことによる Duty保証精度の高い構成を有する、 ことを特徴とするマルチチップ型半導体装置。  A multi-chip type semiconductor device characterized by having a structure with high duty guarantee accuracy due to less current capacity variation between the Pch transistor and the Nch transistor due to a difference in manufacturing process compared to the first semiconductor chip.
[11] 請求項 1において、 [11] In claim 1,
前記第 2半導体チップは、  The second semiconductor chip is
前記第 1半導体チップに比べ、製造プロセスの違いにより、配線インピーダンスが 小さ!/、(シート抵抗が小、線幅制約が大)構成を有する、 ことを特徴とするマルチチップ型半導体装置。 Compared to the first semiconductor chip, due to the difference in the manufacturing process, the wiring impedance is small! /, (The sheet resistance is small, the line width constraint is large), A multi-chip type semiconductor device characterized by the above.
[12] 請求項 1において、 [12] In claim 1,
前記第 1半導体チップに存在する容量素子を前記第 2半導体チップの空き領域に 移すことにより、前記第 1半導体チップの面積を削減し、前記第 2半導体チップの無 駄な空き領域を有効に活用する構成を有する、  The area of the first semiconductor chip is reduced by moving the capacitive element present in the first semiconductor chip to the empty area of the second semiconductor chip, and the unused empty area of the second semiconductor chip is effectively utilized. Having a configuration to
ことを特徴とするマルチチップ型半導体装置。  A multi-chip type semiconductor device characterized by the above.
[13] 請求項 1において、 [13] In claim 1,
前記第 2半導体チップの IOセル配置領域に空き領域がある場合に、前記第 1半導 体チップに存在する容量素子を前記第 2半導体チップの IOセル配置領域に移すこと により前記第 1半導体チップの面積を削減し、前記第 2半導体チップの無駄な空き領 域を有効に活用する構成を有する、  When there is a vacant area in the IO cell arrangement area of the second semiconductor chip, the capacitor element present in the first semiconductor chip is moved to the IO cell arrangement area of the second semiconductor chip to thereby move the first semiconductor chip. The area of the second semiconductor chip is effectively reduced, and the useless space of the second semiconductor chip is effectively utilized.
ことを特徴とするマルチチップ型半導体装置。  A multi-chip type semiconductor device characterized by the above.
[14] 請求項 1において、 [14] In claim 1,
前記第 1半導体チップと前記第 2半導体チップとのそれぞれに同電位の容量素子 が分割されて存在する場合に、前記第 1半導体チップに存在する容量素子を前記第 In the case where capacitive elements having the same potential are divided and exist in each of the first semiconductor chip and the second semiconductor chip, the capacitive element present in the first semiconductor chip is the first semiconductor chip.
2半導体チップに存在する容量素子と統合することにより、前記第 1半導体チップの 面積を削減し、前記第 2半導体チップの無駄な空き領域を有効に活用する構成を有 する、 (2) By integrating with the capacitive element existing in the semiconductor chip, the area of the first semiconductor chip is reduced, and a wasteful empty area of the second semiconductor chip is effectively used.
ことを特徴とするマルチチップ型半導体装置。  A multi-chip type semiconductor device characterized by the above.
[15] 請求項 1において、 [15] In claim 1,
前記第 2半導体チップに複数個の容量素子を形成し、切り替えオプションにより前 記第 2半導体チップの無駄な空き領域を有効に活用する構成を有するとともに安価 に容量素子の切り替え修正ができる構成を有する、  A plurality of capacitive elements are formed on the second semiconductor chip, and a configuration is employed in which a wasteful empty area of the second semiconductor chip is effectively used by a switching option, and switching of the capacitive elements can be corrected at low cost. ,
ことを特徴とするマルチチップ型半導体装置。  A multi-chip type semiconductor device characterized by the above.
[16] 請求項 1において、 [16] In claim 1,
前記第 2半導体チップに複数個の容量素子を形成し、半導体を形成する素子にお いて切り替え可能なオプションを形成することにより、前記第 2半導体チップの無駄な 空き領域を有効に活用する構成を有するとともに安価に容量素子の切り替え修正が できる構成を有する、 A configuration in which a plurality of capacitive elements are formed in the second semiconductor chip, and a switchable option is formed in the elements forming the semiconductor, thereby effectively utilizing a wasteful empty area of the second semiconductor chip. Capacitance element switching correction at low cost Having a possible configuration,
ことを特徴とするマルチチップ型半導体装置。  A multi-chip type semiconductor device characterized by the above.
[17] 請求項 1において、 [17] In claim 1,
前記第 2半導体チップに複数個の容量素子を形成し、ワイヤオプションにより前記 容量素子を切り替え可能な状態にしておくことにより、前記第 2半導体チップの無駄 な空き領域を有効に活用する構成を有するとともに、前記第 1半導体チップおよび前 記第 2半導体チップの修正を行うことなくワイヤ変更のみで前記容量素子の切り替え ができる構成を有する、  A plurality of capacitive elements are formed on the second semiconductor chip, and the capacitive elements are made in a switchable state by a wire option, thereby effectively utilizing a wasted empty area of the second semiconductor chip. And the capacitor element can be switched only by changing the wire without modifying the first semiconductor chip and the second semiconductor chip.
ことを特徴とするマルチチップ型半導体装置。  A multi-chip type semiconductor device characterized by the above.
[18] 請求項 1において、 [18] In claim 1,
前記第 2半導体チップに複数個の容量素子を形成し、前記第 2半導体チップの内 部回路で構成されたレジスタの設定により前記容量素子を切り替え可能な状態にし ておくことにより、前記第 2半導体チップの無駄な空き領域を有効に活用する構成を 有するとともに、前記第 1半導体チップおよび前記第 2半導体チップの修正を行うこと なく外部からの信号を入力することで動的に前記容量素子の切り替えができる構成 を有する、  A plurality of capacitive elements are formed on the second semiconductor chip, and the capacitive elements are made switchable by setting a register configured by an internal circuit of the second semiconductor chip. In addition to having a configuration that effectively uses a wasteful empty area of the chip, the capacitive element is dynamically switched by inputting an external signal without modifying the first semiconductor chip and the second semiconductor chip. Have a configuration that can
ことを特徴とするマルチチップ型半導体装置。  A multi-chip type semiconductor device characterized by the above.
[19] 請求項 1において、 [19] In claim 1,
前記第 1半導体チップに存在する抵抗素子もしくは前記半導体装置外部の抵抗素 子を前記第 2半導体チップの空き領域に移すことにより、前記第 1半導体チップの面 積を削減し前記第 2半導体チップの無駄な空き領域を有効に活用する、もしくは外付 け部品を削減する構成を有する、  The area of the first semiconductor chip is reduced by moving a resistance element existing in the first semiconductor chip or a resistance element outside the semiconductor device to an empty area of the second semiconductor chip, thereby reducing the area of the second semiconductor chip. It has a configuration that makes effective use of wasted empty space or reduces external parts.
ことを特徴とするマルチチップ型半導体装置。  A multi-chip type semiconductor device characterized by the above.
[20] 請求項 1において、 [20] In claim 1,
前記第 1半導体チップに存在するプルダウン抵抗素子を前記第 2半導体チップの 空き領域に移すことにより、前記第 1半導体チップの面積を削減し前記第 2半導体チ ップの無駄な空き領域を有効に活用する構成を有する、  By moving the pull-down resistor element existing in the first semiconductor chip to the empty area of the second semiconductor chip, the area of the first semiconductor chip is reduced, and the useless empty area of the second semiconductor chip is made effective. Having a configuration to utilize,
ことを特徴とするマルチチップ型半導体装置。 A multi-chip type semiconductor device characterized by the above.
[21] 請求項 20において、 [21] In claim 20,
電極パッドおよび複数のプルダウン抵抗を前記第 2半導体チップに設け、前記複数 のプルダウン抵抗から選択的にプルダウン抵抗を前記電極パッドに接続することによ り、前記プルダウン抵抗の抵抗値を選択可能にする構成を有する、  An electrode pad and a plurality of pull-down resistors are provided in the second semiconductor chip, and a pull-down resistor is selectively connected to the electrode pad from the plurality of pull-down resistors, thereby enabling selection of a resistance value of the pull-down resistor. Having a configuration,
ことを特徴とするマルチチップ型半導体装置。  A multi-chip type semiconductor device characterized by the above.
[22] 請求項 1において、 [22] In claim 1,
前記第 1半導体チップに存在するプルアップ抵抗素子を前記第 2半導体チップの 空き領域に移すことにより、前記第 1半導体チップの面積を削減し前記第 2半導体チ ップの無駄な空き領域を有効に活用する構成を有する、  By moving the pull-up resistor element present in the first semiconductor chip to an empty area of the second semiconductor chip, the area of the first semiconductor chip is reduced, and an unnecessary empty area of the second semiconductor chip is effectively used. Have a configuration to use
ことを特徴とするマルチチップ型半導体装置。  A multi-chip type semiconductor device characterized by the above.
[23] 請求項 22において、 [23] In claim 22,
電極パッドおよび複数のプルアップ抵抗を前記第 2半導体チップに設け、前記複数 のプルアップ抵抗から選択的にプルアップ抵抗を前記電極パッドに接続することによ り、前記プルアップ抵抗の抵抗値を選択可能にする構成を有する、  An electrode pad and a plurality of pull-up resistors are provided in the second semiconductor chip, and a pull-up resistor is selectively connected to the electrode pad from the plurality of pull-up resistors, thereby reducing the resistance value of the pull-up resistor. Having a configuration to allow selection;
ことを特徴とするマルチチップ型半導体装置。  A multi-chip type semiconductor device characterized by the above.
[24] 請求項 21において、 [24] In claim 21,
電極パッドと複数のプルアップ抵抗と複数のプルダウン抵抗素子とを前記第 2半導 体チップに設け、前記複数のプルアップ抵抗および前記複数のプルダウン抵抗を選 択的に前記電極パッドに接続することにより、前記プルダウン抵抗および前記ブルア ップ抵抗から所望の抵抗を選択可能にする構成を有する、  An electrode pad, a plurality of pull-up resistors, and a plurality of pull-down resistor elements are provided in the second semiconductor chip, and the plurality of pull-up resistors and the plurality of pull-down resistors are selectively connected to the electrode pads. Therefore, a desired resistance can be selected from the pull-down resistor and the bull-up resistor.
ことを特徴とするマルチチップ型半導体装置。  A multi-chip type semiconductor device characterized by the above.
[25] 請求項 1において、 [25] In claim 1,
前記第 1半導体チップもしくは前記第 2半導体チップ外部に存在するダンピング抵 抗素子を前記第 2半導体チップの空き領域に移すことにより、前記第 1半導体チップ の面積を削減し前記第 2半導体チップの無駄な空き領域を有効に活用する構成を有 する、  By moving a damping resistance element existing outside the first semiconductor chip or the second semiconductor chip to an empty area of the second semiconductor chip, the area of the first semiconductor chip is reduced and the second semiconductor chip is wasted. Have a configuration that makes effective use of free space,
ことを特徴とするマルチチップ型半導体装置。  A multi-chip type semiconductor device characterized by the above.
[26] 請求項 25において、 電極パッドおよび複数のダンピング抵抗を前記第 2半導体チップに設け、前記複数 のダンピング抵抗から選択的にダンピング抵抗を前記電極パッドに接続することによ り、前記ダンピング抵抗の抵抗値を選択可能にする構成を有する、 [26] In claim 25, An electrode pad and a plurality of damping resistors are provided in the second semiconductor chip, and a resistance value of the damping resistor can be selected by selectively connecting the damping resistor to the electrode pad from the plurality of damping resistors. Having a configuration,
ことを特徴とするマルチチップ型半導体装置。  A multi-chip type semiconductor device characterized by the above.
[27] 請求項 1において、 [27] In claim 1,
前記第 1半導体チップの IOセルに存在する静電耐圧及びラッチアップ耐圧の大き い保護回路を前記第 2半導体チップの空き領域に移すことにより、前記第 1半導体チ ップの面積を削減し、前記第 2半導体チップの無駄な空き領域を有効に活用する構 成を有する、  The area of the first semiconductor chip is reduced by moving a protection circuit having a large electrostatic withstand voltage and latch-up withstand voltage existing in the IO cell of the first semiconductor chip to an empty area of the second semiconductor chip, Having a configuration for effectively utilizing the wasted empty area of the second semiconductor chip;
ことを特徴とするマルチチップ型半導体装置。  A multi-chip type semiconductor device characterized by the above.
[28] 請求項 1において、  [28] In claim 1,
電源間の静電耐圧及びラッチアップ耐圧の大きい保護回路が前記第 1半導体チッ プの IOセル配置領域に存在し、前記第 1半導体チップの 1辺の長さの最小値の限界 を決める一要因となっている場合に、前記保護回路を前記第 2半導体チップの IOセ ル配置領域に移すことにより前記第 1半導体チップの 1辺の長さの最小値を削減し、 前記第 1半導体チップの面積をより一層削減し、前記第 2半導体チップの無駄な空き 領域を有効に活用する構成を有する、  A protection circuit with a large electrostatic withstand voltage between the power supplies and a latch-up withstand voltage exists in the IO cell placement area of the first semiconductor chip, and is one factor that determines the limit of the minimum value of the length of one side of the first semiconductor chip. In this case, the minimum value of the length of one side of the first semiconductor chip is reduced by moving the protection circuit to the IO cell arrangement region of the second semiconductor chip, and Having a configuration that further reduces the area and effectively utilizes the wasted empty area of the second semiconductor chip,
ことを特徴とするマルチチップ型半導体装置。  A multi-chip type semiconductor device characterized by the above.
[29] 請求項 1において、  [29] In claim 1,
電源間の静電耐圧及びラッチアップ耐圧の大きい保護回路が前記第 1半導体チッ プの IOセル配置領域に存在し、前記第 1半導体チップの 1辺の長さの最小値の限界 を決める一要因となっており、なおかつ前記第 2半導体チップもすでに IOセル配置 領域が埋まっている場合に、前記保護回路を前記第 2半導体チップの内部空き領域 に移すことで前記第 1半導体チップの 1辺の長さの最小値を削減し、前記第 1半導体 チップの面積をより一層削減し、前記第 2半導体チップの無駄な空き領域を有効に 活用する構成を有する、  A protection circuit with a large electrostatic withstand voltage between the power supplies and a latch-up withstand voltage exists in the IO cell placement area of the first semiconductor chip, and is one factor that determines the limit of the minimum value of the length of one side of the first semiconductor chip. In addition, when the second semiconductor chip is already filled with the IO cell arrangement area, the protection circuit is moved to the internal empty area of the second semiconductor chip to thereby reduce the size of one side of the first semiconductor chip. A configuration in which the minimum value of the length is reduced, the area of the first semiconductor chip is further reduced, and a wasteful empty area of the second semiconductor chip is effectively used;
ことを特徴とするマルチチップ型半導体装置。  A multi-chip type semiconductor device characterized by the above.
[30] 請求項 27、請求項 28、請求項 29のいずれか 1つにおいて、 前記第 1半導体チップより前記第 2半導体チップへ移した前記保護回路と同じ接続 構造を持つ保護回路が前記第 2半導体チップ内にある場合、前記第 2半導体チップ 内の保護回路で共有化する構成を有する、 [30] In any one of claim 27, claim 28, or claim 29, The protection circuit having the same connection structure as the protection circuit transferred from the first semiconductor chip to the second semiconductor chip is shared by the protection circuit in the second semiconductor chip when the protection circuit is in the second semiconductor chip. Having
ことを特徴とするマルチチップ型半導体装置。  A multi-chip type semiconductor device characterized by the above.
[31] 請求項 1において、 [31] In claim 1,
前記第 1半導体チップに存在する電気的に切断可能なヒューズ素子の一部もしく は全部を、前記第 2半導体チップの空き領域に移すことより、前記第 1半導体チップ の面積を削減し、前記第 2半導体チップの無駄な空き領域を有効に活用する構成を 有する、  The area of the first semiconductor chip is reduced by moving a part or all of the electrically disconnectable fuse elements present in the first semiconductor chip to an empty area of the second semiconductor chip, and It has a configuration that effectively uses the wasted empty area of the second semiconductor chip.
ことを特徴とするマルチチップ型半導体装置。  A multi-chip type semiconductor device characterized by the above.
[32] 請求項 31において、 [32] In claim 31,
前記第 1半導体チップは、  The first semiconductor chip is
ヒューズ素子を用いた、内部電源電位を調整する電位調整手段を備えており、 前記第 2半導体チップは、  The second semiconductor chip includes a potential adjusting means that adjusts an internal power supply potential using a fuse element.
前記第 1半導体チップの前記電位調整手段のための、電気的に切断可能なヒユー ズ素子を備えている、  An electrically disconnectable fuse element for the potential adjusting means of the first semiconductor chip;
ことを特徴とするマルチチップ型半導体装置。  A multi-chip type semiconductor device characterized by the above.
[33] 請求項 31において、 [33] In claim 31,
前記第 1半導体チップは、  The first semiconductor chip is
ヒューズ素子を用いた、機能調整手段を備えており、  It is equipped with function adjustment means using a fuse element.
前記第 2半導体チップは、  The second semiconductor chip is
前記第 1半導体チップの前記機能調整手段のための、電気的に切断可能なヒユー ズ素子を備えている、  An electrically disconnectable fuse element for the function adjusting means of the first semiconductor chip;
ことを特徴とするマルチチップ型半導体装置。  A multi-chip type semiconductor device characterized by the above.
[34] 請求項 31において、 [34] In claim 31,
前記第 1半導体チップは、  The first semiconductor chip is
ヒューズ素子を用いた、チップ判別機能を備えており、  It has a chip discrimination function using a fuse element.
前記第 2半導体チップは、 前記第 1半導体チップの前記チップ判別機能のための、電気的に切断可能なヒュ ーズ素子を備えている、 The second semiconductor chip is An electrically disconnectable fuse element for the chip discrimination function of the first semiconductor chip;
ことを特徴とするマルチチップ型半導体装置。  A multi-chip type semiconductor device characterized by the above.
[35] 請求項 1において、  [35] In claim 1,
前記第 2半導体チップは、  The second semiconductor chip is
前記第 1半導体チップの電圧降下低減のための電源配線を備えている、 ことを特徴とするマルチチップ型半導体装置。  A multi-chip type semiconductor device comprising a power supply wiring for reducing a voltage drop of the first semiconductor chip.
[36] 請求項 1において、 [36] In claim 1,
前記第 2半導体チップは、  The second semiconductor chip is
前記第 2半導体チップの内部素子に電源を供給しない、前記第 2半導体チップに 追加された 1層以上のマスクレイヤを使用した、 1層以上のレイヤで構成される第 1の 電源配線を備えており、  1st power supply wiring comprised of one or more layers using one or more mask layers added to the second semiconductor chip, which does not supply power to the internal elements of the second semiconductor chip And
前記第 2半導体チップの入出力パッドのうち外部からの電源供給を受ける入出力パ ッド（第 1のパッド）に前記第 1の電源配線を接続し、  The first power supply wiring is connected to an input / output pad (first pad) that receives an external power supply among the input / output pads of the second semiconductor chip,
前記第 1半導体チップの入出力パッドのうち、前記第 1半導体チップの内部素子に 電源を供給している第 2の電源配線に前記第 1半導体チップの外部から電源を供給 して!/、る入出力パッド（第 2のパッド）と、前記第 2半導体チップの入出力パッドのうち 前記第 1の電源配線に接続されておりかつ前記第 1のパッドとは異なる入出力パッド (第 3のパッド）とを、ワイヤを用いて接続する構成を有する、  Of the input / output pads of the first semiconductor chip, supply power from the outside of the first semiconductor chip to the second power supply wiring that supplies power to the internal elements of the first semiconductor chip. An input / output pad (second pad) and an input / output pad (third pad) connected to the first power supply line and different from the first pad among the input / output pads of the second semiconductor chip ) And a connection using a wire,
ことを特徴とするマルチチップ型半導体装置。  A multi-chip type semiconductor device characterized by the above.
[37] 請求項 1において、 [37] In claim 1,
前記第 2半導体チップは、  The second semiconductor chip is
前記第 2半導体チップの内部素子に電源を供給する第 1の電源配線を備えており 前記第 2の半導体チップの入出力パッドのうち、前記第 1の電源配線に前記第 2半 導体チップの外部から電源を供給してレ、る入出力パッドとは異なる入出力パッド（第 1 のパッド）に、前記第 1の電源配線が接続されており、  A first power supply wiring for supplying power to an internal element of the second semiconductor chip; and an input / output pad of the second semiconductor chip that is connected to the first power supply wiring outside the second semiconductor chip. The first power supply wiring is connected to an input / output pad (first pad) different from the input / output pad supplied with power from
前記第 1半導体チップの入出力パッドのうち、前記第 1半導体チップの内部素子に 電源を供給しておりかつ前記第 1の電源配線と同電位である第 2の電源配線に前記 第 1半導体チップの外部から電源を供給している入出力パッド（第 2のパッド）と、前 記第 1のパッドとを、ワイヤを用いて接続する構成を有する、 Of the input / output pads of the first semiconductor chip, the internal elements of the first semiconductor chip An input / output pad (second pad) that supplies power from the outside of the first semiconductor chip to a second power supply wiring that supplies power and has the same potential as the first power supply wiring; The first pad is connected to the first pad using a wire.
ことを特徴とするマルチチップ型半導体装置。  A multi-chip type semiconductor device characterized by the above.
[38] 請求項 1において、 [38] In claim 1,
前記第 1半導体チップに存在するダミーセルを前記第 2半導体チップに移す事によ つて、前記第 1半導体チップの面積を削減し、前記第 2半導体チップの無駄な領域を 有効活用する、  Transferring the dummy cells existing in the first semiconductor chip to the second semiconductor chip, thereby reducing the area of the first semiconductor chip and effectively utilizing the useless area of the second semiconductor chip;
ことを特徴とするマルチチップ型半導体装置。  A multi-chip type semiconductor device characterized by the above.
[39] 請求項 38において、 [39] In claim 38,
前記第 2半導体チップは、  The second semiconductor chip is
前記第 1半導体チップからの入力信号を前記ダミーセルにより論理変更し前記第 1 半導体チップに戻す、  Logically changing the input signal from the first semiconductor chip by the dummy cell and returning it to the first semiconductor chip;
ことを特徴とするマルチチップ型半導体装置。  A multi-chip type semiconductor device characterized by the above.
[40] 請求項 38において、 [40] In claim 38,
前記第 2半導体チップは、  The second semiconductor chip is
前記第 1半導体チップからの入力信号を前記ダミーセルにより論理変更し、前記第 2半導体チップの出力パッドを介し、前記半導体装置の外部と電気的に接続される、 ことを特徴とするマルチチップ型半導体装置。  A multi-chip type semiconductor, wherein an input signal from the first semiconductor chip is logically changed by the dummy cell, and is electrically connected to the outside of the semiconductor device via an output pad of the second semiconductor chip. apparatus.
[41] 請求項 38において、 [41] In claim 38,
前記第 1半導体チップは、  The first semiconductor chip is
前記第 1半導体チップの出力パッド 1を介して前記半導体装置の外部と電気的に 接続する経路 1と、  A path 1 electrically connected to the outside of the semiconductor device via the output pad 1 of the first semiconductor chip;
前記第 1半導体チップの出力パッド 2を介して前記第 2半導体チップの入力パッド 3 と接続する経路 2に分岐しており、  Branching to a path 2 connected to the input pad 3 of the second semiconductor chip via the output pad 2 of the first semiconductor chip,
前記第 2半導体チップは、  The second semiconductor chip is
前記入力パッド 3から入力した信号を前記ダミーセルにより論理変更し、前記第 2半 導体チップの出力パッド 4を介して、前記半導体装置の外部と電気的に接続しており 前記経路 1と前記経路 2を請求項 17の方式により選択可能な構成を有する、 ことを特徴とするマルチチップ型半導体装置。 The signal input from the input pad 3 is logically changed by the dummy cell and electrically connected to the outside of the semiconductor device via the output pad 4 of the second semiconductor chip. A multi-chip type semiconductor device having a configuration in which the path 1 and the path 2 can be selected by the method of claim 17.
[42] 請求項 41記載の半導体装置を積層チップ構造とし、 [42] The semiconductor device according to claim 41 has a multilayer chip structure,
前記第 1半導体チップの前記パッド 1と前記パッド 2と前記第 2半導体チップの前記 ノ ンド 3と前記パッド 4を同一辺の近接に配置することで、前記経路 1と前記経路 2を 請求項 17の方式により選択する際にパッケージのリード端を共有化することを可能と し、パッケージの端子数の削減を可能とした、  18. The path 1 and the path 2 are arranged by arranging the pad 1 and the pad 2 of the first semiconductor chip and the node 3 and the pad 4 of the second semiconductor chip in the vicinity of the same side. This makes it possible to share the lead end of the package when making a selection, and to reduce the number of package terminals.
ことを特徴とするマルチチップ型半導体装置。  A multi-chip type semiconductor device characterized by the above.
[43] 請求項 38記載の半導体装置を積層チップ構造とし、 [43] The semiconductor device according to claim 38 has a multilayer chip structure,
前記第 1半導体チップの前記パッド 1と前記パッド 2と前記第 2半導体チップの前記 ノ ンド 3と前記パッド 4を同一辺の近接に配置し、請求項 17の方式による選択を実施 することで前記第 1半導体チップの前記パッド 1と前記パッド 2を共有化することを可 能とし、前記第 1半導体チップのパッド数の削減を可能とした、  The pad 1 and the pad 2 of the first semiconductor chip, the node 3 and the pad 4 of the second semiconductor chip are arranged in the vicinity of the same side, and the selection according to the method of claim 17 is performed to perform the selection. The pad 1 and the pad 2 of the first semiconductor chip can be shared, and the number of pads of the first semiconductor chip can be reduced.
ことを特徴とするマルチチップ型半導体装置。  A multi-chip type semiconductor device characterized by the above.
[44] 請求項 1において、 [44] In claim 1,
前記第 1半導体チップに存在する遅延調整用のセルを前記第 2半導体チップに移 す事によって、前記第 1半導体チップの面積を削減し、前記第 2半導体チップの無駄 な領域を有効活用する、  Transferring the delay adjustment cells existing in the first semiconductor chip to the second semiconductor chip, thereby reducing the area of the first semiconductor chip and effectively utilizing a useless area of the second semiconductor chip;
ことを特徴とするマルチチップ型半導体装置。  A multi-chip type semiconductor device characterized by the above.
[45] 請求項 44において、 [45] In claim 44,
前記第 2半導体チップは、  The second semiconductor chip is
前記第 1半導体チップからの入力信号を、前記遅延調整用セルにて遅延値を調整 し、調整後の信号を前記第 1半導体チップに戻す、  The delay value of the input signal from the first semiconductor chip is adjusted by the delay adjustment cell, and the adjusted signal is returned to the first semiconductor chip.
ことを特徴とするマルチチップ型半導体装置。  A multi-chip type semiconductor device characterized by the above.
[46] 請求項 44において、 [46] In claim 44,
前記第 2半導体チップは、  The second semiconductor chip is
前記第 1半導体チップ力 の入力信号を、前記遅延調整用セルにて遅延値の異な る 2つ以上の信号に分岐し、それぞれが出力パッドを介して前記半導体装置の外部 と電気的に接続しており、請求項 17の方式により出力信号の遅延値を調整可能に構 成されている、 The input signal of the first semiconductor chip force is different in delay value in the delay adjustment cell. Branching into two or more signals, each of which is electrically connected to the outside of the semiconductor device via an output pad, and configured to be capable of adjusting the delay value of the output signal by the method of claim 17. Yes,
ことを特徴とするマルチチップ型半導体装置。  A multi-chip type semiconductor device characterized by the above.
[47] 請求項 44において、 [47] In claim 44,
前記第 2半導体チップは、  The second semiconductor chip is
前記第 1半導体チップからの入力信号を、前記第 2半導体チップに備えた遅延調 整用セルにて遅延値の異なる 2つ以上の信号に分岐し、それぞれの信号からマルチ プレクサにより一つを選択した後、前記半導体装置の外部と電気的に接続しており、 請求項 16または請求項 18に記載される方式によりマルチプレクサの選択信号を変 更可能に構成されている、  The input signal from the first semiconductor chip is branched into two or more signals having different delay values in the delay adjustment cell provided in the second semiconductor chip, and one is selected from each signal by the multiplexer. After that, it is electrically connected to the outside of the semiconductor device, and is configured so that the selection signal of the multiplexer can be changed by the method described in claim 16 or claim 18.
ことを特徴とするマルチチップ型半導体装置。  A multi-chip type semiconductor device characterized by the above.
[48] 請求項 1において、 [48] In claim 1,
前記第 1半導体チップに存在する回路の予備回路を、前記第 2半導体チップに 1 つ以上実装し、請求項 17の方式により前記予備回路との選択が可能なように構成さ れている、  At least one spare circuit of the circuit existing in the first semiconductor chip is mounted on the second semiconductor chip, and is configured to be selectable with the spare circuit by the method of claim 17.
ことを特徴とするマルチチップ型半導体装置。  A multi-chip type semiconductor device characterized by the above.
[49] 請求項 1において、 [49] In claim 1,
前記第 1半導体チップは、テスト回路を備えており、  The first semiconductor chip includes a test circuit,
前記第 2半導体チップは、前記第 1半導体チップの前記テスト回路の一部もしくは 全てを備えている、  The second semiconductor chip includes a part or all of the test circuit of the first semiconductor chip;
ことを特徴とするマルチチップ型半導体装置。  A multi-chip type semiconductor device characterized by the above.
[50] 請求項 1において、 [50] In claim 1,
前記第 1半導体チップは、  The first semiconductor chip is
検査対象回路および検査対象メモリを備えており、  It has a circuit to be inspected and a memory to be inspected.
前記第 2半導体チップは、  The second semiconductor chip is
前記第 1半導体チップの前記検査対象回路および前記検査対象メモリの検査用回 路の一部もしくは全てを備えている、 ことを特徴とするマルチチップ型半導体装置。 A part or all of the inspection target circuit of the first semiconductor chip and the inspection circuit of the inspection target memory; A multi-chip type semiconductor device characterized by the above.
[51] 請求項 49記載の半導体装置はバウンダリスキャン検査対象であって、 [51] The semiconductor device according to claim 49, which is a boundary scan inspection target,
前記第 1半導体チップのバウンダリスキャン用回路の一部もしくは全てを前記第 2半 導体チップに移す事によって、前記第 1半導体チップの面積を削減し、前記第 2半導 体チップの無駄な領域を有効活用する、  By transferring a part or all of the boundary scan circuit of the first semiconductor chip to the second semiconductor chip, the area of the first semiconductor chip is reduced, and a useless area of the second semiconductor chip is reduced. Make effective use,
ことを特徴とするマルチチップ型半導体装置。  A multi-chip type semiconductor device characterized by the above.
PCT/JP2007/063834 2006-09-01 2007-07-11 Multi-chip type semiconductor device WO2008026388A1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI752588B (en) * 2019-12-03 2022-01-11 日商鎧俠股份有限公司 semiconductor memory device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08167703A (en) * 1994-10-11 1996-06-25 Matsushita Electric Ind Co Ltd Semiconductor device, manufacture thereof, memory core chip and memory peripheral circuit chip
JPH0992781A (en) * 1995-09-22 1997-04-04 Internatl Business Mach Corp <Ibm> Multichip semiconductor structure with integrated circuit and its preparation

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08167703A (en) * 1994-10-11 1996-06-25 Matsushita Electric Ind Co Ltd Semiconductor device, manufacture thereof, memory core chip and memory peripheral circuit chip
JPH0992781A (en) * 1995-09-22 1997-04-04 Internatl Business Mach Corp <Ibm> Multichip semiconductor structure with integrated circuit and its preparation

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI752588B (en) * 2019-12-03 2022-01-11 日商鎧俠股份有限公司 semiconductor memory device

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