TWI469233B - 具有中空封裝件之封裝系統 - Google Patents
具有中空封裝件之封裝系統 Download PDFInfo
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- TWI469233B TWI469233B TW97120553A TW97120553A TWI469233B TW I469233 B TWI469233 B TW I469233B TW 97120553 A TW97120553 A TW 97120553A TW 97120553 A TW97120553 A TW 97120553A TW I469233 B TWI469233 B TW I469233B
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Description
本發明係大致關於積體電路的封裝,且詳言之,係關於一種用於封裝積體電路及微機電系統的系統。
在手機、數位記錄裝置、以及個人音訊播放器的高度整合領域中,微機電系統與積體電路扮演了重要的角色。這些微型裝置使功能整合實現極小的形狀因子。
通常是使用兩種以下公認有效的技術中之一種在矽晶圓上製成MEMS裝置:體型微加工(bulkmicro-machining)或面型微加工(surface micro-machining)。在這兩種方法中,MEMS裝置是使用標準的積體電路類型之製造設備在矽晶圓上製造。在晶圓製程之後,將晶圓切晶(dice)以形成個別的晶粒。這些MEMS晶粒可與電子元件(在CMOS上)整合或不整合。在晶粒切單(singulate)後,然後必須加以封裝成有某一形式的封裝件,其類似於IC封裝件。最後,將此封裝件插入插座或接合至印刷電路板(PCB)成為整體系統(例如,手機)的一部份。取決於MEMS樣式及應用(包含真空封裝件的要求),這些封裝件可以是相當精細。此外,由於許多MEMS裝置在操作期間需要移動,因此封裝件必須提供空腔(cavity)以允許移動。
此類MEMS封裝方法的問題之一是封裝件佔MEMS裝置總成本的極大比例,大約總成本的百分之30至70。因此,此封裝成本可對於MEMS裝置滲透成本敏感市場(例如,手
機市場)的能力有顯著影響。
現有MEMS封裝方法的另一個問題是與MEMS封裝件及系統其餘部份之電性連接有關的雜訊。與嵌入封裝件之MEMS裝置至電路之界面有關的接合、接線及電性互連必須增加阻抗失諧(impedance mismatch)以產生有雜訊或低的振幅訊號。
不過,很多證據顯示要是能夠解決封裝問題,對於新技術時機成熟的市場,MEMS技術可增加系統(例如,手機)的價值。再以手機為例,無庸置疑地,照相手機對市場的衝擊很大。人們在尋找下一個可擴大手機市場的附加機能。
MEMS可用於麥克風、射頻裝置(RF device)、影像擷取、識別、先進的顯示機能、個人健康及安全監視、以及運動擷取。阻止MEMS滲入手機市場的問題為成本與效能。如上述,封裝係佔MEMS裝置成本的百分之30至70。此項成本問題會阻止MEMS完全整合於所有的手機、顯示系統及許多其他類型的電子裝置。
MEMS裝置為半導體IC製程的邏輯衍生物,而半導體IC製程可用來開發微米尺度的結構裝置,例如轉換器(transducer)或致動器(actuator),而且彼等通常是在矽基板上製造。MEMS裝置通常與物理變數及電子訊號電路有界面。整合MEMS於尺度較大系統的製造很貴,因為有與整合MEMS標準IC技術(例如,CMOS)相關連的製程困難與成本。用於在玻璃上製造MEMS之製程的優點是容易實現電性及機械功能的整合。以此方式,系統層次的整合係有可能
且具成本效益。
因此,仍須要一種封裝系統,可促進具成本效益的整合並符合目標應用系統的電性要求。鑑於要在更小的封裝件中增加機能的需求很高,以致於找出這些問題的答案愈來愈緊要。鑑於持續在增加的商業競爭壓力、一直在成長的消費者預期、以及有意義產品差異在市場位置上的機會在減少,以致於找出這些問題的答案愈來愈緊要。另外,要求節省成本、改善效率及效能、以及滿足競爭壓力都會使解答這些問題的必要性有愈來愈高的緊迫性。
人們長期以來一直在找這些問題的解決方案,但是先前技術並沒有教導或建議任何解決方案,因此,這些問題的解決方案長期以來已困惑熟諳此藝者。
本發明提供一種封裝方法,係包含:形成終端引線(terminal lead);藉由用化合物連接該等終端引線來組構空腔;在該空腔中附接積體電路裝置、微機電系統、微機械系統、或彼等之組合;以及,接合蓋體至該等終端引線用於圍封該空腔。
除了以上提及的態樣以外,本發明還有一些具體實施例具有其他態樣或替代態樣。熟諳此藝者閱讀以下結合附圖的詳細說明將明白該等態樣。
以下的實施例會充分詳細地描述讓熟諳此藝者得以製作及使用本發明。應瞭解,基於本揭示內容,顯然還有其
他的實施例,而且在不脫離本發明的範疇下可進行製程或機械上的改變。
在以下的描述中,給出許多特定細節以供徹底瞭解本發明。不過,在沒有這些特定細節下,顯然仍可實施本發明。為了避免混淆本發明,有些習知電路、系統組態及製程步驟的細節將不予以詳述。同樣地,圖示系統實施例的附圖均為部份示意圖而且不按比例繪製,特別是有些尺寸是為了清楚呈現而在附圖中予以誇大。為了闡明和便於圖解說明、描述及理解,在揭示及描述具有一些共同特徵的多個具體實施例的地方,彼此相同及類似的特徵通常會用相同的元件符號表示。
就解釋上的目的而言,本文所用之術語“水平面”的定義是與晶粒平面或表面平行的平面,而不管它的方向。術語“垂直”係指與剛才定義之水平面垂直的方向。諸如“上方”、“下方”、“底面”、“頂面”、“側面”(如“側壁”)、“高於”、“低於”、“上部”、“上面”、以及“下面”之類的術語都是以水平面來定義。術語“在…上”是意指元件之間的直接接觸。本文所用之術語“系統”係指本發明方法與裝置,這要根據使用該術語的背景。本文所用之術語“製程”包含沖壓、鍛造、圖樣化、曝光、顯影、蝕刻、清洗、及/或材料的移除或雷射修整(trimming),如在形成所描述的結構時所需要的。
第1圖係根據本發明之一實施例圖示有中空封裝件之封裝系統100的橫截面圖。在有中空封裝件之封裝系統100
的橫截面圖中,導線架(lead frame)102的終端引線104係經彎曲成提供離開晶粒座(die pad)106之平面的垂直移位105。終端引線104的彎部可為提供垂直移位105的彎部或弧形物之任何組合。導線架102可用化合物108預封(pre-mold),例如液晶聚合物或環氧樹脂模造化合物。藉由填滿晶粒座106與終端引線104之間的所有空間以形成空腔110(例如,供未來組裝用的碗狀空間),化合物108可部份囊封(encapsulate)導線架102。
應瞭解,可形成沒有晶粒座106的空腔110。由化合物108之鄰接區製成的模造焊墊(molded pad)可足以製造供大部份應用使用的空腔110。
藉由黏晶(die attach)材料114可將晶粒112(例如,微機電系統(MEMS)、微機械系統、或積體電路裝置)貼在晶粒座106上。電性互連116(例如,接合線(bond wire))使晶粒112與終端引線104耦合。終端引線104的頂面與化合物108的任何中介區(intervening area)可塗上黏著劑118(例如,不導電黏著劑)。蓋體120可塗上黏著劑118,藉此蓋體圍封空腔110以及形成晶粒112的中空封裝件122
在有些應用中,在單元處於真空環境或充滿惰性氣體的環境時可施加蓋體120。當蓋體120塗上黏著劑118時,空腔110可變成內有真空或者氣體的密封空間。
第2圖為第1圖之中空封裝件122的底面平面圖。中空封裝件122的底面平面圖圖示在晶粒座106四周有多個形成陣列的終端引線104。在晶粒座106及終端引線104
陣列的四周係模造化合物108。可半蝕(half etch)繫桿(tie bar)202以防止晶粒座106與終端引線104無意中電性連接。晶粒座106可衝壓或蝕刻出方位標記204。在有些應用中,該方位標記可填滿包圍晶粒座106的化合物108。方位標記204可用來標示耦合至第1圖之晶粒112之第一針(pin one)之終端引線104的位置。
第3圖係根據本發明之替代實施例圖示有中空封裝件之封裝系統300的橫截面圖。封裝系統300的橫截面圖係圖示被化合物108部份包圍的終端引線104。化合物108的頂面可塗上黏著劑118以便施加蓋體120。這樣,可製成在終端引線104上設有小接觸區304的中空封裝件302。在有些應用中,對於有稠密互連要求的設計,此組態為在製造上更加可行的解決方案。
第4圖為第3圖之中空封裝件302的底部平面圖。中空封裝件302的底部平面圖圖示具有方位標記204及繫桿202的晶粒座106。繫桿202都被化合物108完全囊封。小接觸區304仍然露出化合物108而終端引線104的其餘部份被化合物108覆蓋使其不能電性連接。
第5圖根據本發明另一替代實施例圖示有中空封裝件之封裝系統500的橫截面圖。封裝系統500的橫截面圖係圖示導線架102具有藉由終端引線104之彎部而垂直偏離晶粒座106平面的終端引線104。導線架102可用化合物108預封,例如液晶聚合物或環氧樹脂模造化合物。化合物108可填滿所有在晶粒座106與終端引線104之間的空
間以形成空腔110,例如供未來組裝用的碗狀空間。
藉由黏晶材料114可將晶粒112(例如,MEMS、微機械系統、或積體電路裝置)貼在晶粒座106上。電性互連116(例如,接合線)使晶粒112與終端引線104耦合。可施加蓋體502(例如,自黏膠帶材料)使得該蓋體圍封空腔110並形成晶粒112的中空封裝件504。使用自黏膠帶材料來形成蓋體502以減少組裝製程中的製造步驟數。
第6圖係根據本發明另一替代實施例圖示有中空封裝件之封裝系統600的橫截面圖。封裝系統600的橫截面圖係圖示導線架102具有垂直偏離晶粒座106之平面的終端引線104。導線架102可用化合物108預封,例如液晶聚合物或環氧樹脂模造化合物。化合物108可填滿所有在晶粒座106與終端引線104之間的空間以形成空腔110,例如供未來組裝用的碗狀空間。化合物108也可在終端引線104上形成端蓋(end cap)602。在未來的組裝製程期間,端蓋602係用作間隔物。
藉由黏晶材料114可將晶粒112(例如,MEMS、微機械系統、或積體電路裝置)貼在晶粒座106上。電性互連116(例如,接合線)使晶粒112與終端引線104耦合。在終端引線104鄰近端蓋602的頂面上可塗上導電互連604(例如,焊料或導電環氧樹脂)。可施加導電層壓基板606(例如,印刷電路板、印刷線路板、軟板、或訊號改道發送媒介(signal re-routing medium)使得該蓋體圍封空腔110並形成晶粒112的中空封裝件608。下接觸墊610可藉由
導電互連604而與終端引線104電性連接。導電鏈結(link)612(例如,印刷電路板跡線)可使上接觸墊614與下接觸墊610連接。該上接觸墊可用來連接外部元件(未圖示),例如離散元件或額外的積體電路、微機械系統、或MEMS封裝件。
第7圖的橫截面圖係圖示有處於封裝件層疊(package on package)組態之中空封裝件的封裝系統700。封裝系統700的橫截面圖圖示有上接觸墊614的中空封裝件608係安裝另一封裝件702(例如,另一積體電路裝置、另一MEMS、另一微機械系統、中空封裝件608之另一單元、或彼等之組合於其上。導電互連604是在上接觸墊614上,而另一封裝件702是在導電互連604上。
第8圖的橫截面圖係圖示中空封裝件802配置成麥克風的封裝系統800。封裝系統800的橫截面圖圖示導線架102具有垂偏離晶粒座106之平面的終端引線104。導線架102可用化合物108預封,例如液晶聚合物或環氧樹脂模造化合物。化合物108可填滿所有在晶粒座106與終端引線104之間的空間以形成空腔110,例如供未來組裝用的碗狀空間。
藉由黏晶材料114可將晶粒112(例如,MEMS、微機械系統、或積體電路裝置)貼在晶粒座106上。電性互連116(例如,接合線)使晶粒112與終端引線104耦合。終端引線104的頂面與化合物108的任何中介區可塗上黏著劑118(例如,不導電黏著劑)。蓋體804可塗上黏著劑118,
藉此蓋體圍封空腔110並形成晶粒112的中空封裝件802。
蓋體804可具有聲波孔口(acoustic orifice)806用來激活晶粒112(例如,MEMS)以因應聲波能量來產生電性訊號。聲波孔口806引導聲波能量至晶粒112的適當位置以便轉換。在此範例中,聲波能量可進入空腔110,不過應瞭解,其他類型的能量或材料可進入用於產生電性訊號的空腔110。
第9圖的橫截面圖圖示封裝系統900有替代結構的中空封裝件,其係配置成麥克風。封裝系統900的橫截面圖圖示導線架902的終端引線104係經彎曲成提供離開下接觸平面904的垂直移位105。導線架902也可具有安裝墊906,其係具有垂偏離下接觸平面904的底側907,該安裝墊906有孔口908供聲波能量進入空腔110。可將化合物108在導線架902上模造成提供鄰接表面而只留下孔口908作為空腔110的入口。在此範例中,聲波能量可進入空腔110,不過應瞭解,其他類型的能量或材料可進入用於產生電性訊號的空腔110。
藉由黏晶材料114可將晶粒112(例如,微機電系統(MEMS)、微機械系統、或積體電路裝置)貼在安裝墊906上。電性互連116(例如,接合線)使晶粒112與終端引線104耦合。終端引線104的頂面與化合物108的任何中介區可塗上黏著劑118(例如,不導電黏著劑)。蓋體120可塗上黏著劑118,藉此蓋體圍封空腔110並形成晶粒112的中空封裝件910。
第10圖為有中空封裝件之封裝系統1000的橫截面圖,其中該中空封裝件910為另一替代配置成麥克風並裝在印刷電路板上。封裝系統1000的橫截面圖圖示中空封裝件910組構成在下接觸平面904中有安裝墊906與終端引線104。中空封裝件910可藉由導電互連604電性連接至在層壓基板1004(例如,印刷電路板)上的晶片座(chip pad)1002。層壓基板1004的開孔(opening)1006係與孔口908對齊。此組態係允許聲波能量進入空腔110供轉換成電性訊號。在此範例中,聲波能量可進入空腔110,不過應瞭解,其他類型的能量或材料可進入用於產生電性訊號的空腔110。
第11圖為有中空封裝件之封裝系統1100的底部平面圖,其中該中空封裝件1102為另一替代實施例。封裝系統1100的底部平面圖圖示中空封裝件1102具有在終端引線104之間的通氣口(vent)1104。此組態允許流體或氣體移動通過中空封裝件1102。此組態可用來具體實作包含流量計或壓力轉換器的裝置。通氣口1104是在模造製程(molding process)期間形成。化合物108可堵塞終端引線104之間的流動,從而產生通氣口1104。
第12圖的流程圖係圖示用於組裝封裝系統100的元件分段法(component staging)1200。元件分段法1200的流程圖係圖示第一元件階段1202,其中導線架102、黏晶材料114及晶粒112是在黏晶時期1204組合。第二元件階段1206增加導電互連604(例如,焊膏),以及任何可添加至
封裝件的被動元件。離散元件黏著時期1208可增加離散元件至導線架102。第三元件階段1210著重在電性互連116,例如,金接合線。焊線互連時期1212使用電性互連116來滿足封裝系統100的互連要求。
第四元件階段1214增加黏著劑118與蓋體120。蓋體黏著時期1216組裝蓋體120於導線架102上以形成中空封裝件122。引線修整時期1218可在導線架102的暴露區上進行電鍍製程,例如鍍焊料製程、鍍鈀鎳(NiPd)製程、或鍍金製程。在本發明之實施例中,鍍焊料製程用於引線修整為最具成本效益的解決方案而且可在模造製程之前進行。切單時期1220可使用鋸子(saw)或剪斷機(shear)將一片中空封裝件122分成數個單一單元。
第13圖為處於製造預備時期之導線架片體1300的橫截面圖。導線架片體1300的橫截面圖圖示一序列藉由終端引線104連結的導線架102。導線架102可整個用化合物108模造而形成實心的碗狀結構。
導線架片體1300顯示具有3個形成於片體的單元。這只是舉例說明,而應瞭解,任意數目的導線架102可連結成"X-Y"陣列。這表示導線架片體1300實際上可在直行有X個單元而在橫列有Y個單元,在此X與Y為整數。
第14圖為處於製造黏晶時期之預封型導線架片體1400的橫截面圖。預封型導線架片體1400的橫截面圖圖示黏晶材料114與晶粒112是位在導線架102的晶粒座106上。
預封型導線架片體1400顯示具有3個形成於片體的單元。這只是舉例說明,而應瞭解,任意數目的導線架102可連結成"X-Y"陣列。這表示預封型導線架片體1400實際上可在直行有X個單元而在橫列有Y個單元,在此X與Y為整數。
第15圖為處於製造線接合時期之預封型導線架片體1500的橫截面圖。預封型導線架片體1500的橫截面圖圖示造成晶粒112與終端引線104電性連接的電性互連116。
預封型導線架片體1500顯示具有3個形成於片體的單元。這只是舉例說明,而應瞭解,任意數目的導線架102可連結成"X-Y"陣列。這表示預封型導線架片體1500實際上可在直行有X個單元而在橫列有Y個單元,在此X與Y為整數。
第16圖為處於製造封蓋時期之封裝件片體1600的橫截面圖。封裝件片體1600的橫截面圖在產生空腔110的終端引線104與蓋體120之間塗上黏著劑118。
封裝件片體1600顯示具有3個形成於片體的單元。這只是舉例說明,而應瞭解,任意數目的導線架102可連結成"X-Y"陣列。這表示封裝件片體1600實際上可在直行有X個單元而在橫列有Y個單元,在此X與Y為整數。
第17圖為處於製造切單時期之中空封裝件122的橫截面圖。中空封裝件122的橫截面圖示在已用鋸斷或剪切製程切單後的一序列中空封裝件122。此範例僅顯示3個中空封裝件122,但應瞭解,中空封裝件122的實際數目可
能會不同。
第18圖為有中空封裝件之封裝系統1800的底部平面圖。封裝系統1800的底部平面圖圖示有半蝕繫桿1802的晶粒座106。繫桿1802係被化合物108部份囊封。小接觸區304仍然露出化合物108同時終端引線104的其餘部份被化合物108覆蓋使其不能與封裝件的外界電性連接。封裝系統1800也圖示穿過繫桿1802的第一剖面線19--19與穿過終端引線104的第二剖面線20-20。
第19圖為沿著第18圖之剖面線19-19繪出的封裝系統1900的橫截面圖。封裝系統1900的橫截面圖圖示晶粒座106的繫桿1802均經半蝕成允許化合物108部份囊封該等繫桿1802。被部份囊封的繫桿1802具有填滿彼等之四周空間的化合物108同時至少留下一表面1902不被覆蓋供電性連接用。
導電互連604(例如,焊料或導電環氧樹脂)形成該等繫桿1802與導電蓋體1904的電性連接。在此組態中,導電蓋體1904(例如,金屬蓋)可用作安裝在中空封裝件1906中之晶粒112的電性屏蔽。
第20圖為沿著第18圖之剖面線20-20繪出的封裝系統2000的橫截面圖。封裝系統2000的橫截面圖圖示中空封裝件302具有耦合晶粒112與晶粒座106的下結合電性互連(down bond electrical interconnect)2002。此技術常用來提供晶粒112的附加接地。
第21圖為第1圖中空封裝件122內之角落部份2100
的等角視圖。空腔110內之角落部份2100的等角視圖圖示被部份囊封化合物108的終端引線104。在部份囊封終端引線104、晶粒座106及繫桿202之間的空間時,下接觸2102沒有被化合物108覆蓋。表面1902也沒有被化合物108覆蓋。
在本發明之實施例中,終端引線104的頂面2104可被化合物108覆蓋。在蓋體120為金屬時,化合物108用作為終端引線104的絕緣體,而蓋體可與繫桿202電性連接。
第22圖係根據本發明之實施例圖示用於製造封裝系統100之封裝方法2200的流程圖。方法2200包含形成中空封裝件,包含:在方塊2202中,形成終端引線;在方塊2204中,藉由用化合物部份囊封該等終端引線來組構空腔;在方塊2206中,在該空腔中貼上積體電路裝置、微機電系統、微機械系統、或彼等之組合;以及在方塊2208中,接合蓋體至該等終端引線用於圍封該空腔。
本發明的主要態樣是允許使用習知的傳遞模塑製程(transfer molding process)來模造導線架。
另一態樣是本發明允許材料的平板可用作蓋體並簡化蓋體連接製程。本發明也適合大量生產並支援低成本製造。
本發明的另一重要態樣是有價值地支援及服務在降低成本、簡化系統及增加效能方面的歷史趨勢。
因此,本發明的以上及其他有價值的態樣促進技術的狀態至少到下一個等級。
因此,已發現,本發明的封裝系統提供先前技術未知、
不曾採用而有重要性的解決方案、性能及功能態樣供量產用。所得到的製程與組態都有明確性、成本效益、簡單不複雜、有高度通用性及有效性,而且藉由修改習知技術即可出人意外及不明顯地具體實作成立即可用、有效率又經濟地用於製造與習知製程及技術完全相容的微機電系統裝置。所得到的製程及組態都有明確性、成本效益、簡單不複雜、高度通用性、準確性、敏感性、及有效性,而且藉由修改習知元件即可具體實作成立即可用、有效率又經濟的製造方式、應用及利用。
儘管已結合特定的最佳模式來描述本發明,應瞭解,熟語此藝者在參閱前述說明後會明白仍有許多替代、修改及變體。因此,希望本發明能涵蓋所有這類落入隨附之申請專利範圍之範疇內的替代、修改及變體。所有迄今為止在本文及附圖中提及的內容都應被解釋成是要用來做圖解說明而沒有限定本發明的意思。
100、300、500、600、700、800、900、1000、1100、1800、1900、2000‧‧‧封裝系統
102、902‧‧‧導線架
104‧‧‧終端引線
105‧‧‧垂直移位
106‧‧‧晶粒座
108‧‧‧化合物
110‧‧‧空腔
112‧‧‧晶粒
114‧‧‧黏晶材料
116‧‧‧電性互連
118‧‧‧黏著劑
120、502、804‧‧‧蓋體
122、302、504、608、802、910、1102‧‧‧中空封裝件
202‧‧‧繫桿
204‧‧‧方位標記
304‧‧‧小接觸區
602‧‧‧端蓋
604‧‧‧導電互連
606‧‧‧導電層壓基板
610‧‧‧下接觸墊
612‧‧‧導電鏈接
614‧‧‧上接觸墊
702‧‧‧封裝件
806‧‧‧聲波孔口
904‧‧‧下接觸平面
906‧‧‧安裝墊
907‧‧‧底側
908‧‧‧孔口
1002‧‧‧晶片座
1004‧‧‧層壓基板
1006‧‧‧開孔
1104‧‧‧通氣口
1200‧‧‧元件分段法
1202‧‧‧第一元件階段
1204‧‧‧黏晶時期
1206‧‧‧第二元件階段
1208‧‧‧離散元件黏著時期
1210‧‧‧第三元件階段
1212‧‧‧焊線互連時期
1214‧‧‧第四元件階段
1216‧‧‧蓋體黏著時期
1218‧‧‧引線修整時期
1220‧‧‧切單時期
1300‧‧‧導線架片體
1400、1500‧‧‧預封型導線架片體
1600‧‧‧封裝件片體
1802‧‧‧繫桿
1902‧‧‧表面
1904‧‧‧導電蓋體
2002‧‧‧下結合電性互連
2100‧‧‧角落部份
2102‧‧‧下接觸
2104‧‧‧頂面
2200‧‧‧封裝方法
2202、2204、2206、2208‧‧‧流程方塊
19--19‧‧‧第一剖面線
20--20‧‧‧第二剖面線
第1圖係根據本發明之實施例圖示有中空封裝件的封裝系統的橫截面圖;第2圖為第1圖之中空封裝件的底面平面圖;第3圖係根據本發明之替代實施例圖示有中空封裝件的封裝系統的橫截面圖;第4圖為第3圖之中空封裝件的底部平面圖;第5圖係根據本發明另一替代實施例圖示有中空封裝件的封裝系統的橫截面圖;
第6圖係根據本發明另一替代實施例圖示有中空封裝件的封裝系統的橫截面圖;第7圖圖示有處於封裝件層疊組態(package on package configuration)之中空封裝件的封裝系統的橫截面圖;第8圖圖示有組構成麥克風之中空封裝件的封裝系統的橫截面圖;第9圖為有中空封裝件之封裝系統的橫截面圖,此替代中空封裝件係經組構成麥克風;第10圖為有中空封裝件之封裝系統的橫截面圖,此另一替代中空封裝件係經組構成麥克風且安裝在印刷電路板上;第11圖為有中空封裝件之封裝系統的底部平面圖,此中空封裝件為另一替代實施例;第12圖係圖示用於組裝有中空封裝件之封裝系統的元件分段法(component staging)的流程圖;第13圖為處於製造預備時期之導線架片體的橫截面圖;第14圖為處於製造黏晶時期之預封型導線架片體(pre-molded lead frame sheet)的橫截面圖;第15圖為處於製造線接合時期之預封型導線架片體的橫截面圖;第16圖為處於製造封蓋時期之封裝件片體的橫截面圖;
第17圖為處於製造切單時期(singulation phase)之中空封裝件的橫截面圖;第18圖為具有中空封裝件之封裝系統的底部平面圖;第19圖為沿著第18圖封裝系統之剖面線19--19繪出的橫截面圖;第20圖為沿著第18圖封裝系統之剖面線20--20繪出的橫截面圖;第21圖為第1圖空腔內之角落部份的等角視圖;以及第22圖係根據本發明之實施例圖示有中空封裝件之封裝方法的流程圖,其係用於製造有中空封裝件之封裝系統。
100‧‧‧封裝系統
102‧‧‧導線架
104‧‧‧終端引線
105‧‧‧垂直移位
106‧‧‧晶粒座
108‧‧‧化合物
110‧‧‧空腔
112‧‧‧晶粒
114‧‧‧黏晶材料
116‧‧‧電性互連
118‧‧‧黏著劑
120‧‧‧蓋體
122‧‧‧中空封裝件
Claims (10)
- 一種封裝方法(2200),係包括:形成終端引線(104);藉由用化合物(108)部份囊封該等終端引線(104)來組構空腔(110);在該空腔(110)中附接積體電路裝置(112)、微機電系統(112)、微機械系統(112)、或彼等之組合;以及接合蓋體(120)至該等終端引線(104)用於圍封該空腔(110),其中,該蓋體(120)接合於該終端引線(104)的頂面上及該化合物(108)的任何中介區上。
- 如申請專利範圍第1項所述的方法(2200),更包括在該空腔(110)中裝設通氣口(1104)。
- 如申請專利範圍第1項所述的方法(2200),其中,藉由用該化合物(108)部份囊封該等終端引線(104)來組構該空腔(110)的步驟係包含:在該等終端引線(104)的周圍模造該化合物(108)並讓該等終端引線(104)之一部份露出用於形成無引線封裝件。
- 如申請專利範圍第1項至第3項中任一項所述的方法(2200),其中:接合該蓋體(120)至該等終端引線(104)的步驟係包含:接合導電層壓基板(1004)至該等終端引線(104);以及更包括:在該空腔(110)上方、下方或上方與下方 形成在該等終端引線(104)與該導電層壓基板(1004)之間的導電互連(604);以及安裝附加之積體電路裝置(702)、附加之微機電系統(702)、附加之微機械系統(702)、或彼等之組合於該導電層壓基板(1004)上。
- 如申請專利範圍第1項至第3項中任一項所述的方法(2200),其中,組構該空腔(110)的步驟係包含:形成該等終端引線(104)與該化合物(108)用於在該空腔(110)的底側(907)上產生凹部。
- 一種封裝系統(100),係包括:終端引線(104);化合物(108),係用於部份囊封該等終端引線(104)以及組構空腔(110);在該空腔(110)中附接積體電路裝置(112)、微機電系統(112)、微機械系統(112)、或彼等之組合;以及蓋體(120),係接合至該等終端引線(104)用於圍封該空腔(110),其中,該蓋體(120)接合於該終端引線(104)的頂面上及該化合物(108)的任何中介區上。
- 如申請專利範圍第6項所述的系統(100),更包括在該空腔(110)中之通氣口(1104)。
- 如申請專利範圍第6項所述的系統(100),其中,藉由用該化合物(108)部份囊封該等終端引線(104)所組構之該空腔(110)係包含:在該等終端引線(104)周圍模造該化合物(108),並露出該等終端引線(104)之一部份用 以形成無引線封裝件。
- 如申請專利範圍第6項至第8項中任一項所述的系統(100),其中:接合至該等終端引線(104)之該蓋體(120)係包含接合至該等終端引線(104)的導電層壓基板(1004);更包括:在該空腔(110)上方、下方或上方與下方形成於該等終端引線(104)與該導電層壓基板(1004)之間的導電互連(604);以及安裝在該導電層壓基板(1004)上的附加之積體電路裝置(702)、附加之微機電系統(702)、附加之微機械系統(702)、或彼等之組合。
- 如申請專利範圍第6項至第8項中任一項所述的系統(100),其中,所組構之該空腔(110)係包含:以在該空腔(110)的底側(907)上有凹部的方式形成該等終端引線(104)與該化合物(108)。
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TW200537660A (en) * | 2004-05-11 | 2005-11-16 | Via Tech Inc | Stacked multi-chip package |
US20060261453A1 (en) * | 2005-03-16 | 2006-11-23 | Yonggill Lee | Semiconductor package and stack arrangement thereof |
Also Published As
Publication number | Publication date |
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US8493748B2 (en) | 2013-07-23 |
KR101501709B1 (ko) | 2015-03-11 |
SG148927A1 (en) | 2009-01-29 |
KR20080114627A (ko) | 2008-12-31 |
SG168516A1 (en) | 2011-02-28 |
TW200903680A (en) | 2009-01-16 |
US20090002961A1 (en) | 2009-01-01 |
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