TWI464875B - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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TWI464875B
TWI464875B TW101106979A TW101106979A TWI464875B TW I464875 B TWI464875 B TW I464875B TW 101106979 A TW101106979 A TW 101106979A TW 101106979 A TW101106979 A TW 101106979A TW I464875 B TWI464875 B TW I464875B
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insulating film
gate electrode
gate insulating
composition
electrode
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TW101106979A
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TW201308594A (zh
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Osamu Takata
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Toshiba Kk
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Description

半導體裝置 [關連申請之參照]
本發明主張JP2011-0176334之優先權(申請日：2011年8月11日)，內容亦引用其全部內容。
後述之實施形態概略關於半導體裝置。
習知之功率MOSFET(Metal-Oxide-Semiconductor Field-Effect Transistor：金氧半場效電晶體)係使用LDMOS(Laterally Diffused MOS：橫向擴散MOSFET)。通常，為減低導通(ON)電阻LDMOS之閘極絕緣膜之膜厚係被設為約12.5nm(奈米)，因此，閘極電壓限制於5V以下。因此，該LDMOS之電源電壓高於5V時，該電源電壓直接使用作為LDMOS之閘極電壓時，閘極絕緣膜有可能被破壞。因此，電源電壓高於5V時，需要LDMOS之閘極電壓之產生用之電路，導致電路複雜化。結果，半導體裝置成為大型化之同時，亦有成本增加之問題。
欲實現高閘極耐壓雖可考慮增厚閘極絕緣膜之厚度。但是，MOSFET之電流能力係和閘極絕緣膜之容量呈比例，閘極絕緣膜之容量係和閘極絕緣膜之膜厚呈反比例，因此增厚閘極絕緣膜時，和其呈反比例反而使電流能力降低，使導通電阻增加。另外，臨限值電壓亦增加。為減低臨 限值電壓而降低通道之雜質濃度，則短通道效應變為顯著，為改善此可增長通道長度，但此舉更增加導通電阻。為彌補導通電阻之增加而增大元件面積，則導致半導體裝置更加大型化之同時，成本亦隨之增加。壞
本發明欲解決的課題在於提供小型、成本低的半導體裝置。
實施形態之半導體裝置，其特徵為具備：導電型為p型之第1源極區域；導電型為p型之第1汲極區域；設於上述第1源極區域與上述第1汲極區域之間連接著導電型為n型之第1通道區域；設於上述第1通道區域上的第1下側閘極絕緣膜；設於上述第1下側閘極絕緣膜上的第1下側閘極電極；設於上述第1下側閘極電極上的第1上側閘極絕緣膜；設於上述第1上側閘極絕緣膜上的第1上側閘極電極；第1開關元件，被連接於上述第1下側閘極電極與上述第1源極區域之間；導電型為n型之第2源極區域；導電型為n型之第2汲極區域，被連接於上述第1汲極區域；導電型為p型之第2通道區域，係被連接於上述第2源極區域與上述第2汲極區域之間；設於上述第2通道區域上的第2下側閘極絕緣膜；設於上述第2下側閘極 絕緣膜上的第2下側閘極電極；設於上述第2下側閘極電極上的第2上側閘極絕緣膜；設於上述第2上側閘極絕緣膜上的第2上側閘極電極；及第2開關元件，係被連接於上述第2下側閘極電極與上述第2源極區域之間。
另一實施形態之半導體裝置，其特徵為具備：導電型為p型之源極區域；導電型為p型之汲極區域；設於上述源極區域與上述汲極區域之間連接著導電型為n型之通道區域；設於上述通道區域上的下側閘極絕緣膜；設於上述下側閘極絕緣膜上的下側閘極電極；設於上述下側閘極電極上的上側閘極絕緣膜；設於上述上側閘極絕緣膜上的上側閘極電極；及連接於上述下側閘極電極與上述源極區域之間的開關元件。
再另一實施形態之半導體裝置，其特徵為具備：導電型為n型之源極區域；導電型為n型之汲極區域；設於上述源極區域與上述汲極區域之間連接著導電型為p型之通道區域；設於上述通道區域上的下側閘極絕緣膜；設於上述下側閘極絕緣膜上的下側閘極電極；設於上述下側閘極電極上的上側閘極絕緣膜；設於上述上側閘極絕緣膜上的上側閘極電極；及連接於上述下側閘極電極與上述源極區域之間的開關元件。
依據上述構成之半導體裝置，可實現小型化及低成本化。
以下，參照圖面之同時說明本發明之實施形態。
首先，說明第1實施形態。
圖1係表示本實施形態之半導體裝置之例示電路圖，圖2係表示本實施形態之半導體裝置之LDMOS之例示平面圖，圖3係表示圖2所示A-A’線斷面圖。
如圖1所示，本實施形態之半導體裝置1係被供給電源電位VDD及接地電位GND。電源電位VDD，係較通常之邏輯電路所使用的驅動電位，例如5V(伏特)高的之電位，例如為30~80V之範圍內之某一定之電位。另外，於半導體裝置1，p通道型LDMOS11及n通道型LDMOS12相互連接而形成輸出電路。如後述，p通道型LDMOS11(以下，簡單稱為「pMOS11」)及n通道型LDMOS12(以下，簡單稱為「nMOS12」)，閘極電極係被積層2層。
於pMOS11之源極，係經由電源端子TVDD 被施加電源電位VDD。於nMOS12之源極，係經由接地端子TGND 被施加接地電位GND。pMOS11之汲極及nMOS12之汲極，係共通連接於輸出端子TOUT 。於pMOS11之上側閘極電極44(圖3參照)及nMOS12之上側閘極電極44，係經由輸入端子TIN 被輸入有輸入信號。輸入信號乃其之電位為電源電位VDD或接地電位GND之二值信號。
於pMOS11之下側閘極電極42(參照圖3)與pMOS11之源極之間連接著開關元件13。開關元件13，係進行pMOS11之下側閘極電極42之切換使其成為連接源極與否 ，例如為p通道型MOSFET。另外，於nMOS12之下側閘極電極42與nMOS12之源極之間連接著開關元件14。開關元件14，係對nMOS12之下側閘極電極42是否連接於源極進行切換者，例如為n通道型MOSFET。開關元件13及14例如為閘極電壓約5V之低電壓、且小電流之電晶體。開關元件13及14之面積，係小於pMOS11及nMOS12之面積。
另外，於pMOS11之下側閘極電極42與pMOS11之源極之間連接著齊鈉二極體15。齊鈉二極體15之陽極係連接於pMOS11之下側閘極電極42，陰極係連接於pMOS11之源極。另外，於nMOS12之下側閘極電極42與nMOS12之源極之間連接著齊鈉二極體16。齊鈉二極體16之陽極係連接於nMOS12之源極，陰極係連接於pMOS11之下側閘極電極42。
接著，說明pMOS11及nMOS12之構成。
如圖2及圖3所示，pMOS11係形成於矽基板20之表面。矽基板20之導電型例如為p型。於矽基板20上之一部分之區域設置導電型為p型之汲極側阱21，於汲極側阱21上之2處之區域設置導電型為n型之源極側阱22。另外，於汲極側阱21上之被源極側阱22挾持的區域設置導電型為p型之飄移區域23。源極側阱22與飄移區域23相互被連接。另外，源極側阱22下面係位於較飄移區域23之下面更下方。
於各源極側阱22上之遠離飄移區域23之區域，設置 導電型為p+ 型之源極區域24。於源極區域24之正上方區域及由該正上方區域看到的飄移區域23側，設置導電型為p型之LDD(Lightly Doped Drain)區域25。但是，LDD區域25係和飄移區域23被隔離。於LDD區域25上，在源極區域24之正上方區域設置矽化物層26。
於飄移區域23上之和源極側阱22隔離之區域，設置導電型為p+ 型之汲極區域27。於汲極區域27之正上方區域設置導電型為p型之LDD區域28。又，LDD區域28，由汲極區域27之正上方區域看係為被設於源極側阱22側之區域。於LDD區域28上設置矽化物層29。
藉由矽基板20、汲極側阱21、源極側阱22、飄移區域23、源極區域24、LDD區域25、矽化物層26、汲極區域27、LDD區域28及矽化物層29，構成矽基材30。於矽基材30上之一部分，設置例如由矽氧化物構成的STI(Shallow Trench Isolation：元件分離絕緣體)31。矽基材30之上面及STI31之上面係構成大略同一平面。
未設置STI31的區域，由上方看係成為長方形狀之開口部32a、32b、32c。開口部32a、32b、32c係沿各開口部之短邊方向依序被配列。於開口部32a及32c，源極側阱22一部分，LDD區域25及矽化物層26，以及飄移區域23之一部分係呈露出，於開口部32b，矽化物層29係呈露出。因此，STI31中之位於開口部32a與開口部32b之間之部分，以及位於開口部32b與開口部32c之間之部分，係被配置於源極區域24與汲極區域27之間。
在由STI31一部分之正上方區域至開口部32a與一部分之正上方區域之區域，及STI31一部分之正上方區域至開口部32c之一部分之正上方區域的區域，分別設置閘極積層體40。各閘極積層體40之形狀，係設為以開口部32a及32c之長邊方向為長邊方向的長方形，而將STI31一部分，飄移區域23之一部分，源極側阱22一部分及LDD區域25之一部分予以覆蓋。
於閘極積層體40，係由下層側起依序積層著下側閘極絕緣膜41、下側閘極電極42、上側閘極絕緣膜43、上側閘極電極44及矽化物層45。下側閘極絕緣膜41例如由矽氧化物構成，其膜厚例如為適用於約1.5~5.5V之閘極電壓的膜厚，例如為12.5nm。上側閘極絕緣膜43例如為單層之矽氧化膜，或矽氧化層及矽氮化層積層的2層膜(ON膜)，或者矽氧化層、矽氮化層及矽氧化層積層的3層膜(ONO膜)，其之藉由電氣測定法測定之膜厚係較下側閘極絕緣膜41為厚。於上側閘極絕緣膜43含有較矽氧化物為高介電率的矽氮化物，如此則可增加上側閘極絕緣膜43全體之介電率。
下側閘極電極42及上側閘極電極44例如為由添加雜質的多晶矽形成。於閘極積層體40之側面上設置例如由矽氧化物構成的側壁46。上述之源極側之LDD區域25，係大略配置於側壁46之正下方區域。另外，汲極側之LDD區域28未被配置於側壁46之正下方區域。又，圖2省略矽化物層45及側壁46之圖示。
於矽化物層26之正上方區域，配置著複數個源極觸部51，連接著矽化物層26。另外，於矽化物層29之正上方區域，配置著複數個汲極觸部52，連接著矽化物層29。另外，下側閘極電極42，係於其長邊方向由上側閘極電極44之正下方區域延伸。在由下側閘極電極42延伸部分之正上方區域設有下側閘極觸部53，連接著下側閘極電極42。另外，於矽化物層45之正上方區域設置1個上側閘極觸部54，被連接著矽化物層45。
另外，nMOS12亦被形成於矽基板20。亦即pMOS11及nMOS12係形成於同一之矽基板20。nMOS12之構成，係對於圖2及圖3所示pMOS11之構成，將矽基板20以外之構成要素之導電型設為相反者。亦即於nMOS12係設置n型之汲極側阱21、p型之源極側阱22、n型之飄移區域23、n+ 型之源極區域24、n型之LDD區域25、矽化物層26、n+ 型之汲極區域27、n型之LDD區域28及矽化物層29。另外，於矽基材30上選擇性設置STI31，於矽基板30及STI31之正上方區域之一部分設有閘極積層體40。
和pMOS11同樣，於閘極積層體40係由下層側依序積層下側閘極絕緣膜41、下側閘極電極42、上側閘極絕緣膜43、上側閘極電極44及矽化物層45積層。另外，於閘極積層體40之側面上設有側壁46。於pMOS11與nMOS12之間，下側閘極絕緣膜41之膜厚及組成互為相等，下側閘極電極42之厚度及組成互為相等，上側閘極絕 緣膜43之膜厚及組成互為相等，上側閘極電極44之厚度及組成互為相等，矽化物層45之厚度及組成互為相等。
說明上述構成的半導體裝置1之動作。
於圖4，橫軸取時間，縱軸取各信號之電位，而表示本實施形態之半導體裝置之動作之例示時序流程。
於pMOS11之源極常時被輸入電源電位VDD，於nMOS12之源極常時被輸入接地電位GND。另外，輸入端子TIN 之輸入信號係將電源電位VDD及接地電位GND予以切換而輸入。另外，於p通道型MOSFET構成的開關元件13之閘極，係使電源電位VDD及較其低5V之電位(VDD-5V)切換、輸入而作為p通道截止(cut-off)信號，於n通道型MOSFET構成的開關元件14之閘極，係使接地電位GND及較其高5V之電位(GND+5V)被切換、輸入而作為n通道截止信號。
以下參照圖4說明各信號之電位之變化及伴隨之各元件之狀態之變化。
(a)時刻t1
於時刻t1，係於開關元件13之閘極輸入電位(VDD-5V)作為p通道截止信號。因此，開關元件13成為導通狀態。另外，於開關元件14之閘極被輸入作為n通道截止信號的接地電位GND。因此，開關元件14成為非導通狀態。另外，於輸入端子TIN ，係被輸入電源電位VDD作為輸入信號。此時，開關元件13成為導通狀態，因此 pMOS11之下側閘極電極42之電位成為電源電位VDD，pMOS11成為非導通狀態。另外，開關元件14為非導通狀態，因此nMOS12之下側閘極電極42成為浮遊狀態，成為接地電位GND與電源電位VDD之間之電位。因此，nMOS12成為導通狀態。結果，接地電位GND被由輸出端子TOUT 輸出。此時，於nMOS12之上側閘極電極44與通道之間雖被施加高的電壓(VDD-GND)，因為下側閘極電極42之電位成為接地電位GND與電源電位VDD之間之電位，因此可以緩和被施加於上側閘極絕緣膜43及下側閘極絕緣膜41之電場。
(b)時刻t2
於時刻t2，被輸入至開關元件14之閘極的n通道截止信號，係由接地電位GND升壓至電位(GND+5V)。如此則，開關元件14成為導通狀態。
(c)時刻t3
於時刻t3，被輸入至輸入端子TIN 之輸入電位，係由電源電位VDD被切換為接地電位GND。此時，開關元件14成為導通狀態，因此電荷快速由nMOS12之下側閘極電極42排出，電位成為接地電位GND。結果，nMOS12成為非導通狀態。另外，於於該時點，開關元件13乃為導通狀態，pMOS11之下側閘極電極42之電位成為電源電位VDD，因此pMOS11乃為非導通狀態。
(d)時刻t4
於時刻t4，被輸入至開關元件13之閘極的p通道截止信號，係由電位(VDD-5V)升壓至電源電位VDD。如此則，開關元件13成為非導通狀態。結果，pMOS11之下側閘極電極42成為浮遊狀態，成為接地電位GND與電源電位VDD之間之電位，pMOS11成為導通狀態。結果，電源電位VDD由輸出端子TOUT 輸出。此時，於pMOS11之上側閘極電極44與通道之間雖被施加高的電壓(VDD-GND)，但因下側閘極電極42之電位成為接地電位GND與電源電位VDD之間之電位，因此可緩和施加於上側閘極絕緣膜43及下側閘極絕緣膜41之電場。
(e)時刻t5
於時刻t5，被輸入至開關元件13之閘極的p通道截止信號，係由電源電位VDD降壓至電位(VDD-5V)。如此則，開關元件13成為導通狀態。
(f)時刻t6
於時刻t6，被輸入至輸入端子TIN 的輸入電位，係由接地電位GND被切換為電源電位VDD。此時，開關元件13成為導通狀態，電荷被快速注入pMOS11之下側閘極電極42，電位成為電源電位VDD。結果，pMOS11成為非導通狀態。另外，於該時點，開關元件14乃保持導通狀態 ，nMOS12之下側閘極電極42之電位成為接地電位GND，nMOS12乃保持非導通狀態。
(g)時刻t7
於時刻t7，被輸入至開關元件14之閘極的n通道截止信號，係由電位(GND+5V)降壓至接地電位GND。如此則，開關元件14成為非導通狀態。結果，nMOS12之下側閘極電極42成為浮遊狀態，成為接地電位GND與電源電位VDD之間之電位，因此nMOS12成為導通狀態。結果，接地電位GND由輸出端子TOUT 被輸出。如此則，回復時刻t1之狀態。以後，重複時刻t1~t7之動作。
接著，說明本實施形態之效果。
本實施形態中，係於pMOS11及nMOS12分別依序積層下側閘極絕緣膜41、下側閘極電極42、上側閘極絕緣膜43及上側閘極電極44，而形成具有2層之閘極電極的閘極積層體40。如此則，被施加於各電晶體之源極-閘極間的閘極電壓，可由下側閘極絕緣膜41及上側閘極絕緣膜43分壓，因此可施加高的閘極電壓。因此，閘極電位可直接使用電源電位VDD及接地電位GND。結果，無須閘極電位產生用之電路，可實現半導體裝置之小型化及低成本化。另外，施加於下側閘極絕緣膜41及上側閘極絕緣膜43的電場應力可以緩和，可實現和通常之LDMOS同等之壽命。
另外，於本實施形態中，閘極絕緣膜被分為下側閘極 絕緣膜41及上側閘極絕緣膜43之2層，對於施加於pMOS11及nMOS12的閘極電壓，可以薄化下側閘極絕緣膜41之膜厚。因此，可增大下側閘極絕緣膜41之容量。如上述說明，MOSFET之電流能力係和閘極絕緣膜之容量呈比例，因此可增大pMOS11及nMOS12之電流能力，可抑低導通電阻。另外，和形成1片厚的閘極絕緣膜時比較，臨限值電壓增加等之弊害變少，成膜製程亦容易。
另外，本實施形態中，於pMOS11之下側閘極電極42與源極之間設有開關元件13。如此則，可切換pMOS11之下側閘極電極42對電源端子TVDD 之連接。同樣，於nMOS12之下側閘極電極42與源極之間設有開關元件14。如此則，可切換nMOS12之下側閘極電極42對於接地端子VGND 之連接。如此則，對各下側閘極電極42之電荷之充放電可以快速進行，半導體裝置1之動作可以高速化。
另外，如圖4所示，將輸入電位之切換時序，與開關元件13及14之導通/非導通之切換時序分別設為不同，則可於圖4之時刻t3時刻至t4之間之時間帶，及時刻t6與時刻t7之間之時間帶，將pMOS11及nMOS12雙方設為非導通狀態。如此則，輸入電位之切換時，pMOS11及nMOS12雙方可以同時成為導通狀態，可以確實防止貫穿電流流入電源端子TVDD 與接地端子VGND 之間。
另外，本實施形態中，於nMOS11之下側閘極電極42與源極之間，係設有以下側閘極電極42朝源極之方向為 順向的齊鈉二極體15。如此則，可防止下側閘極電極42之電位高於電源電位VDD之同時，在下側閘極電極42之電位較電源電位VDD低一定電壓以上時，逆向電流可經由齊鈉二極體15流入。如此則，可保護nMOS11之下側閘極絕緣膜41。同樣，於pMOS12之下側閘極電極42與源極之間，設有以源極朝向下側閘極電極42之方向為順向的齊鈉二極體16。如此則，可防止下側閘極電極42之電位低於接地電位GND之同時，當下側閘極電極42之電位較接地電位GND高一定電壓以上時，逆向電流會經由齊鈉二極體16流入。如此則，可保護pMOS11之下側閘極絕緣膜41。
接著，說明比較例。
圖5係表示本比較例之半導體裝置之例示電路圖， 圖6係表示本比較例之半導體裝置之LDMOS之例示斷面圖。
如圖5及圖6所示，本比較例之半導體裝置101，其和前述之第1實施形態比較之差異在於，於p通道型LDMOS111及n通道型LDMOS112分別僅各設置1層之閘極絕緣膜及閘極電極。亦即於閘極積層體140，係由下層側依序積層閘極絕緣膜141、閘極電極142及矽化物層145。於矽化物層145連接著閘極觸部154。閘極絕緣膜141之膜厚係對應於5V左右之閘極電壓之膜厚。
因此，於半導體裝置101，於p通道型LDMOS111之閘極無法被施加接地電位GND，因此作為低電位側之閘極 電位而需要用來產生電位(VDD-5V)之電位產生電路121。另外，需要對電源電位VDD及電位(VDD-5V)進行切換而對p通道型LDMOS111之閘極進行供給的反相器電路122。同樣，無法對n通道型LDMOS112之閘極施加電源電位VDD，需要電位產生電路123來產生作為高電位側之閘極電位的電位(GND+5V)。另外，亦需要反相器電路124，用於對接地電位GND與電位(GND+5V)進行切換而供給至n通道型LDMOS112之閘極。因此，半導體裝置101之電路構成複雜，小型化及低成本化變為困難。
接著，說明第2實施形態。
圖7係表示本實施形態之半導體裝置之例示電路圖， 圖8係表示本實施形態之半導體裝置之LDMOS之例示斷面圖。
如圖7及圖8所示，本實施形態之半導體裝置2和前述之第1實施形態比較之差異在於，於p通道型LDMOS11a及n通道型LDMOS12a分別各設置3層之閘極絕緣膜及閘極電極。亦即於閘極積層體40a，係由下層側依序積層下側閘極絕緣膜41、下側閘極電極42、中側閘極絕緣膜47、中側閘極電極48、上側閘極絕緣膜43、上側閘極電極44及矽化物層45。中側閘極絕緣膜47之電性膜厚，係較下側閘極絕緣膜41厚，較上側閘極絕緣膜43薄。另外，中側閘極電極48，可為浮遊狀態，或和下側閘極電極42同樣，於其和源極之間連接著開關元件及齊鈉二極體之其中至少一方。
本實施形態中和前述之第1實施形態比較，閘極電壓可由3個閘極絕緣膜分壓，可以施加更高的閘極電壓。例如，可以施加30~100V左右之閘極電壓。本實施形態中之上述以外之構成，動作及效果，均和前述之第1實施形態同樣。又，閘極絕緣膜及閘極電極，亦可積層4層以上。
接著，說明第3實施形態。
圖9係表示本實施形態之半導體裝置之例示斷面圖。
如圖9所示，於本實施形態之半導體裝置3，係於矽基板60設定輸出電路區域61、邏輯電路區域62及容量區域63。輸出電路區域61及邏輯電路區域62例如係藉由STI64被區隔。
於輸出電路區域61形成功率電路用MOSFET66。亦即於矽基板60之上層部分，源極區域71及汲極區域72係相互呈隔離被形成，源極區域71與汲極區域72之間成為通道區域73。於矽基板60上之通道區域73之正上方區域，係由下層側依序積層下側閘極絕緣膜74、下側閘極電極75、上側閘極絕緣膜76及上側閘極電極77。於源極區域71與下側閘極電極75之間，被連接著開關元件78。施加於功率電路用MOSFET66的閘極電壓，例如為30~80V左右。
於邏輯電路區域62形成邏輯電路用MOSFET67。亦即於矽基板60之上層部分，源極區域79與汲極區域80相互呈隔離被形成，源極區域79與汲極區域80之間則成為通道區域81。於矽基板60上之通道區域81正上方區域，係由下層側依序積層閘極絕緣膜82及閘極電極83。施 加於邏輯電路用MOSFET67的閘極電壓例如為5V，較施加於功率電路用MOSFET66的閘極電壓為低。
於容量區域63係設有PIP(Poly-Insulator-Poly)容量68。亦即於矽基板60上設置STI64，於STI64上由下層側依序積層絕緣膜84、下部電極85、容量絕緣膜86及上部電極87。
功率電路用MOSFET66之下側閘極絕緣膜74，邏輯用MOSFET67之閘極絕緣膜82，及PIP容量68之絕緣膜84，係藉由同一製程形成。因此，彼等絕緣膜之膜厚及組成互為相等。
另外，功率電路用MOSFET66之下側閘極電極75，邏輯電路用MOSFET67之閘極電極83，及PIP容量68之下部電極85，係藉由同一製程形成。因此，彼等電極之厚度及組成互為相等。
另外，功率電路用MOSFET66之上側閘極絕緣膜76，及PIP容量68之容量絕緣膜86，係藉由同一製程形成。因此，彼等絕緣膜之膜厚及組成互為相等。
另外，功率電路用MOSFET66之上側閘極電極77，及PIP容量68之上部電極87，係藉由同一製程形成。因此，彼等電極之厚度及組成互為相等。
本實施形態中，功率MOSFET66可以和邏輯電路用MOSFET67及PIP容量68同時形成。如此則，可抑制半導體裝置3之製造成本。本實施形態中之上述以外之效果係和前述之第1實施形態同樣。又，本實施形態中，係和 前述之第1實施形態同樣，功率MOSFET66可設為LDMOS。另外，和前述之第1實施形態同樣，可將p通道型MOSFET與n通道型MOSFET組合構成輸出電路。
接著，說明參考例。
圖10係表示本參考例之半導體裝置之例示電路圖。
如圖10所示，本參考例之半導體裝置91，其和前述之第1實施形態之半導體裝置1(參照圖1)比較之差異為，未設置開關元件13及14(參照圖1)。
於本參考例之半導體裝置91，雖無法實現圖4所示動作，但藉由閘極絕緣膜設為2層構成，可獲得閘極電壓之分壓效果。如此則，輸入電位可以直接使用電源電位VDD及接地電位GND，電路構成大為簡化。另外，藉由齊鈉二極體15及16之設置，可保護各LDMOS之下側閘極絕緣膜。
又，前述之各實施形態中說明之例，係將LDMOS構造或通常之MOS構造設為閘極電極為2層構造的電晶體構造，但不限定於此。只要具備2層構造之閘極電極的電晶體為場效電晶體，則例如亦可為DMOS(Double-Diffused MOSFET：二重擴散MOSFET)。
另外，前述之第1及第2實施形態中雖說明將高側電晶體(pMOS11)之閘極電極與低側電晶體(nMOS12)之閘極電極相互連接之例，但不限定於，亦可將兩閘極電極相互絕緣。
另外，前述之各實施形態中，可以相互組合而實施。
依據以上說明實施形態，可實現小型、成本低的半導 體裝置。
以上說明本發明之幾個實施形態，但是彼等實施形態僅為一例，並非用來限定本發明。彼等新規之實施形態可以其他各種形態實施，在不脫離發明要旨之範圍內可進行各種省略、取代或變更。彼等實施形態或其變形亦包含於發明之範圍或要旨之同時，亦包含於申請專利範圍記載之發明及其之等效範圍。
11‧‧‧pMOS
20‧‧‧矽基板
21‧‧‧汲極側阱
22‧‧‧源極側阱
23‧‧‧飄移區域
24‧‧‧源極區域
25‧‧‧LDD區域
26‧‧‧矽化物層
27‧‧‧汲極區域
28‧‧‧LDD區域
29‧‧‧矽化物層
30‧‧‧矽基材
31‧‧‧STI(Shallow Trench Isolation：元件分離絕緣體)
40‧‧‧積層體
41‧‧‧下側閘極絕緣膜
42‧‧‧下側閘極電極
43‧‧‧上側閘極絕緣膜
44‧‧‧上側閘極電極
45‧‧‧矽化物層
46‧‧‧側壁
51‧‧‧源極觸部
52‧‧‧汲極觸部
54‧‧‧上側閘極觸部
[圖1]第1實施形態之半導體裝置之例示電路圖。
[圖2]第1實施形態之半導體裝置之LDMOS之例示平面圖。
[圖3]圖2所示A-A’線之斷面圖。
[圖4]橫軸取時間，縱軸取各信號之電位，將第1實施形態之半導體裝置之動作予以例示的時序流程。
[圖5]比較例之半導體裝置之例示電路圖。
[圖6]比較例之半導體裝置之LDMOS之例示斷面圖。
[圖7]第2實施形態之半導體裝置之例示電路圖。
[圖8]第2實施形態之半導體裝置之LDMOS之例示斷面圖。
[圖9]第3實施形態之半導體裝置之例示斷面圖。
[圖10]參考例之半導體裝置之例示電路圖。
11‧‧‧pMOS
20‧‧‧矽基板
21‧‧‧汲極側阱
22‧‧‧源極側阱
23‧‧‧飄移區域
24‧‧‧源極區域
25‧‧‧LDD區域
26‧‧‧矽化物層
27‧‧‧汲極區域
28‧‧‧LDD區域
29‧‧‧矽化物層
30‧‧‧矽基材
31‧‧‧STI(Shallow Trench Isolation：元件分離絕緣體)
40‧‧‧積層體
41‧‧‧下側閘極絕緣膜
42‧‧‧下側閘極電極
43‧‧‧上側閘極絕緣膜
44‧‧‧上側閘極電極
45‧‧‧矽化物層
46‧‧‧側壁
51‧‧‧源極觸部
52‧‧‧汲極觸部
54‧‧‧上側閘極觸部

Claims (20)

  1. 一種半導體裝置，其特徵為具備：導電型為p型之第1源極區域；導電型為p型之第1汲極區域；設於上述第1源極區域與上述第1汲極區域之間連接著導電型為n型之第1通道區域；設於上述第1通道區域上的第1下側閘極絕緣膜；設於上述第1下側閘極絕緣膜上的第1下側閘極電極；設於上述第1下側閘極電極上的第1上側閘極絕緣膜；設於上述第1上側閘極絕緣膜上的第1上側閘極電極；第1開關元件，被連接於上述第1下側閘極電極與上述第1源極區域之間；導電型為n型之第2源極區域；導電型為n型之第2汲極區域，被連接於上述第1汲極區域；導電型為p型之第2通道區域，係被連接於上述第2源極區域與上述第2汲極區域之間；設於上述第2通道區域上的第2下側閘極絕緣膜；設於上述第2下側閘極絕緣膜上的第2下側閘極電極；設於上述第2下側閘極電極上的第2上側閘極絕緣膜 ；設於上述第2上側閘極絕緣膜上的第2上側閘極電極；及第2開關元件，係被連接於上述第2下側閘極電極與上述第2源極區域之間。
  2. 如申請專利範圍第1項之半導體裝置，其中，上述第1開關元件為，在上述第1通道區域被供給第1電位，上述第1上側閘極電極被供給較上述第1電位低的第2電位時，將上述第1下側閘極電極設為浮遊狀態之開關元件；上述第2開關元件為，在上述第2通道區域被供給上述第2電位，上述第2上側閘極電極被供給上述第1電位時，將上述第2下側閘極電極設為浮遊狀態之開關元件。
  3. 如申請專利範圍第1項之半導體裝置，其中另外具備：第1齊鈉二極體(Zener Diode)，其之陽極連接於上述第1下側閘極電極，陰極連接於上述第1源極區域；和第2齊鈉二極體，其之陽極連接於上述第2源極區域，陰極連接於上述第2下側閘極電極。
  4. 如申請專利範圍第1項之半導體裝置，其中於上述第1上側閘極電極及上述第2上側閘極電極，係被輸入共通之閘極電位。
  5. 如申請專利範圍第1項之半導體裝置，其中上述第1下側閘極絕緣膜之膜厚及組成，係相等於上 述第2下側閘極絕緣膜之膜厚及組成；上述第1下側閘極電極之厚度及組成，係相等於上述第2下側閘極電極之厚度及組成；上述第1上側閘極絕緣膜之膜厚及組成，係相等於上述第2上側閘極絕緣膜之膜厚及組成；上述第1上側閘極電極之厚度及組成，係相等於上述第2上側閘極電極之厚度及組成。
  6. 如申請專利範圍第1項之半導體裝置，其中另外具備：第3源極區域，第3汲極區域，設於上述第3源極區域與上述第3汲極區域之間的第3通道區域，設於上述第3通道區域上的閘極絕緣膜，及設於上述閘極絕緣膜上的閘極電極，上述閘極絕緣膜之膜厚及組成，係相等於上述第1下側閘極絕緣膜之膜厚及組成。
  7. 如申請專利範圍第1項之半導體裝置，其中另外具備：下部電極，設於上述下部電極上的容量絕緣膜，及設於上述容量絕緣膜上的上部電極，上述下部電極之厚度及組成，係相等於上述第1下側閘極電極之厚度及組成， 上述容量絕緣膜之膜厚及組成，係相等於上述第1上側閘極絕緣膜之膜厚及組成，上述上部電極之厚度及組成，係相等於上述第1上側閘極電極之厚度及組成。
  8. 一種半導體裝置，其特徵為具備：導電型為p型之源極區域；導電型為p型之汲極區域；設於上述源極區域與上述汲極區域之間連接著導電型為n型之通道區域；設於上述通道區域上的下側閘極絕緣膜；設於上述下側閘極絕緣膜上的下側閘極電極；設於上述下側閘極電極上的上側閘極絕緣膜；設於上述上側閘極絕緣膜上的上側閘極電極；及連接於上述下側閘極電極與上述源極區域之間的開關元件。
  9. 如申請專利範圍第8項之半導體裝置，其中上述開關元件為，在上述通道區域被供給第1電位，上述上側閘極電極被供給較上述第1電位低的第2電位時，將上述下側閘極電極設為浮遊狀態之開關元件。
  10. 如申請專利範圍第8項之半導體裝置，其中另外具備：齊鈉二極體，其之陽極連接於上述下側閘極電極，陰極連接於上述源極區域。
  11. 如申請專利範圍第8項之半導體裝置，其中 另外具備：中側閘極絕緣膜，被設於上述下側閘極電極與上述上側閘極絕緣膜之間及中側閘極電極，被設於上述中側閘極絕緣膜與上述上側閘極絕緣膜之間。
  12. 如申請專利範圍第8項之半導體裝置，其中另外具備：另一源極區域，另一汲極區域，設於上述另一源極區域與上述另一汲極區域之間的另一通道區域，設於上述另一通道區域上的閘極絕緣膜，及設於上述閘極絕緣膜上的閘極電極，上述閘極絕緣膜之膜厚及組成，係相等於上述下側閘極絕緣膜之膜厚及組成。
  13. 如申請專利範圍第8項之半導體裝置，其中另外具備：下部電極，設於上述下部電極上的容量絕緣膜，及設於上述容量絕緣膜上的上部電極，上述下部電極之厚度及組成，係相等於上述下側閘極電極之厚度及組成，上述容量絕緣膜之膜厚及組成，係相等於上述上側閘極絕緣膜之膜厚及組成， 上述上部電極之厚度及組成，係相等於上述上側閘極電極之厚度及組成。
  14. 一種半導體裝置，其特徵為具備：導電型為n型之源極區域；導電型為n型之汲極區域；設於上述源極區域與上述汲極區域之間連接著導電型為p型之通道區域；設於上述通道區域上的下側閘極絕緣膜；設於上述下側閘極絕緣膜上的下側閘極電極；設於上述下側閘極電極上的上側閘極絕緣膜；設於上述上側閘極絕緣膜上的上側閘極電極；及連接於上述下側閘極電極與上述源極區域之間的開關元件。
  15. 如申請專利範圍第14項之半導體裝置，其中上述開關元件為，在上述通道區域被供給第2電位，上述上側閘極電極被供給較上述第2電位高的第1電位時，將上述下側閘極電極設為浮遊狀態之開關元件。
  16. 如申請專利範圍第14項之半導體裝置，其中另外具備：齊鈉二極體，其之陽極連接於上述源極區域，陰極連接於上述下側閘極電極。
  17. 如申請專利範圍第14項之半導體裝置，其中另外具備：中側閘極絕緣膜，被設於上述下側閘極電極與上述上 側閘極絕緣膜之間及中側閘極電極，被設於上述中側閘極絕緣膜與上述上側閘極絕緣膜之間。
  18. 如申請專利範圍第14項之半導體裝置，其中另外具備：另一源極區域，另一汲極區域，設於上述另一源極區域與上述另一汲極區域之間的另一通道區域，設於上述另一通道區域上的閘極絕緣膜，及設於上述閘極絕緣膜上的閘極電極，上述閘極絕緣膜之膜厚及組成，係相等於上述下側閘極絕緣膜之膜厚及組成。
  19. 如申請專利範圍第14項之半導體裝置，其中另外具備：下部電極，設於上述下部電極上的容量絕緣膜，及設於上述容量絕緣膜上的上部電極，上述下部電極之厚度及組成，係相等於上述下側閘極電極之厚度及組成，上述容量絕緣膜之膜厚及組成，係相等於上述上側閘極絕緣膜之膜厚及組成，上述上部電極之厚度及組成，係相等於上述上側閘極電極之厚度及組成。
  20. 如申請專利範圍第14項之半導體裝置，其中另外具備：設於上述汲極區域與上述通道區域之間的元件分離絕緣體。
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Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9306055B2 (en) * 2014-01-16 2016-04-05 Microchip Technology Incorporated High voltage double-diffused MOS (DMOS) device and method of manufacture
CN104900199B (zh) 2014-03-05 2017-08-15 矽创电子股份有限公司 驱动模块及其显示装置
CN115513285A (zh) * 2022-11-22 2022-12-23 广州粤芯半导体技术有限公司 半导体器件及其制造方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5937399A (en) * 1993-12-02 1999-08-10 Tadahiro Ohmi Semiconductor integrated circuit
TW544870B (en) * 2002-07-26 2003-08-01 Winbond Electronics Corp Programming method and device of flash EEPROM
CN101061551A (zh) * 2004-09-21 2007-10-24 爱特梅尔股份有限公司 使用双位线作电流读出的低功率非易失性存储单元
US7542342B2 (en) * 2006-04-21 2009-06-02 Intersil Americas Inc. Multiple time programmable (MTP) PMOS floating gate-based non-volatile memory device for a general-purpose CMOS technology with thick gate oxide
US20110163370A1 (en) * 2004-10-04 2011-07-07 Kabushiki Kaisha Toshiba Semiconductor memory and fabrication method for the same

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2445137C3 (de) * 1974-09-20 1981-02-26 Siemens Ag, 1000 Berlin Und 8000 Muenchen Verfahren zum Betrieb eines n-Kanal-Speicher-FET, n-Kanal-Speicher-FET zur Ausübung des Verfahrens und Anwendung des Verfahrens auf die n-Kanal-Speicher-FETs einer Speichermatrix
JPH07321322A (ja) * 1994-05-20 1995-12-08 Citizen Watch Co Ltd 電界効果型トランジスタ
US5468981A (en) * 1994-09-01 1995-11-21 Advanced Micro Devices, Inc. Self-aligned buried channel/junction stacked gate flash memory cell
US7157784B2 (en) 2005-01-31 2007-01-02 Texas Instruments Incorporated Drain extended MOS transistors with multiple capacitors and methods of fabrication
US8294197B2 (en) * 2006-09-22 2012-10-23 Taiwan Semiconductor Manufacturing Company, Ltd. Program/erase schemes for floating gate memory cells
JP5141069B2 (ja) * 2007-03-28 2013-02-13 株式会社リコー 半導体装置
US7554846B2 (en) * 2007-06-28 2009-06-30 Micron Technology, Inc. Select gate transistors and methods of operating the same
US8053319B2 (en) 2009-02-23 2011-11-08 Globalfoundries Singapore Pte. Ltd. Method of forming a high voltage device
WO2010109963A1 (ja) * 2009-03-26 2010-09-30 株式会社 東芝 不揮発性プログラマブルロジックスイッチ
US8048765B2 (en) 2009-08-28 2011-11-01 Broadcom Corporation Method for fabricating a MOS transistor with source/well heterojunction and related structure

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5937399A (en) * 1993-12-02 1999-08-10 Tadahiro Ohmi Semiconductor integrated circuit
TW544870B (en) * 2002-07-26 2003-08-01 Winbond Electronics Corp Programming method and device of flash EEPROM
CN101061551A (zh) * 2004-09-21 2007-10-24 爱特梅尔股份有限公司 使用双位线作电流读出的低功率非易失性存储单元
US20110163370A1 (en) * 2004-10-04 2011-07-07 Kabushiki Kaisha Toshiba Semiconductor memory and fabrication method for the same
US7542342B2 (en) * 2006-04-21 2009-06-02 Intersil Americas Inc. Multiple time programmable (MTP) PMOS floating gate-based non-volatile memory device for a general-purpose CMOS technology with thick gate oxide

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