TWI456646B - 晶圓平坦化製程 - Google Patents

晶圓平坦化製程 Download PDF

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Publication number
TWI456646B
TWI456646B TW100133051A TW100133051A TWI456646B TW I456646 B TWI456646 B TW I456646B TW 100133051 A TW100133051 A TW 100133051A TW 100133051 A TW100133051 A TW 100133051A TW I456646 B TWI456646 B TW I456646B
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TW
Taiwan
Prior art keywords
material layer
layer
wafer
region
stop layer
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TW100133051A
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English (en)
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TW201241904A (en
Inventor
Brett Busch
Gowri Damarla
Anurag Jindal
Chia Yen Ho
Thy Tran
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Nanya Technology Corp
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Publication of TW201241904A publication Critical patent/TW201241904A/zh
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30625—With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Claims (13)

  1. 一種晶圓平坦化製程，包括：提供一晶圓，該晶圓包括一第一物質層及一第二物質層，且該晶圓定義有一第一區域及一第二區域，其中該第二物質層於垂直方向設置於該第一物質層上方，且該第二區域於水平方向鄰接該第一區域；進行一蝕刻製程，以去除該第一區域中的該第二物質層；形成一第三物質層順應性覆蓋該第一物質層及該第二物質層；順應性形成一毯覆式停止層於該第三物質層上；進行一第一化學機械研磨製程，以完全去除該第二區域中該第三物質層上方的該毯覆式停止層，此時該第一區域內的該第三物質層上，仍覆蓋有部分該毯覆式停止層；進行一第二化學機械研磨製程以平坦化該晶圓，其中以該第一物質層為基準，當該第二物質層之一相對高度小於或等於該毯覆式停止層之一相對高度，係以該毯覆式停止層做為一研磨停止層，或是當該第二物質層之一相對高度大於或等於該毯覆式停止層之一相對高度，係以該第二物質層做為一研磨停止層；以及進行一第三化學機械研磨製程以平坦化該晶圓，其中移除剩餘的該毯覆式停止層以及該第二區域中的該第三物質層。
  2. 如請求項1所述之晶圓平坦化製程，其中進行該第一化學機械研 磨製程時，使用非選擇性研磨液。
  3. 如請求項1所述之晶圓平坦化製程，其中進行該第二化學機械研磨製程時，使用相對於該毯覆式停止層及該第二物質層具有選擇性之研磨液。
  4. 如請求項2所述之晶圓平坦化製程，其中進行該第二化學機械研磨製程時，使用相對於該毯覆式停止層及該第二物質層具有選擇性之研磨液。
  5. 如請求項1、2、3或4所述之晶圓平坦化製程，其中進行該第三化學機械研磨製程時，使用非選擇性研磨液。
  6. 一種晶圓平坦化製程，包括：提供一晶圓，該晶圓包括一第一物質層及一第二物質層，且該晶圓定義有一第一區域及一第二區域，其中該第二物質層於垂直方向設置於該第一物質層上方，且該第二區域於水平方向鄰接該第一區域；進行一蝕刻製程，以去除該第一區域中的該第二物質層；形成一第三物質層順應性覆蓋該第一物質層及該第二物質層；順應性形成一毯覆式停止層於該第三物質層上；進行一第一化學機械研磨製程，以完全去除該第二區域中該第三物質層上方的該毯覆式停止層，此時該第一區域內的該第三 物質層上，仍覆蓋有部分該毯覆式停止層；進行一第二化學機械研磨製程以平坦化該晶圓，其中係以該第二物質層做為一研磨停止層或係以該毯覆式停止層做為一研磨停止層；以及移除剩餘的該毯覆式停止層。
  7. 如請求項6所述之晶圓平坦化製程，其中進行該第一化學機械研磨製程時，使用非選擇性研磨液。
  8. 如請求項6所述之晶圓平坦化製程，其中進行該第二化學機械研磨製程時，使用相對於該毯覆式停止層及該第二物質層具有選擇性之研磨液。
  9. 如請求項7所述之晶圓平坦化製程，其中進行該第二化學機械研磨製程時，使用相對於該毯覆式停止層及該第二物質層具有選擇性之研磨液。
  10. 如請求項6、7、8或9所述之晶圓平坦化製程，其中移除剩餘的該毯覆式停止層步驟以濕蝕刻方式進行。
  11. 如請求項9所述之晶圓平坦化製程，在移除剩餘的該毯覆式停止層步驟之後，另包括進行一第三化學機械研磨製程以平坦化該晶圓。
  12. 一種晶圓平坦化製程，包括：提供一晶圓，該晶圓包括一第一物質層及一第二物質層，且該晶圓定義有一第一區域及一第二區域，其中該第二物質層於垂直方向設置於該第一物質層上方，且該第二區域於水平方向鄰接該第一區域；進行一蝕刻製程，以去除該第一區域中的該第二物質層；形成一第三物質層順應性覆蓋該第一物質層及該第二物質層；順應性形成一毯覆式停止層於該第三物質層上；進行一第一化學機械研磨製程，以完全去除該第二區域中該第三物質層上方的該毯覆式停止層，此時該第一區域內的該第三物質層上，仍覆蓋有部分該毯覆式停止層；進行一選擇性乾蝕刻製程，以相對於該毯覆式停止層及該第二區域中的該第二物質層，選擇性去除該第二區域中的該第三物質層；以及進行一使用非選擇性研磨液的第二化學機械研磨製程以平坦化該晶圓之表面圖形。
  13. 如請求項12所述之晶圓平坦化製程，其中進行該第一化學機械研磨製程時，使用非選擇性研磨液。
TW100133051A 2011-04-06 2011-09-14 晶圓平坦化製程 TWI456646B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US13/080,676 US8580690B2 (en) 2011-04-06 2011-04-06 Process of planarizing a wafer with a large step height and/or surface area features

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KR102650539B1 (ko) 2016-09-23 2024-03-27 삼성전자주식회사 3차원 반도체 장치의 제조 방법
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Also Published As

Publication number Publication date
TW201241904A (en) 2012-10-16
CN102737978B (zh) 2014-12-17
US20120258596A1 (en) 2012-10-11
US8580690B2 (en) 2013-11-12
US8871103B2 (en) 2014-10-28
CN102737978A (zh) 2012-10-17
US20140038414A1 (en) 2014-02-06

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