TWI447848B - 形成記憶體單元陣列之方法，形成複數個場效電晶體之方法，形成源極／汲極區域及隔離溝渠之方法及在基板中形成一系列間隔溝渠之方法 - Google Patents

形成記憶體單元陣列之方法，形成複數個場效電晶體之方法，形成源極／汲極區域及隔離溝渠之方法及在基板中形成一系列間隔溝渠之方法 Download PDF

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TWI447848B
TWI447848B TW100107795A TW100107795A TWI447848B TW I447848 B TWI447848 B TW I447848B TW 100107795 A TW100107795 A TW 100107795A TW 100107795 A TW100107795 A TW 100107795A TW I447848 B TWI447848 B TW I447848B
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Neal L Davis
Richard T Housley
Ranjan Khurana
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Micron Technology Inc
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Description

形成記憶體單元陣列之方法，形成複數個場效電晶體之方法，形成源極/汲極區域及隔離溝渠之方法及在基板中形成一系列間隔溝渠之方法
本文中所揭示之實施例係關於形成記憶體單元陣列之方法、形成複數個場效電晶體之方法、形成源極/汲極區域及隔離溝渠之方法及在基板中形成一系列間隔溝渠之方法。
積體電路可製作於半導體基板上方及內部。電路之個別裝置組件由形成於半導體基板上方及/或內部之介電質或其他隔離與其他裝置組件分離開或電隔離開。一種形式之隔離通常稱作其中溝渠蝕刻至半導電基板材料中且隨後由一種或多種介電材料填充之溝渠隔離。
積體電路可經製作以具有許多功能，且可包括諸如電容器、電晶體、電阻器、二極體等許多不同電子裝置。一種類型之電路係包含個別記憶體單元陣列之記憶體電路。在某些記憶體電路中，個別記憶體單元包括一場效電晶體及一電荷儲存裝置，例如一電容器。
在積體電路製作中，使用多個不同遮罩及沈積步驟。實現沈積步驟及/或遮罩步驟之減少之處理可優於需要更多沈積步驟及/或遮罩步驟之製程。
首先參照圖1至11來闡述一形成一記憶體單元陣列之方法之一實例性實施例。在一個實施例中，該陣列中之個別記憶體單元包括一場效電晶體及一電荷儲存裝置。無論如何，本發明之一實施例亦包括一形成複數個場效電晶體之方法。
參見圖1，一基板片段通常以參考編號10來指示。在一個實施例中，此包含一半導體基板。在本文件之上下文中，術語「半導體基板」或「半導電基板」被界定為意指包含半導電材料之任一構造，該半導電材料包括(但不限於)諸如一半導電晶圓(單獨或在其上包含其他材料之總成中)及半導電材料層(單獨或在包含其他材料之總成中)之塊狀半導電材料。術語「基板」係指任一支撐結構，其包括(但不限於)上文所述的半導電基板。半導體基板10可係均質的或非均質的，例如包含多個不同組成區域及/或層。基板10包含具有形成於其上方之複數個間隔線14、15、16的半導電材料12。實例性半導電材料12包括單晶矽或多晶矽、砷化鎵、磷化銦或任何其他現有或有待開發之材料處理半導體性質。半導體基板10可包括諸如絕緣材料及導電材料之非半導電材料且可(舉例來說)包含一絕緣物上半導體基板。在所繪示實例中，半導電材料12具有一上部經摻雜區域18及一下部經摻雜區域20。下部經摻雜區域20將用作場效電晶體中之溝渠區域，且上部經區域18將用作源極/汲極區域。可提供額外區域或層，且可稍後在該處理期間形成區域18及20。
間隔線14、15、16可係均質的或非均質的，例如具有多個不同組成區域及/或層。在實例性實施例中，間隔線14、15、16可包含光阻劑、基本上由光阻劑組成、或由光阻劑組成。線14、15、16可包含一種或多種硬遮罩材料。此外，可提供一層或多層不同於半導電材料之材料作為區域18與間隔線14、15、16之間的基板10之一部分。實例包括一個或多個硬遮罩層及/或抗反射塗層，例如DARC(富含矽的氧氮化矽)及/或BARC(一旋轉有機膜)。在一個實施例中，該複數個間隔線形成為具有所繪示截面中之55奈米之標稱寬度及78奈米之其之間的間隔之一平行線陣列。另一選擇係，線14、15、16之寬度及其之間的間隔可相對於彼此不同。換言之，所有該等線寬度及所有該等間隔寬度不必相等。
參見圖2，間隔線14、15、16已被橫向修整以減小其各別寬度。此可藉由自該等間隔線之側面及頂部大致相等地移除材料之一各向同性蝕刻來實施。另一選擇係，可使用趨於自橫向側比自各別頂部蝕刻更多材料之化學品及條件。另一選擇係，可使用趨於自頂部比自橫向側蝕刻更多材料之化學品及條件。此外，無需進行橫向修整。圖1中之特徵寬度及間距可係或可不係亞微影的(sub-lithographic)，且圖2中之線寬度及間隔可係或可不係亞微影的。在一個實施例中，自每一線14、15、16之第一側壁橫向修整大約10奈米，從而提供一35奈米之線寬度，其中毗鄰線之間的間隔為約98奈米。為了繼續討論之目的，線14、15及16可視為具有可彼此相同或不同之各別最大寬度，其中35奈米係僅一個實例。在一個實例中，圖1之線14、15、16可視為個別具有大於圖2之線14、15、16之最大寬度之前體。此外，在其中使用橫向修整之一個實施例中，可進行對圖1線之蝕刻以產生圖2之線從而在無後續處理的情況下促成所期望最大寬度。另一選擇係，舉例來說，可將該等線修整為小於一所期望最大寬度，並隨後處理該等線以使其寬度增大至所期望最大寬度。
參見圖3，一間隔物形成層24已形成於該基板上方。此可係均質的或非均質的，且可包含導電、絕緣及半導電材料中之任一者，包括其任一組合。實例包括二氧化矽、氮化矽、多晶矽及導電金屬氮化物。
參見圖4，間隔物形成層24已經各向異性蝕刻以在該等間隔線之相對側上形成側壁間隔物26、27、28、29、30及31。此在該等線中之直接毗鄰線之間留下間隔32。間隔32可視為具有該等間隔物中之直接毗鄰間隔物之間的一各別最小寬度Ws 。最小寬度Ws 可對於不同間隔32係相同的或不同的。無論如何，在一個實施例中，線14、15及16中之個別線具有比間隔32之最小寬度大的最大寬度。在其中圖2中之線14、15、16具有一35奈米之最大寬度以及98奈米之直接毗鄰線之間的間隔之上述具體實例中，一實例性最小寬度Ws 為約20奈米，其中該等各別間隔物具有一約39奈米之最大寬度。此可例如藉由將層24沈積至一約39奈米之厚度來達成。層24既可在該蝕刻期間部分地被遮罩以形成間隔物26至31，亦可完全不被遮罩。
參見圖5，間隔線14、15、16(未顯示)已從間隔物26至31之間移除以在間隔物26至31之間分別形成交錯之第一及第二遮罩開口36、32。因此，創建一遮罩40，該遮罩將用於蝕刻其下方之基板材料12。第一遮罩開口36位於該等間隔線先前所在之處，且寬於第二遮罩開口32。第一遮罩開口36既可具有亦可不具有相同之最大寬度。此外，第二遮罩開口32既可具有亦可不具有相同之最大寬度。在一個實施例中，該陣列內之所有第一遮罩開口36之最大寬度皆相同，且該陣列內之所有第二遮罩開口32之寬度皆相同且小於該等第一遮罩開口之寬度。
上文闡述僅一種在一半導體基板之半導電材料上方之一遮罩中形成交錯之第一及第二遮罩開口之技術，其中該等第一遮罩開口寬於該等第二遮罩開口。可使用任一替代現有或有待開發之技術。無論如何，在一個實施例中，第一遮罩開口36比第二遮罩開口32寬至少1.5倍，且在一個實施例中，比第二遮罩開口32寬至少1.75倍。
參見圖6，第一遮罩開口36已用於在半導電材料12中蝕刻電晶體間(在電晶體之間)溝渠42且第二遮罩開口32已用於在半導電材料12中蝕刻電晶體內(在至少一單個電晶體內)溝渠44。電晶體間溝渠42被蝕刻成在半導電材料12內比電晶體內溝渠44寬且深。在一個實施例中，電晶體間溝渠42在半導電材料12內比電晶體內溝渠44深約兩倍。僅舉例來說，該半導電材料內之一實例性電晶體間溝渠深度為250奈米而該半導電材料內之一實例性電晶體內溝渠深度為125奈米。因此，對於所繪示之更淺及更深溝渠使用相同遮罩40。在一個實施例中，此蝕刻在無該陣列上方之額外遮罩的情況下進行以使得對電晶體間溝渠42及電晶體內溝渠44之所繪示蝕刻可同時進行。
可藉由利用與第二遮罩開口32之最大開口寬度相比較第一遮罩開口36之該等不同最大開口寬度來獲得與電晶體內溝渠44相比較電晶體間溝渠42之所繪示不同溝渠深度以實施一單個蝕刻。與使用更窄的遮罩開口相比較，及例如在該蝕刻包含電漿增強型蝕刻時，使用更寬的遮罩開口可在基板材料內產生更深的蝕刻。舉例而言，在半導電材料12基本上由經摻雜單晶矽組成時，將產生深度為溝渠44的大約兩倍之溝渠42之一實例性蝕刻技術包括當HBr處於一從約100 sccm到300 sccm之流率下、O2 處於一從約100 sccm到約300 sccm之流率下、基板溫度從約40℃到90℃、室壓力從約10毫托到60毫托、功率處於約200 W到500 W下、且電極電壓處於約200 V到400 V下時使用一電感耦合電漿蝕刻反應器。
電晶體間溝渠42及電晶體內溝渠44中之一者或兩者可由一種或多種介電材料填充。此外，當介電材料提供於兩者中時，此可由相同或不同介電材料填充。另一選擇係或另外，僅舉例來說，電晶體間溝渠42及電晶體內溝渠44中任何一者中之部分或全部可包含一製成電路構造中之空隙空間。
參見圖7中之一實例，一種或多種介電材料48已同時沈積至電晶體間溝渠42及電晶體內溝渠44兩者內。在此實例中，此沈積已繼續直至該兩個此類溝渠皆由介電材料48過填充為止。另外可在沈積介電材料48之前，例如藉由熱生長來給電晶體間溝渠42及電晶體內溝渠44襯以一介電質或其他材料。實例性材料48包括經摻雜二氧化矽、未經摻雜二氧化矽及/或氮化矽。
參見圖8，介電材料48已被平坦化至少回至半導電材料12之最外部表面，且由此間隔物26至31(未顯示)已被移除。間隔物26至31亦可在沈積介電材料48之前完全被移除，或者可部分或全部保留作為該製成積體電路構造之一部分。
2009年8月20日公開之Werner Juengling之美國專利申請公開案第2009/0206443號據此以引用方式全部併入仿佛全盤地包括於本文中。用以產生2009/0206443公開案中之圖2之構造之製造處理在不同時間蝕刻該兩個不同深度組溝渠並使用兩個不同介電質沈積步驟以用介電材料108及110來填充此等溝渠。根據此揭示內容，如上文所述之處理實現(但未必需要)在相同的各別時間蝕刻並填充該等不同深度溝渠。
處理可如2009/0206443公開案中所述進行以製作複數個場效電晶體，或以額外或其他方式製作複數個場效電晶體。舉例而言，處理可如關於2009/0206443公開案中之圖3至27所述進行以產生複數個場效電晶體，其中一個電晶體由本文中之圖9中之參考編號50指示。圖9圖解說明一單個電晶體50之半導電部分之一實例性半導電材料形狀，例如與2009/0206443公開案中之圖3至26相關聯實施之處理之結果。在本文中之圖9中，為清楚起見電晶體間溝渠42及電晶體內溝渠44內之隔離材料48(未顯示)已被移除。電晶體50包括自一基底192升起之一鰭190。鰭190包括一遠端部分，該遠端部分具有由延伸低於上部經摻雜區域18之深度之一電晶體內溝渠44分離開之兩個支腿194及196。所圖解說明之支腿194及196包括上部經摻雜區域18及下部經摻雜區域20之一頂部部分兩者。鰭190亦包括可大體上彼此平行、相對於彼此大體上呈一角度或相對於彼此大體上彎曲之兩個相對側200及202。亦顯示鰭190之邊緣204及206，且鰭190之邊緣204及206可大體上垂直於側200及202且大體上彼此平行、相對於彼此大體上呈一角度或相對於彼此大體上彎曲。
上部經摻雜區域18構成一對已在電晶體間溝渠42中之直接毗鄰溝渠之間的電晶體內溝渠44中之個別溝渠之相對側上之半導電材料12上形成之源極/汲極區域56。可在由電晶體間溝渠42中之直接毗鄰溝渠之間的該對源極/汲極區域56立面向內之半導電材料12內提供一通道區域208。接近於此通道區域以可操作方式提供一閘極。此在圖9中圖解顯示為構成一對分別橫向於該各別兩個相對側202及200上方之閘極184及186。在一個實施例中，電晶體50之閘極184及186中之任何一者包含相對於電晶體間溝渠42正交延伸之複數個閘極線中之一者之一部分。電晶體50可根據閘極184及186之一電壓選擇性地控制源極/汲極56之間的電流流動。當被導通時，電晶體50建立由圖解說明該兩個源 極/汲極之間的電流流動之箭頭208所表示之一通道。通道208可由自閘極184及186發出之電場建立。閘極184及186可根據各種圖案來激勵，例如如2009/0206443公開案中所述。
上文說明中之圖9係對於一藉由使用一個或多個閘極來建立一通道區域之電晶體及方法之僅一個實例性實施例。亦涵蓋替代構造及方法。舉例而言，且僅舉例來說，一閘極介電質及閘極可提供於電晶體內溝渠44內，例如如美國專利申請公開案第2006/0046407號之圖33中所示。
在一形成一記憶體單元陣列之方法之一個實施例中，形成複數個字線、複數個位元線及複數個電荷儲存裝置。舉例而言，且參見圖10，顯示兩個場效電晶體50a及50b，其中每一場效電晶體皆與一電荷儲存裝置且與一位元線連接。在圖10中，呈電容器形式之電荷儲存裝置60示意性地繪示為位元線BL1 、BL2 、BL3 。電荷儲存裝置60中之個別裝置與一個別電晶體之該對源極/汲極區域56中之一者電接觸。此外，所繪示位元線BL1 、BL2 、BL3 中之一者與該個別電晶體之該對源極/汲極區域56中之另一者電接觸。至少一個字線(例如字線186)係可操作地接近該個別電晶體之通道區域208。每一電晶體結合其字線、所連接位元線及所連接電荷儲存裝置構成一單個記憶體單元。
圖11圖解繪示圖10示意圖之一俯視圖。
在圖4之上述實施例中，線14、15、16個別具有比所繪示截面中該等線中之直接毗鄰線之間的該等間隔物中之直 接毗鄰間隔物之間的間隔32之最小寬度大的最大寬度。然而，此可為相反情況，其中該等線個別具有比該等線中之直接毗鄰線之間的該等間隔物中之直接毗鄰間隔物之間的一間隔之最小寬度小的最大寬度。舉例而言，圖12揭示其中此等寬度關係已為相反之圖4所繪示之實施例基板片段之一替代實施例基板片段10a。已在圖12中利用來自圖4實施例之相似編號，其中差別係以後綴「a」指示。後續處理可與圖5至11類似地進行以形成複數個場效電晶體，包括形成一個別包含一場效電晶體及一電荷儲存裝置之記憶體單元陣列之一方法。在此等實施例中，可對於該等電晶體間溝渠使用更寬的間隔32a且可對於該等電晶體內溝渠使用在移除線14a、15a及16a(圖13)之後留下的間隔36a。舉例而言，圖14顯示電晶體間溝渠42a及電晶體內溝渠44a。亦可使用上述技術中之任一者來製作其他記憶體單元陣列。
本發明之某些實施例涵蓋與隨後製作一通道區域及一閘極無關地在一半導體基板之半導電材料內形成場效電晶體之源極/汲極區域及隔離溝渠之方法。舉例而言，在一個實施例中，此一方法涵蓋在一半導體基板之半導電材料上方之一遮罩中形成一對第一遮罩開口及一第二遮罩開口。該對第一遮罩開口寬於第二遮罩開口。第二遮罩開口於該對第一遮罩開口之間，且在一個實施例中在該對第一遮罩開口之間居中。舉例而言，對於圖5，該兩個最左邊圖解說明之遮罩開口36可視為一實例性此對第一遮罩開口，且 於其之間的第二遮罩開口32可視為一遮罩40中之此第二遮罩開口。
使用此遮罩，在該半導電材料中蝕刻一對隔離溝渠及一電晶體內溝渠兩者。該等隔離溝渠形成穿過該等第一遮罩開口而該電晶體內溝渠形成穿過該第二遮罩開口。該等隔離溝渠被蝕刻成在該半導電材料內比該電晶體內溝渠寬且深。此處理例如繪示於圖6中。一對源極/汲極區域提供於該對隔離溝渠之間的該電晶體內溝渠之相對側上之半導電材料內。
本發明之實施例亦涵蓋與是否形成複數個場效電晶體無關地，且與形成源極/汲極區域無關地在一基板中形成一系列間隔溝渠之方法。此一方法之實例性實施例涵蓋在既可係亦可不係一半導體基板之一基板上方形成複數個間隔線。在該等間隔線之相對側上形成各向異性蝕刻之側壁間隔物。在一個實施例中，該等線中之個別線具有比該等線之直接毗鄰線之間的該等間隔物中之直接毗鄰間隔物之間的間隔之最小寬度大的最大寬度。另一選擇係，該等線中之個別線具有比該等線中之直接毗鄰線之間的該等間隔物中之直接毗鄰間隔物之間的間隔之最小寬度小的最小寬度。前者由圖4中之實例顯示而後者由圖12中之實例顯示。
移除該等間隔線以在該等間隔物之間形成一系列交錯之第一及第二遮罩開口。該等第一遮罩開口位於該等間隔線先前所在之處。在一個實施例(即，圖5之實施例)中，該等 第一遮罩開口寬於該等第二遮罩開口。在另一實施例(即，圖13之實施例)中，該等第一遮罩開口窄於該等第二遮罩開口。
分別經由該等交錯之第一及第二遮罩開口在該基板中同時蝕刻交錯之第一及第二溝渠，以在該基板內形成第一及第二溝渠。在一個實施例(即，圖6之實施例)中，該等第一溝渠形成為在該基板內比該等第二溝渠寬且深。在另一實施例(即，圖14之實施例)中，該等第一溝渠形成為在該基板內比該等第二溝渠窄且淺。
按照條例，已使用或多或少關於結構及方法特徵之特定語言闡述了本文中所揭示之標的物。然而，應理解，由於本文所揭示之方法包括實例實施例，因此申請專利範圍不限於所顯示及所闡述之具體特徵。因此，申請專利範圍係由字面措辭來提供完整範疇，且根據等效內容之教義適當地予以解釋。
10．．．基板片段
10a．．．替代實施例基板片段
12．．．半導電材料
14．．．間隔線
14a．．．線
15．．．間隔線
15a．．．線
16．．．間隔線
16a．．．線
18．．．上部經摻雜區域
20．．．下部經摻雜區域
24．．．間隔物形成層
26．．．側壁間隔物
27．．．側壁間隔物
28．．．側壁間隔物
29．．．側壁間隔物
30．．．側壁間隔物
31．．．側壁間隔物
32．．．第二遮罩開口、間隔
32a．．．間隔
36．．．第一遮罩開口
36a．．．間隔
40．．．第二遮罩開口
42．．．電晶體間溝渠
42a．．．電晶體間溝渠
44．．．電晶體內溝渠
44a．．．電晶體內溝渠
48．．．介電材料
50a．．．場效電晶體
50b．．．場效電晶體
50．．．電晶體
56．．．源極/汲極區域
60．．．電荷儲存裝置
184．．．閘極
186．．．字線
190．．．鰭
192．．．基底
194．．．支腿
196．．．支腿
200．．．側
202．．．側
204．．．邊緣
206．．．邊緣
208．．．通道區域
BL1 ．．．位元線
BL2 ．．．位元線
BL3 ．．．位元線
圖1係處於根據本發明之一實施例之製程中之一基板片段之一圖解剖面圖；圖2係繼圖1所顯示步驟之後的一處理步驟處之圖1基板之一視圖；圖3係繼圖2所顯示步驟之後的一處理步驟處之圖2基板之一視圖；圖4係繼圖3所顯示步驟之後的一處理步驟處之圖3基板之一視圖；圖5係繼圖4所顯示步驟之後的一處理步驟處之圖4基板之一視圖；
圖6係繼圖5所顯示步驟之後的一處理步驟處之圖5基板之一視圖；
圖7係繼圖6所顯示步驟之後的一處理步驟處之圖6基板之一視圖；
圖8係繼圖7所顯示步驟之後的一處理步驟處之圖7基板之一視圖；
圖9係圖8基板之一部分之一放大圖解透視圖，其中為清楚起見某些介電材料已移除；
圖10係繼圖8所顯示步驟之後的一處理步驟處之圖8基板之一視圖；
圖11係圖10之基板片段之一圖解俯視平面圖，其中圖10已沿圖11中線10-10截取；
圖12係處於根據本發明之一實施例之製程中之一基板片段之一圖解剖面圖；
圖13係繼圖12所顯示步驟之後的一處理步驟處之圖12基板之一視圖；及
圖14係繼圖13所顯示步驟之後的一處理步驟處之圖13基板之一視圖。
10．．．半導體基板
12．．．半導電材料
18．．．上部經摻雜區域
20．．．下部經摻雜區域
42．．．電晶體間溝渠
44．．．電晶體內溝渠
48．．．介電材料
50a．．．場效電晶體
50b．．．場效電晶體
56．．．源極/汲極區域
60．．．電荷儲存裝置
186．．．字線
208．．．通道區域
BL1 ．．．位元線
BL2 ．．．位元線
BL3 ．．．位元線

Claims (33)

  1. 一種在一基板中形成一系列間隔溝渠之方法，其包含：在一基板上方形成複數個間隔線；在該等間隔線之相對側上形成各向異性蝕刻之側壁間隔物，該等線中之個別線之最大寬度大於該等線中之直接毗鄰線之間的該等間隔物中之直接毗鄰間隔物之間的間隔之最小寬度；移除該等間隔線以在該等間隔物之間形成一系列交錯之第一及第二遮罩開口，該等第一遮罩開口位於該等間隔線先前所在之處且寬於該等第二遮罩開口，個別的該等第一開口具有由該等間隔物之橫向最內部之邊緣定義之橫向最內部之邊緣，個別的該等第二開口具有由該等間隔物之橫向最外部之邊緣定義之橫向最內部之邊緣；及分別經由該等交錯第一及第二遮罩開口在該基板中同時蝕刻交錯之第一及第二溝渠，以將該等第一溝渠形成為在該基板內比該等第二溝渠寬且深。
  2. 如請求項1之方法，其中形成該等間隔線包含：形成個別地具有大於該最大寬度之寬度之前體線；及橫向修整該等前體線之該寬度。
  3. 如請求項2之方法，其中該橫向修整係藉由蝕刻至該最大寬度。
  4. 如請求項3之方法，其包含形成該等前體線以包含光阻劑。
  5. 如請求項1之方法，其中該移除將該等第一遮罩開口形成為比該等第二遮罩開口寬至少1.5倍。
  6. 如請求項1之方法，其中該移除將該等第一遮罩開口形成為比該等第二遮罩開口寬至少1.75倍。
  7. 如請求項1之方法，其中該蝕刻包含電漿蝕刻。
  8. 如請求項1之方法，其中該基板包含半導電材料，該蝕刻將該等第一溝渠形成為在該半導電材料內之深度為該等第二溝渠的約兩倍。
  9. 如請求項1之方法，其包含以介電材料填充該等第一溝渠。
  10. 如請求項1之方法，其包含以介電材料填充該等第二溝渠。
  11. 如請求項1之方法，其包含以介電材料填充該等第一及第二溝渠。
  12. 如請求項11之方法，其中該填充包含同時於該等第一及第二溝渠中沈積該相同之介電材料。
  13. 如請求項12之方法，其包含繼續該沈積直至該等第一及第二溝渠皆由該介電材料過填充為止。
  14. 一種形成複數個場效電晶體之方法，其包含：在一半導體基板之半導體材料上方形成複數個間隔線；在該等間隔線之相對側上形成各向異性蝕刻之側壁間隔物，該等線中之個別線具有比直接毗鄰於直接毗鄰該等線之間的該第一及該第二間隔物之間的間隔之最小寬 度大的最大寬度；自該第一及該第二間隔物之間移除該等間隔線以形成包含由第一及第二遮罩開口交錯之一遮罩，該等第一遮罩開口係位於該等間隔線之位置且寬於該等第二遮罩開口，個別的該等第一開口具有由該第一及該第二間隔物之橫向最內部之邊緣定義之橫向最內部之邊緣，個別的該等第二開口具有由該第一及該第二間隔物之橫向最外部之邊緣定義之橫向最內部之邊緣；使用該遮罩，在該半導電材料中同時地蝕刻電晶體間溝渠及電晶體內溝渠兩者，該等電晶體間溝渠係經由該等第一遮罩開口而形成，該等電晶體內溝渠係經由該等第二遮罩開口而形成，該等電晶體間溝渠係蝕刻成在該半導電材料內比該等電晶體內溝渠寬且深；在該半導電材料內該等電晶體間溝渠中之直接毗鄰溝渠之間的該等電晶體內溝渠中之個別溝渠之相對側上提供一對源極/汲極區域；在該半導電材料內該等電晶體間溝渠中之直接毗鄰溝渠之間的該對源極/汲極區域的內立面上提供一通道區域；及提供可操作地接近該通道區域之一閘極。
  15. 如請求項14之方法，其包含用介電材料來填充該等電晶體間溝渠。
  16. 如請求項14之方法，其包含用介電材料來填充該等電晶體內溝渠。
  17. 如請求項14之方法，其包含用介電材料來填充該等電晶體間溝渠及該等電晶體內溝渠兩者。
  18. 如請求項17之方法，其中該填充包含將該相同之介電材料同時沈積至該等電晶體間溝渠及該等電晶體內溝渠兩者內。
  19. 如請求項18之方法，其包含繼續該沈積直至該等電晶體間溝渠及該等電晶體內溝渠兩者已過填充有該相同之介電材料為止。
  20. 如請求項14之方法，其包含形成該閘極以包含複數個閘極線中之一者之一部分，並將該複數個閘極線形成為相對於該等電晶體間溝渠正交延伸。
  21. 如請求項20之方法，其包含形成該閘極以包含該複數個閘極線中之兩者之部分。
  22. 如請求項14之方法，其中形成該等間隔線包含：形成個別地具有大於該最大寬度之寬度之前體線；及橫向修整該等前體線之該寬度。
  23. 一種形成個別地包含一場效電晶體及一電荷儲存裝置之一記憶體單元陣列之方法，其包含：在一半導體基板之半導電材料上方形成複數個間隔線；在該等間隔線之相對側上形成各向異性蝕刻之側壁間隔物，該等線中之個別線之最大寬度大於該等線中之直接毗鄰線之間的該等間隔物中之直接毗鄰間隔物之間的間隔之最小寬度； 自該等間隔物之間移除該等間隔線以在該等間隔物之間形成交錯之第一及第二遮罩開口，該等第一遮罩開口位於該等間隔線先前所在之處且寬於該等第二遮罩開口個別的該等第一開口具有由該等間隔物之橫向最內部之邊緣定義之橫向最內部之邊緣，個別的該等第二開口具有由該等間隔物之橫向最外部之邊緣定義之橫向最內部之邊緣；使用該等第一遮罩開口以在該半導電材料中蝕刻電晶體間溝渠並使用該等第二遮罩開口以在該半導電材料中蝕刻電晶體內溝渠，該等電晶體間溝渠係蝕刻成在該半導電材料內比該等電晶體內溝渠寬且深；在該半導電材料中同時蝕刻該等電晶體間溝渠及該等電晶體內溝渠；在該半導電材料內該等電晶體間溝渠中之直接毗鄰溝渠之間的該等電晶體內溝渠中之個別溝渠之相對側上提供一對源極/汲極區域；在該半導電材料內該等電晶體間溝渠中之直接毗鄰溝渠之間的該對源極/汲極區域的內立面上提供一通道區域；及形成複數個字線、複數個位元線及複數個電荷儲存裝置；該等電荷儲存裝置中之個別電荷儲存裝置與一個別電晶體之該對源極/汲極區域中之一者電接觸；該等位元線中之一者與該個別電晶體之該對源極/汲極區域中之另一者電接觸；該等字線中之一者係接納成可操作地接近 該個別電晶體之該通道區域。
  24. 如請求項23之方法，其包含用介電材料來填充該等電晶體間溝渠及該等電晶體內溝渠兩者，該填充包含將該相同之介電材料同時沈積至該等電晶體間溝渠及該等電晶體內溝渠兩者內。
  25. 如請求項24之方法，其包含繼續該沈積直至該等電晶體間溝渠及該等電晶體內溝渠兩者已過填充有該相同之介電材料為止。
  26. 如請求項23之方法，其中形成該等間隔線包含：形成個別地具有大於該最大寬度之寬度之前體線；及橫向修整該等前體線之該寬度。
  27. 如請求項26之方法，其包含形成該等前體線以包含光阻劑。
  28. 一種在一基板中形成一系列間隔溝渠之方法，其包含：在一基板上方形成複數個間隔線；在該等間隔線之相對側上形成各向異性蝕刻之側壁間隔物，該等線中之個別線之最大寬度小於該等線中之直接毗鄰線之間的該等間隔物中之直接毗鄰間隔物之間的間隔之最小寬度；移除該等間隔線以在該等間隔物之間形成一系列交錯之第一及第二遮罩開口，該等第一遮罩開口位於該等間隔線先前所在之處且窄於該等第二遮罩開口；及分別經由該等交錯之第一及第二遮罩開口在該基板中同時蝕刻交錯之第一及第二溝渠，以將該等第一溝渠形 成為在該基板內比該等第二溝渠窄且淺。
  29. 如請求項28之方法，其包含以介電材料填充該等第一溝渠。
  30. 如請求項28之方法，其包含以介電材料填充該等第二溝渠。
  31. 如請求項28之方法，其包含以介電材料填充該等第一及第二溝渠。
  32. 如請求項31之方法，其中該填充包含同時於該等第一及第二溝渠中沈積該相同之介電材料。
  33. 如請求項32之方法，其包含繼續該沈積直至該等第一及第二溝渠皆由該介電材料過填充為止。
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US8796086B2 (en) 2010-03-09 2014-08-05 Micron Technology, Inc. Methods of forming an array of memory cells, methods of forming a plurality of field effect transistors, methods of forming source/drain regions and isolation trenches, and methods of forming a series of spaced trenches into a substrate
TWI708320B (zh) * 2019-10-29 2020-10-21 南亞科技股份有限公司 半導體結構及其形成方法

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US8586429B2 (en) 2013-11-19
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US20110223734A1 (en) 2011-09-15
US20120021573A1 (en) 2012-01-26
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CN102792429A (zh) 2012-11-21
US8389353B2 (en) 2013-03-05
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US20130005115A1 (en) 2013-01-03

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