TWI708320B - 半導體結構及其形成方法 - Google Patents
半導體結構及其形成方法 Download PDFInfo
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- TWI708320B TWI708320B TW108145179A TW108145179A TWI708320B TW I708320 B TWI708320 B TW I708320B TW 108145179 A TW108145179 A TW 108145179A TW 108145179 A TW108145179 A TW 108145179A TW I708320 B TWI708320 B TW I708320B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 53
- 238000000034 method Methods 0.000 title claims abstract description 28
- 238000002955 isolation Methods 0.000 claims abstract description 67
- 125000006850 spacer group Chemical group 0.000 claims description 28
- 229910052751 metal Inorganic materials 0.000 claims description 13
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- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 3
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- 239000011574 phosphorus Substances 0.000 claims description 3
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- 239000004020 conductor Substances 0.000 description 3
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- 230000015572 biosynthetic process Effects 0.000 description 1
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
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- 239000002904 solvent Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
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- 239000010937 tungsten Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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Abstract
本揭露提供一種半導體結構及其形成方法。半導體結構包括一對主動區、第一隔離結構、閘極結構以及一對接觸件。第一隔離結構位於主動區之間。閘極結構位於第一隔離結構上。接觸件分別位於主動區上,其中接觸件的每一個具有底表面與側壁,側壁垂直於底表面。
Description
本揭露係有關於一種半導體結構與一種形成半導體結構的方法。
隨著電子產業的快速發展,積體電路(IC)的發展已實現高性能與微型化。積體電路材料與設計的技術進步已經產生了幾代的積體電路,其中每一代都比前一代具有較小與較複雜的電路。
接觸件用於在半導體結構的不同特徵內或之中建立連接。舉例來說,接觸件用於將一個金屬結構連接到另一金屬結構,否則前述的金屬結構彼此電性隔離,例如通過絕緣或介電材料來隔離金屬結構。然而,蝕刻製程的凹陷不均勻地形成。因此,在隨後的製程中,接觸件在凹陷中不均勻地形成,從而導致接觸件的吞吐量(through-put)降低。
本揭露之一技術態樣為一種半導體結構。
根據本揭露一實施方式,半導體結構包括一對主
動區、第一隔離結構、閘極結構以及一對接觸件。第一隔離結構位於主動區之間。閘極結構位於第一隔離結構上。接觸件分別位於主動區上,其中接觸件的每一個具有底表面與側壁,側壁垂直於底表面。
在本揭露的一些實施方式中,接觸件分別接觸於主動區。
在本揭露的一些實施方式中,主動區的每一個具有頂表面與側壁,側壁垂直於頂表面。
在本揭露的一些實施方式中,接觸件的每一個的底表面與側壁分別共形於主動區的每一個的頂表面與側壁。
在本揭露的一些實施方式中,半導體結構更包括第二隔離結構。主動區的其中一個位於第一隔離結構與第二隔離結構之間,並且第二隔離結構具有彎曲頂表面。彎曲頂表面鄰接於主動區的其中一個的頂表面。
在本揭露的一些實施方式中,半導體結構更包括第一間隔物、第二間隔物以及間隙。第一間隔物與第二間隔物位於閘極結構與接觸件的其中一個之間。間隙位於第一間隔物與第二間隔物之間。
在本揭露的一些實施方式中,第二間隔物位於主動區的其中一個上。
在本揭露的一些實施方式中,半導體結構更包括位元線接觸件、介電結構以及金屬結構。位元線接觸件位於閘極結構的下面。介電結構位於位元線接觸件與閘極結構之間。金屬結構位於介電結構與閘極結構之間。
在本揭露的一些實施方式中,接觸件的每一個的頂表面高於閘極結構的底表面。
在本揭露的一些實施方式中,主動區的每一個具有頂部,頂部具有階梯狀輪廓,並且接觸件的底表面低於主動區的頂部的複數頂表面。
在本揭露的一些實施方式中,接觸件的每一個的底表面低於位元線接觸件的底表面。
在本揭露的一些實施方式中,接觸件的側壁與底表面具有<100>晶向。
在本揭露的一些實施方式中,接觸件包括複數摻雜劑,摻雜劑包括磷。
本揭露之另一技術態樣為一種形成半導體結構的方法。
依據本揭露的一實施方式,形成半導體結構的方法包括以下步驟。在一對主動區之間形成第一隔離結構。在第一隔離結構上形成閘極結構。蝕刻主動區,以形成具有複數彎曲頂表面的複數凹陷。再次蝕刻主動區,以將彎曲頂表面的每一個改變為頂表面與側壁,側壁垂直於頂表面。在主動區上分別形成一對接觸件,使得接觸件的每一個具有底表面與側壁,側壁垂直於底表面。
在本揭露的一些實施方式中,形成半導體結構的方法更包括在形成接觸件之前,在主動區的頂表面與側壁上執行清洗處理。
在本揭露的一些實施方式中,形成半導體結構的
方法更包括形成第二隔離結構,使得主動區的其中一個位於第一隔離結構與第二隔離結構之間。
在本揭露的一些實施方式中,形成半導體結構的方法更包括蝕刻第二隔離結構,使得第二隔離結構具有彎曲頂表面的凹陷。
在本揭露的一些實施方式中,再次蝕刻主動區,以改變彎曲頂表面的每一個係通過執行溼式蝕刻。
在前述的實施方式中,因為半導體結構的接觸件的每一個具有底表面以及垂直於底表面的側壁,故可實現較高的成長率,並且接觸件可以均勻地形成在主動區上。因此,接觸件的高吞吐量可以被實現,並且半導體結構的效能可以被改善。
應當瞭解前面的一般說明和以下的詳細說明都僅是示例,並且旨在提供對本揭露的進一步解釋。
100‧‧‧半導體結構
110‧‧‧主動區
111‧‧‧彎曲頂表面
112‧‧‧頂表面
114‧‧‧側壁
116‧‧‧頂部
118‧‧‧頂表面
120‧‧‧第一隔離結構
122‧‧‧第二隔離結構
123‧‧‧彎曲頂表面
130‧‧‧閘極結構
132‧‧‧底表面
140‧‧‧接觸件
142‧‧‧底表面
144‧‧‧側壁
146‧‧‧頂表面
150‧‧‧第一間隔物
152‧‧‧第二間隔物
160‧‧‧位元線接觸件
162‧‧‧底表面
170‧‧‧介電結構
180‧‧‧金屬結構
190‧‧‧字元線
2-2‧‧‧線
G‧‧‧間隙
R1‧‧‧凹陷
R2‧‧‧凹陷
本揭露之態樣可從以下實施方式的詳細說明及隨附的圖式理解。
第1圖是根據本揭露的一實施方式的半導體結構的上視圖。
第2圖是第1圖的半導體結構沿線2-2的剖面圖。
第3圖是第2圖的局部放大圖。
第4圖、第5圖與第7圖是根據本揭露的一實施方式的在各個階段形成半導體結構的剖面圖。
第6圖是第5圖的局部放大圖。
第8圖是第7圖的局部放大圖。
第9圖是第7圖的上視圖。
現在將參照本揭露的實施方式,其示例被繪示在圖式中。本揭露在圖式及說明書中盡量使用相同的圖式元件號碼,來表示相同或相似的部分。
第1圖是根據本揭露的一實施方式的半導體結構100的上視圖、第2圖是第1圖的半導體結構100沿線2-2的剖面圖,以及第3圖是第2圖的局部放大圖。一併參閱第1圖至第3圖,半導體結構100包括一對主動區110、第一隔離結構120、閘極結構130以及一對接觸件140。第一隔離結構120設置於主動區110之間。閘極結構130設置於第一隔離結構120上。接觸件140分別設置於主動區110上。接觸件140可電性連接於導電組件,例如是電容器。接觸件140的每一個具有底表面142與側壁144,且側壁144垂直於底表面142。在前述的配置下,可以實現接觸件140的較高的成長率,並且可以在主動區110上均勻地形成接觸件140。因此,可以實現接觸件140的高吞吐量(through-put),並且可以改善半導體結構100的性能。
在一些實施方式中,接觸件140的每一個的底表面142與側壁144之間的角度大約為90度。在一些實施方式中,接觸件140的側壁144與底表面142具有<100>晶向(crystal orientation)。<100>晶向有助於增加接觸件140的成
長率與成長均勻性。因此,可以增加接觸件140的吞吐量。
在一些實施方式中,接觸件140分別接觸於主動區110。詳細來說,接觸件140從主動區110向上地凸出。
在一些實施方式中,主動區110具有頂表面112與實質上垂直於頂表面112的側壁114。接觸件140的底表面142與側壁144分別與主動區110的頂表面112與側壁114共形(conformal)。換句話說,接觸件140的底表面142與主動區110的頂表面112位於相同的水平高度,並且接觸件140的側壁144與主動區110的側壁114彼此面對。
在一些實施方式中,半導體結構100還包括第二隔離結構122。主動區110中的其中一個設置在第一隔離結構120與第二隔離結構122之間,並且第二隔離結構122具有與頂表面112鄰接的彎曲頂表面123。在一些實施方式中,接觸件140與主動區110接觸於第二隔離結構122。
在一些實施方式中,半導體結構100還包括第一間隔物150與第二間隔物152。第一間隔物150與第二間隔物152位於閘極結構130與接觸件140的其中一個之間,其中第一間隔物150與第二間隔物152之間具有間隙G。在一些實施方式中,第一間隔物150設置在第一隔離結構120上,而第二間隔物152設置於前述的第一隔離結構120旁邊的主動區110上。詳細來說,第一間隔物150與第二間隔物152分別接觸於第一隔離結構120與主動區110。
在一些實施方式中,半導體結構100還包括位元線接觸件(bit line contact)160、介電結構170以及金屬結構
180。位元線接觸件160設置在閘極結構130的下方。介電結構170設置在位元線接觸件160與閘極結構130之間。金屬結構180設置在介電結構170與閘極結構130之間。在一些實施方式中,第一間隔物150接觸於閘極結構130、金屬結構180、介電結構170以及第一隔離結構120,而第二間隔物152接觸於接觸件140以及主動區110。
在一些實施方式中,接觸件140的頂表面146高於閘極結構130的底表面132。在一些實施方式中,接觸件140的底表面142低於位元線接觸件160的底表面162。
在一些實施方式中,如第3圖所示,主動區110具有階梯狀輪廓(step profile)的頂部116,並且接觸件140的底表面142低於主動區110的頂部116的頂表面118。
在本實施方式中,閘極結構130可視為位元線(bit line;BL)。再者,如第1圖所示,半導體結構100還包括字元線(word line)190。字元線190的長度方向垂直於閘極結構130(亦即位元線)的長度方向。
在一些實施方式中,主動區110可包括矽。在一些實施方式中,第一隔離結構120與第二隔離結構122可以由氧化矽、氮化矽、氮氧化矽或其他適當的材料製成。第一隔離結構120與第二隔離結構122可以是淺溝槽隔離(shallow trench isolation;STI)結構。在一些實施方式中,閘極結構130可包括諸如鎢(W)的導電材料或其他適當的導電材料。閘極結構130的材料可不同於金屬結構180的材料。在一些實施方式中,接觸件140可以由包括摻雜的多晶矽的材料製成。接
觸件140可以包括複數摻雜劑,且前述的摻雜劑包括磷(P)。
第4圖、第5圖與第7圖是根據本揭露的一些實施方式的在各個階段形成第2圖的半導體結構100的剖面圖。
參閱第4圖。第一隔離結構120形成在一對主動區110之間。詳細來說,形成第二隔離結構122,使得主動區110的其中一個位於第一隔離結構120與第二隔離結構122之間。第一隔離結構120與第二隔離結構122可以藉由物理氣相沉積(PVD)、化學氣相沉積(CVD)等沉積方法形成。在形成第一隔離結構120之後,在第一隔離結構120上形成閘極結構130。
第6圖是第5圖的局部放大圖。一併參閱第5圖與第6圖,在形成閘極結構130之後,蝕刻主動區110,以形成凹陷R1,使得主動區110具有彎曲頂表面111。再者,蝕刻第二隔離結構122,使得第二隔離結構122具有凹陷R2,第二隔離結構122具有另一個彎曲頂表面123,且彎曲頂表面123位於彎曲頂表面111的旁邊。在一些實施方式中,第二隔離結構122的凹陷R2直接連接到主動區110的凹陷R1。第二隔離結構122的彎曲頂表面123鄰接主動區110的彎曲頂表面111。
在一些實施方式中,藉由乾式蝕刻製程來蝕刻主動區110與第二隔離結構122,以形成凹陷R1與凹陷R2。在一些實施方式中,可以選擇諸如氫氣(H2)與氮氣(N2)的乾式蝕刻劑用於乾式蝕刻製程。
第8圖是第7圖的局部放大圖,並且第9圖是第7圖的上視圖。參閱第7圖至第9圖,在蝕刻主動區110以形成具有如第5圖所示的彎曲頂表面111的凹陷R1之後,再次蝕刻主動
區110,以將彎曲頂表面111的每一個改變為頂表面112與側壁114,且側壁114實質上垂直於頂表面112。換句話說,第5圖的凹陷R1在側向與垂直方向上被擴展,使得主動區110的頂表面112與側壁114實質上彼此垂直。在一些實施方式中,再次蝕刻主動區110,而不蝕刻第二隔離結構122。換句話說,凹陷R1被擴展,而凹陷R2維持不變。
在一些實施方式中,通過溼式蝕刻製程再次蝕刻主動區110,以改變彎曲頂表面111的每一個。在一些實施方式中,可以選擇諸如氫氧化銨(NH4OH)的溼式蝕刻劑用於溼式蝕刻製程。在一些實施方式中,如第7圖所示的蝕刻製程中使用的蝕刻劑不同於如第5圖所示的蝕刻製程中使用的蝕刻劑。
在一些實施方式中,再次蝕刻主動區110之後,在主動區110的頂表面112與側壁114上執行清洗處理(clean treatment),以移除由第5圖與第7圖的蝕刻製程產生的殘餘顆粒。在一些實施方式中,可以選擇諸如氫氧化氨:過氧化氫:水(NH4OH:H2O2:H2O)(亦稱APM)與稀釋氫氟酸(diluted hydrofluoric acid;DHF)等清洗溶劑(蝕刻劑)用於清洗處理。因此,可以減少由蝕刻製程產生的顆粒,並且可以增加在後續製程中形成於凹陷R1與凹陷R2中的接觸件140的吞吐量。
再次蝕刻主動區110之後,分別在主動區110上形成接觸件140,使得接觸件140的每一個具有底表面142與側壁144,且側壁144實質上垂直於底表面142。如此一來,可以獲得如第2圖所示的半導體結構100。在一些實施方式中,在主
動區110上形成接觸件140的方法可以包括在第7圖的凹陷R1與凹陷R2中填入導電材料,然後執行回蝕(etch-back)操作。
綜上所述,因為半導體結構包括主動區、第一隔離結構、閘極結構以及接觸件,其中接觸件的每一個具有底表面以及垂直於底表面的側壁,故可實現較高的成長率,並且接觸件可以均勻地形成在主動區上。因此,接觸件的高吞吐量可以被實現,並且半導體結構的效能可以被改善。
雖然本揭露已經將實施方式詳細地揭露如上,然而其他的實施方式也是可能的,並非用以限定本揭露。因此,所附之權利要求的精神及其範圍不應限於本揭露實施方式之說明。
本領域任何熟習此技藝者,在不脫離本揭露之精神和範圍內,當可作各種之改變或替換,因此所有的這些改變或替換都應涵蓋於本揭露所附權利要求的保護範圍之內。
100‧‧‧半導體結構
110‧‧‧主動區
112‧‧‧頂表面
114‧‧‧側壁
120‧‧‧第一隔離結構
122‧‧‧第二隔離結構
123‧‧‧彎曲頂表面
130‧‧‧閘極結構
132‧‧‧底表面
140‧‧‧接觸件
142‧‧‧底表面
144‧‧‧側壁
146‧‧‧頂表面
150‧‧‧第一間隔物
152‧‧‧第二間隔物
160‧‧‧位元線接觸件
162‧‧‧底表面
170‧‧‧介電結構
180‧‧‧金屬結構
G‧‧‧間隙
Claims (18)
- 一種半導體結構,包含:一對主動區;一第一隔離結構,位於該對主動區之間;一閘極結構,位於該第一隔離結構上;以及一對接觸件,分別位於該對主動區上,其中該對接觸件的每一者具有一底表面與一側壁,該側壁垂直於該底表面。
- 如請求項1所述之半導體結構,其中該對接觸件分別接觸於該對主動區。
- 如請求項1所述之半導體結構,其中該對主動區的每一者具有一頂表面與一側壁,該側壁垂直於該頂表面。
- 如請求項3所述之半導體結構,其中該對接觸件的每一者的該底表面與該側壁分別共形於該對主動區的每一者的該頂表面與該側壁。
- 如請求項1所述之半導體結構,更包含:一第二隔離結構,其中該對主動區的其中一者位於該第一隔離結構與該第二隔離結構之間,並且該第二隔離結構具有一彎曲頂表面,該彎曲頂表面鄰接於該對主動區的其中一者的該頂表面。
- 如請求項1所述之半導體結構,更包含:一第一間隔物及一第二間隔物,位於該閘極結構與該對接觸件的其中一者之間;一間隙,位於該第一間隔物及該第二間隔物之間。
- 如請求項6所述之半導體結構,其中該第二間隔物位於該對主動區的其中一者上。
- 如請求項1所述之半導體結構,更包含:一位元線接觸件,位於該閘極結構的下面;一介電結構,位於該位元線接觸件與該閘極結構之間;以及一金屬結構,位於該介電結構與該閘極結構之間。
- 如請求項1所述之半導體結構,其中該對接觸件的每一者的一頂表面高於該閘極結構的一底表面。
- 如請求項1所述之半導體結構,其中該對主動區的每一者具有一頂部,該頂部具有一階梯狀輪廓,並且該對接觸件的該些底表面低於該對主動區的該些頂部的複數頂表面。
- 如請求項8所述之半導體結構,其中該對接觸件的每一者的該底表面低於該位元線接觸件的一底表面。
- 如請求項1所述之半導體結構,其中該對接觸件的該些側壁與該些底表面具有<100>晶向。
- 如請求項1所述之半導體結構,其中該對接觸件包含複數摻雜劑,該些摻雜劑包含磷。
- 一種形成半導體結構的方法,包含:形成一第一隔離結構,在一對主動區之間;形成一閘極結構,在該第一隔離結構上;蝕刻該對主動區,以形成具有複數彎曲頂表面的複數凹陷;再次蝕刻該對主動區,以將該些彎曲頂表面的每一者改變為一頂表面與一側壁,該側壁垂直於該頂表面;以及分別形成一對接觸件,在該對主動區上,使得該對接觸件的每一者具有一底表面與一側壁,該側壁垂直於該底表面。
- 如請求項14所述之形成半導體結構的方法,更包含:在形成該對接觸件之前,在該對主動區的該些頂表面與該些側壁上執行一清洗處理。
- 如請求項14所述之形成半導體結構的方法,更包含:形成一第二隔離結構,使得該對主動區的其中一者位於該第一隔離結構與該第二隔離結構之間。
- 如請求項16所述之形成半導體結構的方法,更包含:蝕刻該第二隔離結構,使得該第二隔離結構具有一彎曲頂表面的一凹陷。
- 如請求項14所述之形成半導體結構的方法,其中再次蝕刻該對主動區,以改變該些彎曲頂表面的每一者係通過執行溼式蝕刻。
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI845033B (zh) * | 2021-12-07 | 2024-06-11 | 南韓商三星電子股份有限公司 | 半導體記憶體裝置 |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5702969A (en) * | 1995-04-25 | 1997-12-30 | Samsung Electronics Co., Ltd. | Buried bit line DRAM cells and fabricating methods therefor |
US5977579A (en) * | 1998-12-03 | 1999-11-02 | Micron Technology, Inc. | Trench dram cell with vertical device and buried word lines |
TW469566B (en) * | 1998-06-11 | 2001-12-21 | Siemens Ag | Vertical device formed adjacent to a wordline sidewall and method for semiconductor chips |
US6689660B1 (en) * | 1997-07-08 | 2004-02-10 | Micron Technology, Inc. | 4 F2 folded bit line DRAM cell structure having buried bit and word lines |
TWI256103B (en) * | 2005-01-26 | 2006-06-01 | Promos Technologies Inc | Method for reducing line width of bit line and manufacturing bit line contact plug |
TWI400768B (zh) * | 2008-01-16 | 2013-07-01 | Micron Technology Inc | 用於交叉點之三維及三維肖脫基二極體、可變電阻材料記憶體、其製造方法及使用方法 |
TWI447848B (zh) * | 2010-03-09 | 2014-08-01 | Micron Technology Inc | 形成記憶體單元陣列之方法,形成複數個場效電晶體之方法,形成源極/汲極區域及隔離溝渠之方法及在基板中形成一系列間隔溝渠之方法 |
TWI634643B (zh) * | 2012-03-30 | 2018-09-01 | 南韓商三星電子股份有限公司 | 半導體元件及其製造方法 |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100470388B1 (ko) * | 2002-05-03 | 2005-02-07 | 주식회사 하이닉스반도체 | 독립적이고 비대칭적인 소스/드레인을 포함하는 디램 셀및 그 형성 방법 |
US8362552B2 (en) * | 2008-12-23 | 2013-01-29 | Alpha And Omega Semiconductor Incorporated | MOSFET device with reduced breakdown voltage |
US8765491B2 (en) * | 2010-10-28 | 2014-07-01 | International Business Machines Corporation | Shallow trench isolation recess repair using spacer formation process |
KR101177486B1 (ko) * | 2011-01-26 | 2012-08-27 | 에스케이하이닉스 주식회사 | 반도체 소자 및 그 형성 방법 |
US9076817B2 (en) * | 2011-08-04 | 2015-07-07 | International Business Machines Corporation | Epitaxial extension CMOS transistor |
US8533639B2 (en) * | 2011-09-15 | 2013-09-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Optical proximity correction for active region design layout |
KR101887414B1 (ko) * | 2012-03-20 | 2018-08-10 | 삼성전자 주식회사 | 반도체 장치 및 그 제조 방법 |
US9029220B2 (en) * | 2013-06-18 | 2015-05-12 | Infineon Technologies Austria Ag | Method of manufacturing a semiconductor device with self-aligned contact plugs and semiconductor device |
US9412842B2 (en) * | 2013-07-03 | 2016-08-09 | Samsung Electronics Co., Ltd. | Method for fabricating semiconductor device |
US9529956B2 (en) * | 2014-08-07 | 2016-12-27 | Taiwan Semiconductor Manufacturing Co., Ltd. | Active region design layout |
US9653462B2 (en) * | 2014-12-26 | 2017-05-16 | Samsung Electronics Co., Ltd. | Semiconductor device and method for fabricating the same |
US9287290B1 (en) * | 2015-02-11 | 2016-03-15 | Sandisk Technologies Inc. | 3D memory having crystalline silicon NAND string channel |
US9406675B1 (en) * | 2015-03-16 | 2016-08-02 | Taiwan Semiconductor Manufacturing Company Ltd. | FinFET structure and method of manufacturing the same |
US11282845B2 (en) * | 2017-08-24 | 2022-03-22 | Micron Technology, Inc. | Semiconductor devices comprising carbon-doped silicon nitride and related methods |
US10811422B2 (en) * | 2018-11-20 | 2020-10-20 | Globalfoundries Inc. | Semiconductor recess to epitaxial regions and related integrated circuit structure |
US10840351B2 (en) * | 2019-01-03 | 2020-11-17 | International Business Machines Corporation | Transistor with airgap spacer and tight gate pitch |
-
2019
- 2019-10-29 US US16/667,893 patent/US11145727B2/en active Active
- 2019-12-10 TW TW108145179A patent/TWI708320B/zh active
- 2019-12-17 CN CN201911301559.7A patent/CN112750757B/zh active Active
-
2021
- 2021-09-03 US US17/446,834 patent/US11538912B2/en active Active
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5702969A (en) * | 1995-04-25 | 1997-12-30 | Samsung Electronics Co., Ltd. | Buried bit line DRAM cells and fabricating methods therefor |
US6689660B1 (en) * | 1997-07-08 | 2004-02-10 | Micron Technology, Inc. | 4 F2 folded bit line DRAM cell structure having buried bit and word lines |
TW469566B (en) * | 1998-06-11 | 2001-12-21 | Siemens Ag | Vertical device formed adjacent to a wordline sidewall and method for semiconductor chips |
US5977579A (en) * | 1998-12-03 | 1999-11-02 | Micron Technology, Inc. | Trench dram cell with vertical device and buried word lines |
TWI256103B (en) * | 2005-01-26 | 2006-06-01 | Promos Technologies Inc | Method for reducing line width of bit line and manufacturing bit line contact plug |
TWI400768B (zh) * | 2008-01-16 | 2013-07-01 | Micron Technology Inc | 用於交叉點之三維及三維肖脫基二極體、可變電阻材料記憶體、其製造方法及使用方法 |
TWI447848B (zh) * | 2010-03-09 | 2014-08-01 | Micron Technology Inc | 形成記憶體單元陣列之方法,形成複數個場效電晶體之方法,形成源極/汲極區域及隔離溝渠之方法及在基板中形成一系列間隔溝渠之方法 |
TWI634643B (zh) * | 2012-03-30 | 2018-09-01 | 南韓商三星電子股份有限公司 | 半導體元件及其製造方法 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI845033B (zh) * | 2021-12-07 | 2024-06-11 | 南韓商三星電子股份有限公司 | 半導體記憶體裝置 |
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