TWI442571B - 薄膜電晶體 - Google Patents

薄膜電晶體 Download PDF

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TWI442571B
TWI442571B TW96137938A TW96137938A TWI442571B TW I442571 B TWI442571 B TW I442571B TW 96137938 A TW96137938 A TW 96137938A TW 96137938 A TW96137938 A TW 96137938A TW I442571 B TWI442571 B TW I442571B
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zinc oxide
substrate
semiconductor layer
gate
nanodisk
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TW200830557A (en
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Yuning Li
Beng S Ong
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Xerox Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B82NANOTECHNOLOGY
    • B82YSPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H01L29/045Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669Nanowires or nanotubes
    • H01L29/0673Nanowires or nanotubes oriented parallel to a substrate

Description

薄膜電晶體
本發明關於一種薄膜電晶體。特別地,此薄膜電晶體包括基板與經定向氧化鋅半導體層。
已知氧化鋅(ZnO)為薄膜電晶體(“TFT”)之通道半導體。其易得且可在周圍溫度處理。其亦具有非常高之電子遷移率(高達155平方公分/伏特.秒之整體遷移率及70平方公分/伏特.秒之場效遷移率),為環境安定性,具有大帶隙,無毒性,而且不昂貴。
然而,製造半導體之方法影響ZnO半導體層之遷移率。具有高遷移率(5~20平方公分/伏特.秒)之ZnO半導體通常只能藉由射頻磁控濺鍍而製造。此種設備昂貴且導致高製造成本。在另一種方法中,其使用ZnO前驅物,然後處理形成ZnO半導體層。然而,此方法需要溫度為400~550℃之退火步驟。此種溫度不適合在較低溫度變形之基板,如聚合基板,例如聚酯、聚碳酸酯、聚醯亞胺薄膜或薄片。亦已使用ZnO奈米粒子或奈米棒於溶液中在低(周圍)溫度製造ZnO半導體。然而,此種半導體具有低遷移率(~0.6平方公分/伏特.秒)。
氧化鋅薄膜結晶通常具有晶格參數a=3.2960及c=5.2065埃之Wurtzite結構(六面體對稱性)。氧化鋅之定向可使用例如x-射線繞射(XRD)技術分析。對於無規定向氧化鋅結晶,藉由使用Cu Kα輻射(λ 1.5418埃)可觀察到(100)、(002)與(101)平面之d-間隔距離各為d=2.81、2.60與2.48埃之三個峰。無規定向氧化鋅粉末樣品中三個峰之強度比例各為約I(100) /I(002) /I(101) =57/44/100(強度係得自The International Centre for Diffraction Data提供之ICDD/JCPDS卡號36-1451)。對於無規定向氧化鋅結晶,(002)峰之強度相對於(100)、(002)與(101)峰之強度和I(100) +I(002) +I(101) 的百分比,I(002) /[I(100) +I(002) +I(101) ]×100%為約22%±2%。
TFT通常在基板上由導電性閘極、源極與汲極、電絕緣閘極介電層(其將閘極與源極及汲極分隔)、及接觸閘極介電層且橋接源極及汲極之半導體層組成。
在各種具體實施例中,本發明關於一種包括基板、介電層及半導體層之薄膜電晶體,其中半導體層包括氧化鋅奈米碟(nanodisk),其c軸係垂直介電層或基板而定向。
在進一步具體實施例中,介電層或基板具有一個包括或已改質成包括至少一種極性官能基之表面。極性官能基進一步與奈米碟交互作用而助其自我組合成經適當定向的氧化鋅半導體層。
在額外具體實施例中,基板可具有低於300℃之變形溫度。基板可為聚合基板,例如聚酯、聚碳酸酯、聚醯亞胺薄膜或薄片。
在又進一步具體實施例中,本發明之TFT半導體具有至少1平方公分/伏特.秒之遷移率。在更特定具體實施例中,TFT具有至少5平方公分/伏特.秒之遷移率。
其亦揭示用於製造此種TFT之方法。
本發明之此等及其他非限制特性更特別地揭示於下。
雖然在以下說明中為了明確而使用特定術語,這些術語係僅用以指經選擇用於描述圖式之具體實施例的特定結構,而非用以界定或限制本發明之範圍。應了解,在圖式及以下說明中,同樣之號碼代號指同樣功能之組件。
第1圖略示地描述一種TFT組態10,其包括基板16、與其接觸之金屬接點18(閘極);及一層閘極介電層14,在其頂部沉積兩個金屬接點,源極20與汲極22。金屬接點20與22上方及其間為如本文所述之氧化鋅半導體層12。
第2圖略示地描述另一種TFT組態30,其包括基板36、閘極38、源極40與汲極42、閘極介電層34、及氧化鋅半導體層32。
第3圖略示地描述另一種TFT組態50,其包括基板(未示)/氧化銦錫(ITO)/氧化鋁鈦(ATO)(其中ITO 56為閘極且ATO 54為介電層)、及氧化鋅半導體層52,在其頂部沉積源極60與汲極62。
第4圖略示地描述另一種TFT組態70,其包括基板76、閘極78、源極80、汲極82、氧化鋅半導體層72、及閘極介電層74。
本發明之TFT具有包括氧化鋅奈米碟的半導體層,其c軸垂直介電層或基板平面而定向。半導體層之結晶氧化鋅較佳為以c軸垂直基板平面而定向。在具體實施例中,此較佳定向指半導體層之結晶氧化鋅具有大於約40%,大於約60%,大於約80%(或從約40%至約100%,從約60%至約100%,從約80%至約100%)之(002)峰之x-射線繞射強度相對於(100)、(002)與(101)峰之強度和的百分比I(002) /[I(100) +I(002) +I(101) ]×100%。其已發現在奈米碟以此方式定向時電子運輸最有利。
術語「奈米碟」在此指具有3維構造之奈米大小物體,其高度沿c軸且基底沿(002)平面;基底可為圓形(或近圓形)、多角形或不規則形狀;碟之高度等於或小於基底之直徑。在此亦包括氧化鋅奈米板作為奈米碟。各氧化鋅奈米碟可為氧化鋅單晶或可含許多種氧化鋅結晶(多晶);在後者情形,奈米碟中之氧化鋅結晶應具有其c軸係垂直奈米碟基底之較佳定向。奈米碟與奈米棒可由其結構區別;在奈米棒中,奈米棒之高度大於基底之直徑。
於上面沉積半導體層之介電層或基板可含有或經表面改質而含有表面極性官能基,如-OH、-NH2 、-COOH、-SO3 H、-P(=O)(OH)2 等。已發現ZnO奈米碟之(002)平面(最具極性且具有最高表面能量)與表面極性官能基強烈地交互作用,使得奈米碟以其c軸垂直介電層或基板而較佳地定向。
本發明之TFT半導體具有至少1平方公分/伏特.秒之遷移率。其超過大部份使用其他液體沉積技術所製造之TFT的遷移率。
本發明之氧化鋅半導體層係使用液體沉積技術。此技術包括將包括氧化鋅奈米碟之組成物沉積在TFT之介電層、基板或其他組件上方,視情況地在低於基板之變形溫度的溫度加熱,及視情況地冷卻。亦可重複此等步驟以形成由數個較小的副層所構成之較厚的半導體層。
複合劑視情況地用於氧化鋅奈米碟組成物,其具有下列可能益處:增加氧化鋅奈米碟在液體中之溶解度或分散力,增加氧化鋅奈米碟組成物之黏度以改良薄膜均勻性,及利於在薄膜中形成具有c軸垂直所得半導體層之經較佳定向的氧化鋅奈米碟。複合劑可為例如羧酸與有機胺。在具體實施例中,複合劑為一種選自例如由乙醇胺、胺基丙醇、二乙醇胺、2-甲胺基乙醇、N,N-二甲胺基乙醇、甲氧基乙胺、甲氧基丙胺、二胺基乙烷、二胺基丙烷、二胺基丁烷、二胺基環己烷、及其類似物、及其混合物所組成群組之有機胺。
可使用任何合適液體(包括例如有機溶劑與水)來分散或溶解氧化鋅奈米碟而形成氧化鋅奈米碟組成物。合適之有機溶劑包括烴溶劑,如戊烷、己烷、環己烷、庚烷、辛烷、壬烷、十一碳烷、十二碳烷、十三碳烷、十四碳烷、甲苯、二甲苯、三甲苯、及其類似物;醇,如甲醇、乙醇、丙醇、丁醇、戊醇、己醇、庚醇、乙二醇、甲氧基乙醇、乙氧基乙醇、甲氧基丙醇、乙氧基丙醇、甲氧基丁醇、二甲氧基二醇、及其類似物,酮,如丙酮、丁酮、戊酮、環己酮、及其類似物,四氫呋喃、氯苯、二氯苯、三氯苯、硝基苯、氰基苯、乙腈、N,N-二甲基甲醯胺、及其混合物。
氧化鋅奈米碟組成物之濃度為例如全部氧化鋅奈米碟組成物之約1至約80重量%,約2至約50重量%,而且特別是約5至約30重量%。選用複合劑對氧化鋅奈米碟之莫耳比例為例如約0.1至約10,約0.2至約5,而且特別是約0.5至約2。
在具體實施例中,可將其他成分併入包括氧化鋅奈米碟之組成物。此種成分包括例如聚合物,如聚苯乙烯、聚(甲基丙烯酸甲酯)、聚(乙烯基吡咯啶酮)、及其類似物,由如金、銀、及其類似物所構成之金屬奈米粒子,由如氧化矽、氧化鎵、氧化鋯、氧化鋁、氧化錫、氧化銦錫(ITO)、及其類似物及其混合物所構成之金屬氧化物奈米粒子。
液體沉積氧化鋅奈米碟組成物可藉任何液體沉積技術完成,例如旋塗、刮刀塗覆、棒塗、浸塗、網版印刷、微接觸印刷(microcontact printing)、噴墨印刷、壓印、及其類似技術。
在具體實施例中,視情況而使用之加熱步驟指在約50℃至約300℃間範圍內之一個溫度或數個溫度的熱處理。加熱可例如以立即加熱方式使用預熱加熱設備在特定溫度完成。在具體實施例中,加熱可以逐漸加熱方式完成,其自室溫(約25℃)開始或自約25℃至約100℃間之溫度開始,使用加熱設備可達成之加熱速率,範圍為例如每分鐘約0.5至約100℃。在進一步具體實施例中,加熱亦可在數個溫度逐步完成,例如在約100℃,然後在約200℃,然後在約300℃。在具體實施例中,加熱亦可在數個組合逐漸加熱的溫度逐步完成。加熱亦可例如在較高溫度,然後在較低溫度完成,如首先在約300℃然後在約200℃。
在具體實施例中,視情況而使用之「冷卻」指使所沉積的組成物之溫度為低於約100℃之溫度,而且特別是大約室溫(即約25℃)。冷卻可例如以自我冷卻方式藉由關閉加熱設備,或以控制方式按特定冷卻速率(例如約0.1℃/分鐘至100℃/分鐘)完成。在具體實施例中,其可採用如冷卻速率為約0.1℃/分鐘至約10℃/分鐘之緩慢冷卻,特別是自高於約300℃之溫度以降低半導體層及基板中之機械應變。
用於具體實施例之氧化鋅奈米碟的大小可具有約1奈米至約1000奈米之基底直徑。在指定具體實施例中,基底直徑為約1奈米至約500奈米。在進一步具體實施例中,基底直徑為約2奈米至約100奈米。氧化鋅奈米碟可具有約0.5奈米至約1000奈米之高度。在指定具體實施例中,高度為約0.5奈米至約500奈米。在進一步具體實施例中,高度為約1奈米至約100奈米。製備氧化鋅奈米碟之描述性實例可在數篇文章中發現。M.Monge、M.L.Kahn、A.Maisonnat與B.Chaudret之“Room-Temperature Organometallic Synthesis of Soluble and Crystalline ZnO Nanoparticles of Controlled Size and Shape”,Angew.Chem.,第115卷,5479-5482(2003)敘述一種在室溫於四氫呋喃使用二環己鋅與有機胺合成直徑為3~5奈米之氧化鋅奈米碟的方法。Y.Peng、A.Xu、B.Deng、M.Antonietti、與H.Colfen之“POlymer-Controlled Crystallization of Zinc Oxide Hexagonal Nanorings and Disks”,J.Phys.Chem.B,第110卷2988-2993(2006)揭露一種藉由將含經羧基改質之聚丙烯醯胺之Zn(NO3 )2 水溶液加熱而製備直徑為400奈米至1000奈米之氧化鋅奈米碟的方法。
本發明之氧化鋅半導體層可用於電子裝置,如大面積顯示器、射頻識別(RFID)標籤等,其使用具有例如大於1平方公分/伏特.秒之高場效遷移率的薄膜電晶體。
氧化鋅半導體層具有範圍為例如約10奈米至約1微米之厚度,特別是約20至約200奈米之厚度。TFT裝置含寬W及長L之半導體通道。半導體通道寬度可為例如約0.1微米至約5毫米,特定通道寬度為約5微米至約1毫米。半導體通道長度可為例如約0.1微米至約1毫米,更特定通道長度為約5微米至約100微米。
基板可由任何合適材料組成,例如矽、玻璃、鋁、或塑膠。基板之厚度可為約10微米至超過10毫米,堅硬基板(如玻璃板或矽晶圓)之代表性厚度為約1至約10毫米。
閘極可為薄金屬膜、導電聚合物薄膜、由導電墨或漿料製成之導電薄膜、或基板本身(例如重度摻雜矽)。閘極材料之實例包括但不限於鋁、鎳、金、銀、銅、鋅、銦、氧化鋅鎵、氧化銦錫、氧化銦銻、導電聚合物(如聚苯乙烯磺酸酯摻雜聚(3,4-伸乙二氧基噻吩)(PSS-PEDOT))、由聚合物黏合劑之碳黑/石墨或膠體銀分散液所構成的導電墨/漿料(如得自Acheson Colloids Company之ELECTRODAGTM )。閘極可利用金屬或導電性金屬氧化物之真空蒸發、濺鍍;藉旋塗、流延或印刷由導電聚合物溶液或導電墨水之塗覆而製備。閘極之厚度對金屬薄膜範圍為例如約10至約200奈米,及對聚合物導體為約1至約10微米之範圍。適合使用作為源極與汲極之典型材料包括如鋁、鋅、銦、導電性金屬氧化物(如氧化鋅鎵、氧化銦錫、氧化銦銻)、導電聚合物、及導電墨之閘極材料。源極與汲極之典型厚度為例如約40奈米至約1微米,更特定厚度為約100至約400奈米。
閘極介電層通常可為無機材料薄膜或有機聚合物薄膜。適合作為閘極介電層之無機材料的描述性實例包括氧化鋁鈦、氧化鋁、氧化矽、氮化矽、鈦酸鋇、鈦酸鋇鋯、及其類似物;閘極介電層用有機聚合物之描述性實例包括聚酯、聚碳酸酯、聚(乙烯基酚)、聚醯亞胺、聚苯乙烯、聚(甲基丙烯酸酯)類、聚(丙烯酸酯)類、環氧樹脂、及其類似物。依所使用介電材料之介電常數而定,閘極介電層之厚度為例如約10奈米至約2000奈米。閘極介電層之代表性厚度為約100奈米至約500奈米。閘極介電層可具有例如小於約10-12 S/公分之導電度。
在具體實施例中,閘極介電層、閘極、半導體層、源極、及汲極係按任何順序,以閘極與半導體層兩者均接觸閘極介電層,及源極與汲極兩者均接觸半導體層而形成。片語「按任何順序」包括循序及同時形成。例如源極與汲極可同時或循序形成。
對於n-通道TFT,源極接地且對汲極施加通常為例如約0伏特至約80伏特之偏壓,以在對閘極施加通常為約-20伏特至約+80伏特之電壓時收集跨越半導體通道運輸之電荷載子。
在具體實施例中,TFT裝置中之氧化鋅半導體層通常呈現大於例如約1平方公分/伏特.秒(每秒每伏特之平方公分)之場效遷移率,及大於例如約103 之開/關比(on/off ratio)。開/關比指電晶體開時之源極-汲極電流對電晶體關時之源極-汲極電流的比例。
應了解,各種以上揭示及其他特點與功能或其替代方案可如所需組合成許多其他不同之系統或應用。其中各種目前未知或未預期替代方案、修改、變化、或改良可繼而由熟悉此技藝者完成,其亦意圖包括於以下之申請專利範圍。除非在申請專利範圍中特別地列舉,申請專利範圍之步驟或成分不應依說明書或任何其他申請專利範圍意指或意含任何特定次序、數量、位置、大小、形狀、角度、顏色、或材料。
10...TFT組態
12...氧化鋅半導體層
14...閘極介電層
16...基板
18...閘極
20...源極
22...汲極
30...TFT組態
32...氧化鋅半導體層
34...閘極介電層
36...基板
38...閘極
40...源極
42...汲極
50...TFT組態
52...氧化鋅半導體層
54...ATO介電層
56...ITO閘極
60...源極
62...汲極
70...TFT組態
72...氧化鋅半導體層
74...閘極介電層
76...基板
78...閘極
80...源極
82...汲極
第1圖為本發明之TFT的第一例示具體實施例。
第2圖為本發明之TFT的第二例示具體實施例。
第3圖為本發明之TFT的第三例示具體實施例。
第4圖為本發明之TFT的第四例示具體實施例。
70...TFT組態
72...氧化鋅半導體層
74...閘極介電層
76...基板
78...閘極
80...源極
82...汲極

Claims (3)

  1. 一種薄膜電晶體,其包括:基板;閘極、源極與汲極;介電層;及半導體層;其中該半導體層包括氧化鋅奈米碟,該等氧化鋅奈米碟的c軸係垂直該介電層或該基板而定向,及其中該半導體層係沉積在該基板之一表面上,且該基板在該表面上具有至少一種極性官能基。
  2. 一種薄膜電晶體,其包括:聚合基板;閘極、源極與汲極;介電層;及半導體層,其中該半導體層包括氧化鋅奈米碟,該等氧化鋅奈米碟的c軸係垂直該基板而定向,及其中該半導體層係沉積在該基板之一表面上,且該基板在該表面上具有至少一種極性官能基。
  3. 一種薄膜電晶體,其包括:聚合基板;閘極、源極與汲極;介電層;及半導體層,其中該半導體層包括氧化鋅奈米碟,該等氧化鋅奈米碟的c軸係垂直該介電層而定向,及 其中該半導體層係沉積在該基板之一表面上,且該基板在該表面上具有至少一種極性官能基。
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