TWI431724B - 半導體結構及其製造方法 - Google Patents

半導體結構及其製造方法 Download PDF

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TWI431724B
TWI431724B TW097123688A TW97123688A TWI431724B TW I431724 B TWI431724 B TW I431724B TW 097123688 A TW097123688 A TW 097123688A TW 97123688 A TW97123688 A TW 97123688A TW I431724 B TWI431724 B TW I431724B
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layer
germanium
gate dielectric
material layer
semiconductor structure
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TW200939398A (en
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Ding Yuan Chen
Chen Hua Yu
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Taiwan Semiconductor Mfg
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Description

半導體結構及其製造方法
本發明係有關於一種半導體結構及其製造方法，特別係有關於互補式金氧半導體裝置及其製造方法。
第1圖至第5圖繪示習知互補式MOS(complementary MOS,CMOS)裝置的製程剖面圖。第1圖顯示包含NMOS區4及PMOS區6的矽基底2。於矽基底2上毯覆式地形成一高介電係數閘極介電層8。接著形成N型金屬層(N－metal layer)10。接著形成一硬罩幕12，並對其進行圖案化，以遮蔽NMOS區4。在第2圖中，將PMOS區6內的介電層8及N型金屬層10移除。PMOS區6內的矽基底2也被移除以形成一凹處7。如第3圖所示，接著在凹處7內磊晶形成矽鍺材料層14。第4圖顯示毯覆性地形成高介電係數閘極介電層16、P型金屬層(P－metal layer)18及硬罩幕19。第5圖顯示接著將NMOS區4內的高介電係數閘極介電層16、P型金屬層18及硬罩幕19移除。
第5圖中所顯示的堆疊層可用來形成位於NMOS區4內的NMOS元件(未顯示於圖中)，以及位於PMOS區6內的PMOS元件(未顯示於圖中)。因此所形成之PMOS元件的通道區是由矽鍺材料層14所形成。此有利於將PMOS元件的臨界電壓(threshold voltage)降低。此 外，與具有矽通道的PMOS元件相比，具有矽鍺通道的PMOS元件其電洞移動率較高。因此能夠增進形成於PMOS區6內之PMOS元件的驅動電流(drive current)。
然而，以上述方法所形成的CMOS元件有其缺點。由於形成於NMOS區4內之NMOS元件的通道區，並無來自於通道區下方之基底的應力，因此NMOS元件的驅動電流小於理想值。再者，由於矽鍺材料層14內的鍺元素可能會擴散至高介電係數介電層16，因此會在所形成的PMOS元件內造成漏電流。因此有需要能夠增進NMOS元件的驅動電流，及降低PMOS元件漏電流的製造方法。
本發明提供一種半導體結構的製造方法，包括下列步驟。提供一半導體基底，該半導體基底包含一第一區及一第二區。形成一第一MOS元件，包括：於該半導體基底的該第一區上形成一第一矽鍺材料層；於該第一矽鍺材料層上形成一矽材料層；於該矽材料層上形成一第一閘極介電層；以及圖案化該第一閘極介電層以形成一第一閘極介電結構。以及形成一第二MOS元件，包括：於該半導體基底的該第二區上形成一第二矽鍺材料層；於該第二矽鍺材料層上形成一第二閘極介電層，其中該第二MOS元件中的該第二矽鍺材料層及該第二閘極介電層之間並不具有一大體上的純矽材料層；以及圖案化該第二閘極介電層以形成一第二閘極介電結構。
本發明也提供一種半導體結構的製造方法，包括下列步驟。提供一矽基底，該矽基底包含一NMOS區及一PMOS區。於該矽基底上磊晶形成一第一矽鍺材料層，其中該第一矽鍺材料層包括位於該NMOS區上的一第一部分，及位於該PMOS區上的一第二部分。於該第一矽鍺材料層上磊晶形成一矽材料層。於該矽材料層上形成一第一閘極介電層。於該第一閘極介電層上形成一第一閘極電極層。移除該PMOS區上的該第一閘極電極層、該第一閘極介電層及該矽材料層。形成一第二閘極介電層，其中該第二閘極介電層包括至少一部分是位於該第一矽鍺材料層的該第二部分上。於該第二閘極介電層上形成一第二閘極電極層。圖案化該第一閘極介電層及該第一閘極電極層以形成一第一閘極堆疊結構。以及圖案化該第二閘極介電層及該第二閘極電極層以形成一第二閘極堆疊結構。
本發明還提供一種半導體結構的製造方法，包括下列步驟。提供一矽基底。於該矽基底上磊晶形成一第一矽鍺材料層。於該第一矽鍺材料層上磊晶形成一矽材料層。移除該矽材料層。於該第一矽鍺材料層上磊晶形成一第二矽鍺材料層。於該矽材料層上形成一閘極介電層。以及圖案化該閘極介電層以形成一閘極介電結構。
另外，本發明提供一種半導體結構，包括一半導體基底，包含一第一區及一第二區。一第一MOS元件，包括：一第一矽鍺材料層，位於該半導體基底的該第一區 上；一矽材料層，位於該第一矽鍺材料層上；以及一第一閘極介電結構，位於該矽材料層上。以及一第二MOS元件，包括：一第二矽鍺材料層，位於該半導體基底的該第二區上；以及一第二閘極介電結構，位於該第二矽鍺材料層上；其中該第二MOS元件中的該第二矽鍺材料層及該第二閘極介電結構之間並不具有一大體上的純矽材料層。
本發明也提供一種半導體結構，包括一矽基底，包含一第一區及一第二區。一NMOS元件，包括：一第一矽鍺材料層，位於該矽基底的該第一區上；一矽材料層，位於該第一矽鍺材料層上，其中該矽材料層包含大體上的純矽；以及一第一閘極介電結構，位於該矽材料層上。以及一PMOS元件，包括：一第二矽鍺材料層，位於該矽基底的該第二區上，其中該第一矽鍺材料層及該第二矽鍺材料層具有相同的鍺原子百分比；一第三矽鍺材料層，位於該第二矽鍺材料層上；以及一第二閘極介電結構，位於該第三矽鍺材料層上。
本發明之實施例提供一種金氧半導體結構的製造方法。有關各實施例之製造方式和使用方式係如下所詳述，並伴隨圖示加以說明。其中，圖式和說明書中使用之相同的元件編號係表示相同或類似之元件。而在圖式中，為清楚和方便說明起見，有關實施例之形狀和厚度 或有不符實際之情形。而以下所描述者係特別針對本發明之裝置的各項元件或其整合加以說明，然而，值得注意的是，上述元件並不特別限定於所顯示或描述者，而是可以熟習此技藝之人士所得之的各種形式，此外，當一層材料層是位於另一材料層或基板之上時，其可以是直接位於其表面上或另外插入有其他中介層。
請參考第6圖，提供一半導體基底20。半導體基底20可以是一般使用的半導體材料及結構，例如塊矽(bulk silicon)、絕緣層上覆矽(silicon－on－insulator,SOI)及類似的結構。半導體基底20包含NMOS區100及PMOS區200。於半導體基底20上磊晶形成一矽鍺(silicon germanium,SiGe)材料層24。於一實施例中，矽鍺材料層24是在一腔室內以減壓化學氣相沉積法(reduced pressure chemical vapor deposition)形成。前驅物可包括例如矽烷(SiH4)的含矽氣體，及例如鍺烷(GeH4)的含鍺氣體。矽鍺材料層24的鍺原子百分比可介於約5至30百分比，或是其他的百分比。矽鍺材料層24的厚度可大於約50。然而，習知技藝人士應了解到，此說明書中對厚度或其他尺寸的描述僅只是舉例，其亦可隨著積體電路的尺寸大小作改變。
接著在矽鍺材料層24上磊晶形成一矽材料層26。於一較佳實施例中，矽材料層26可以純矽(pure silicon)或大體上的純矽(substantially pure silicon)材料所形成。於其他實施例中，矽材料層26可包含鍺元素。然而，矽層 26的鍺原子百分比明顯低於矽鍺材料層24的鍺原子百分比。具有較高鍺原子百分比的矽鍺材料層24會在矽材料層26內造成張應力(tensile stress)。矽材料層26的厚度可介於例如約50至約400。
請參考第7圖，形成淺溝槽隔離(shallow trench isolation,STI)區22。淺溝槽隔離區22可用以定義NMOS區100及PMOS區200的範圍。在其他實施例中，可在矽材料層26形成之前，或甚至在矽鍺材料層24形成之前，形成淺溝槽隔離區22。
第8圖顯示閘極介電層28、含金屬的材料層(metal－containing layer)30，及罩幕層32的形成。在一較佳實施例中，閘極介電層28是由具有例如大於約3.9之高介電係數(high dielectric constant)的材料所形成。高介電係數材料包括例如二氧化鉿(HfO2)、二氧化鋯(ZrO2)或氮氧化矽鉿(HfSiON)的金屬氧化物，例如鋯酸鉿(HfZrO)、鉭酸鉿(HfTaO)或鈦酸鉿(HfTaO)的金屬合金氧化物(metal alloy oxide)，及其組合。閘極介電層28較佳為例如鑭酸鉿(HfLaO)之含鑭的材料(lanthanum containing material)。使用含鑭的高介電係數材料有益於降低所形成NMOS元件的閘極功函數。在其他實施例中，閘極介電層28可以氧化矽形成。於一實施例中，閘極介電層28的厚度是介於約1 nm至約10 nm之間。可選擇性地在閘極介電層28下方形成一厚度小於約1 nm的薄界面氧化物(thin interfacial oxide)以提高載子移動率 (carrier mobility)。
含金屬的材料層30較佳具有適合形成NMOS元件的功函數。功函數較佳為介於約4.0 eV至約4.4 eV之間，更佳為一導帶邊緣功函數(conduction band－edge work function)(接近矽材料的導帶，約4.1 eV)。可能的材料包含例如碳化鉭(TaC)、氮化鉭(TaN)、氮矽鉭化合物(TaSiN)及其組合的含鉭材料(tantalum－containing material)。含金屬的材料層30的厚度可介於約8 nm至約100 nm之間。閘極介電層28及含金屬的材料層30的形成方法包括低壓化學氣相沉積法(low－pressure chemical vapor deposition,LPCVD)、電漿增強化學氣相沉積法(plasma enhanced chemical vapor deposition,PECVD)、原子層沉積法(atomic layer deposition,ALD)、物理氣相沉積法(physical vapor deposition,PVD)、有機金屬化學氣相沉積法(metal－organic chemical vapor deposition,MOCVD)及類似的方法。硬罩幕32可由氮化矽(silicon nitride)、氮氧化矽(silicon oxynitride)及類似的材料所形成。將硬罩幕32圖案化以移除其位於PMOS區200上方的部份。
第9圖繪示利用例如乾蝕刻的方式將含金屬的材料層30、閘極介電層28及矽材料層26自PMOS區200移除。硬罩幕層32保護NMOS區100內的含金屬的材料層30、閘極介電層28及矽材料層26不被蝕刻移除。
矽材料層26的蝕刻可能造成其下方之矽鍺材料層24的表面受到損壞，因此矽鍺材料層24的表面可能會變得 粗糙。此會造成所形成通道區(channel region)可能存在於矽鍺材料層24內之PMOS元件的電洞移動率(hole mobility)降低的不利效果。因此可利用例如選擇性磊晶成長法(selective eptiaxial growth,SEG)，在矽鍺材料層24上磊晶形成第二矽鍺材料層34。所形成的結構如第10圖所示。在一實施例中，矽鍺材料層34與矽鍺材料層24大體上具有相同的原子百分比(atomic percentage)。在其他實施例中，矽鍺材料層34的鍺原子百分比是介於約5百分比至約30百分比之間。矽鍺材料層34的鍺原子百分比以大於矽鍺材料層24的鍺原子百分比為較佳，以使矽鍺材料層34內的應力可為壓(compressive)應力，以更增強電洞移動率。在其他實施例中，矽鍺材料層34內的鍺百分比可低於，或等於矽鍺材料層24內的鍺百分比。在一實施例中，矽鍺材料層34的厚度介於約5至400之間。由於矽鍺材料層24可能會被過蝕刻(over－etching)，以及矽鍺材料層34的形成，矽鍺材料層34之頂表面36的高度可能高於、等於或低於NMOS區100內部份矽鍺材料層24之頂表面38的高度。垂直差距(vertical difference)DT的高度約為300。差距DT可為正值(表示頂表面36高於頂表面38)或負值(表示頂表面36低於頂表面38)。要注意的是，當矽鍺材料層24及矽鍺材料層34具有不同的鍺原子百分比時，矽鍺材料層24及矽鍺材料層34是可被辨別的。然而，當矽鍺材料層24及矽鍺材料層54具有相同的原子百分比時，矽 鍺材料層24及矽鍺材料層34可能是無法被辨別的。
第11圖顯示閘極介電層42、含金屬的材料層(metal－containing layer)44，及硬罩幕46的形成。閘極介電層42由高介電係數材料所形成為較佳。高介電係數材料可包含例如鋁酸鉿(HfAlO)、氮氧化鋁鉿(HfAlON)、鋁酸鉿(AlZrO)及類似之含鋁的介電材料(aluminum－containing dielectric)。也可使用例如含鉿的材料(Hf－containing material)的其他高介電係數材料。使用含鋁的高介電係數材料有益於降低所形成之PMOS元件的臨界電壓(threshold voltage)。此外，在閘極介電層42中的鋁元素能夠抑制其下方之矽鍺材料層24及34中的鍺元素擴散至閘極介電層42內。因此所形成之PMOS元件的漏電流能夠被降低。在其他實施例中，閘極介電層42是由氧化矽(silicon oxide)所形成。閘極介電層42的厚度可介於約1 nm及10 nm之間。同樣的，也可選擇性地在閘極介電層42下方形成一厚度小於約1 nm的薄界面氧化物(thin interfacial oxide)以提高載子移動率(carrier mobility)。
含金屬的材料層44較佳具有適合形成PMOS元件的功函數。含金屬的材料層44具有介於約4.9 eV及約5.2 eV之間的功函數為較佳，更佳為接近約5.2 eV的導帶邊緣功函數(conduction band－edge work function)。材料可包含例如鎢(tungsten)或氮化鎢(tungsten mitride)之含鎢的材料(tungsten－containing meterial)，例如釕(ruthemium) 或氧化釕(ruthemium oxide)之含釕的材料(ruthemium－containing meterial)，例如鉬(molybdenum)或氮化鉬(molybdenum mitride)之含鉬的材料(molybdenum－containing meterial)，或上述材料之組合。閘極介電層42及含金屬的材料層44可分別使用與閘極介電層28及含金屬的材料層30相同的形成方法形成。接著可使用與硬罩幕32相同的材料形成硬罩幕層46。
第12圖繪示將閘極介電層42、含金屬的材料層44及硬罩幕層46進行圖案化以自NMOS區100移除。接著再進行一閘極圖案化步驟，以形成如第13圖所繪示的閘極堆疊結構150及250。因此，閘極介電層152及閘極電極層154形成於NMOS區100內，閘極介電層252及閘極電極層254形成於PMOS區200內。在其他實施例中，閘極堆疊結構250不必經過第12圖所繪示的步驟，而可由第11圖中的結構直接形成。
第14圖顯示NMOS元件160及PMOS元件260中其他元件的形成。首先形成輕摻雜源極/汲極(lightly doped source/drain)區162及262。輕摻雜源極/汲極區162及262可利用習知技藝，分別在NMOS區100及PMOS區200中摻雜N型雜質及P型雜質的方式形成。由於閘極堆疊結構150及250可在摻雜步驟中作遮蔽用，因此輕摻雜源極/汲極區162及262實質上是各自對準於閘極堆疊結構150及250的邊緣。
閘極間隙壁164及264分別形成於閘極堆疊結構150 及250的側壁上。可利用沉積一或多層間隙壁層(未顯示於圖中)，並以蝕刻的方式將間隙壁層水平的部分移除，以形成閘極間隙壁164及264。在較佳實施例中，間隙壁層包括在襯氧化層(liner oxide layer)上的氮化層。沉積間隙壁的較佳方式包括PECVD、LPCVD、次大氣壓化學氣相沉積(sub－atmospheric chemical vapor deposition,SACVD)及類似的方法。
第14圖也顯示深源極/汲極區166及266，以及矽鍺應力源(SiGe stressor)268的形成。由於深源極/汲極區166及266，以及矽鍺應力源(SiGe stressor)268可利用習知方式予以形成，因此不再詳述其形成步驟。接著形成源極/汲極矽化物區(source/drain silicide region)(未顯示於圖中)。
本發明的實施例具有一些優點特徵。由於NMOS元件160是形成於矽材料層上，且矽材料層是形成於矽鍺材料層上，因此矽材料層與矽鍺材料層之間的晶格差異(lattice mismatch)所形成的應力(strain)可增進通道區內的電子移動率。另外，由於PMOS元件是形成於矽鍺材料層上，因此PMOS元件的臨界電壓(threshold voltage)可被降低。再者，將鋁元素摻雜至PMOS元件260的閘極介電層中可抑制鍺元素擴散至上方的閘極介電層內，因此PMOS元件的漏電流能夠被降低。
雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何熟悉此項技藝者，在不脫離本發明之精 神和範圍內，當可做些許更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
2‧‧‧矽基底
4‧‧‧NMOS區
6‧‧‧PMOS區
7‧‧‧凹處
8‧‧‧閘極介電層
10‧‧‧N型金屬層
12‧‧‧硬罩幕
14‧‧‧矽鍺材料層
16‧‧‧閘極介電層
18‧‧‧P型金屬層
19‧‧‧硬罩幕
20‧‧‧半導體基底
22‧‧‧淺溝槽隔離區
24‧‧‧矽鍺材料層
26‧‧‧矽材料層
28‧‧‧閘極介電層
30‧‧‧含金屬的材料層
32‧‧‧罩幕層
34‧‧‧矽鍺材料層
36‧‧‧頂表面
38‧‧‧頂表面
42‧‧‧閘極介電層
44‧‧‧含金屬的材料層
46‧‧‧硬罩幕
100‧‧‧NMOS區
150‧‧‧閘極堆疊結構
152‧‧‧閘極介電層
154‧‧‧閘極電極層
160‧‧‧NMOS元件
162‧‧‧輕摻雜源極/汲極區
164‧‧‧閘極間隙壁
166‧‧‧深源極/汲極區
200‧‧‧PMOS區
250‧‧‧閘極堆疊結構
252‧‧‧閘極介電層
254‧‧‧閘極電極層
260‧‧‧PMOS元件
262‧‧‧輕摻雜源極/汲極區
264‧‧‧閘極間隙壁
266‧‧‧深源極/汲極區
268‧‧‧矽鍺壓力區
第1圖至第5圖繪示習知互補式MOS裝置的製程剖面圖。
第6圖至第14圖繪示本發明實施例的製程剖面圖。
20‧‧‧半導體基底
22‧‧‧淺溝槽隔離區
24‧‧‧矽鍺材料層
26‧‧‧矽材料層
34‧‧‧矽鍺材料層
100‧‧‧NMOS區
150‧‧‧閘極堆疊結構
152‧‧‧閘極介電層
154‧‧‧閘極電極層
160‧‧‧NMOS元件
162‧‧‧輕摻雜源極/汲極區
164‧‧‧閘極間隙壁
166‧‧‧深源極/汲極區
200‧‧‧PMOS區
250‧‧‧閘極堆疊結構
252‧‧‧閘極介電層
254‧‧‧閘極電極層
260‧‧‧PMOS元件
262‧‧‧輕摻雜源極/汲極區
264‧‧‧閘極間隙壁
266‧‧‧深源極/汲極區
268‧‧‧矽鍺壓力區

Claims (30)

  1. 一種半導體結構的製造方法，包括下列步驟：提供一半導體基底，該半導體基底包含一第一區及一第二區；形成一第一MOS元件，包括：於該半導體基底的該第一區上形成一第一矽鍺材料層；於該第一矽鍺材料層上形成一矽材料層；於該矽材料層上形成一第一閘極介電層，其中該第一閘極介電層包含鑭元素且不包含鋁元素；以及圖案化該第一閘極介電層以形成一第一閘極介電結構；以及形成一第二MOS元件，包括：於該半導體基底的該第二區上形成一第二矽鍺材料層；於該第二矽鍺材料層上形成一第二閘極介電層，其中該第二MOS元件中的該第二矽鍺材料層及該第二閘極介電層之間並不具有一大體上的純矽材料層，其中該第二閘極介電層包含鋁元素且不包含鑭元素；以及圖案化該第二閘極介電層以形成一第二閘極介電結構。
  2. 如申請專利範圍第1項所述之半導體結構的製造方法，其中該第一MOS元件是一NMOS元件，該第二MOS元件是一PMOS元件。
  3. 如申請專利範圍第1項所述之半導體結構的製造方法，其中該第一矽鍺材料層、該第二矽鍺材料層及該矽材料層是以磊晶成長的方式形成。
  4. 如申請專利範圍第1項所述之半導體結構的製造方法，更包括在形成該第二閘極介電層前，於該第二矽鍺材料層上形成一第三矽鍺材料層。
  5. 如申請專利範圍第1項所述之半導體結構的製造方法，其中該第一矽鍺材料層及該第二矽鍺材料層是同時形成。
  6. 如申請專利範圍第1項所述之半導體結構的製造方法，其中該矽材料層延伸於該半導體基底的該第二區上，且該方法更包括移除該第二區上的該矽材料層。
  7. 如申請專利範圍第6項所述之半導體結構的製造方法，更包括：於該第一閘極介電層上形成一第一閘極電極層；以及在移除該第二區上的該矽材料層後，於該第二閘極介電層上形成一第二閘極電極層。
  8. 如申請專利範圍第1項所述之半導體結構的製造方法，其中該半導體基底是矽基底。
  9. 一種半導體結構的製造方法，包括下列步驟：提供一矽基底，該矽基底包含一NMOS區及一PMOS區；於該矽基底上磊晶形成一第一矽鍺材料層，其中該 第一矽鍺材料層包括位於該NMOS區上的一第一部分，及位於該PMOS區上的一第二部分；於該第一矽鍺材料層上磊晶形成一矽材料層；於該矽材料層上形成一第一閘極介電層；於該第一閘極介電層上形成一第一閘極電極層；移除該PMOS區上的該第一閘極電極層、該第一閘極介電層及該矽材料層；形成一第二閘極介電層，其中該第二閘極介電層包括至少一部分是位於該第一矽鍺材料層的該第二部分上；於該第二閘極介電層上形成一第二閘極電極層；圖案化該第一閘極介電層及該第一閘極電極層以形成一第一閘極堆疊結構；以及圖案化該第二閘極介電層及該第二閘極電極層以形成一第二閘極堆疊結構。
  10. 如申請專利範圍第9項所述之半導體結構的製造方法，其中形成該第二閘極電極層及該第二閘極介電層的步驟包括：毯覆性地形成該第二閘極介電層；毯覆性地形成該第二閘極電極層；以及移除該NMOS區上的該第二閘極電極層及該第二閘極介電層。
  11. 如申請專利範圍第9項所述之半導體結構的製造方法，其中該第一閘極介電層包含鑭元素且不包含鋁元 素，該第二閘極介電層包含鋁元素且不包含鑭元素。
  12. 如申請專利範圍第9項所述之半導體結構的製造方法，更包括在移除該PMOS區上的該第一閘極電極層、該第一閘極介電層及該矽材料層後，磊晶形成一第二矽鍺材料層於該第一矽鍺材料層上，且該第二矽鍺材料層與該第一矽鍺材料層接觸。
  13. 一種半導體結構的製造方法，包括下列步驟：提供一矽基底；於該矽基底上磊晶形成一第一矽鍺材料層；於該第一矽鍺材料層上磊晶形成一矽材料層；移除該矽材料層；於該第一矽鍺材料層上磊晶形成一第二矽鍺材料層；於該矽材料層上形成一閘極介電層；以及圖案化該閘極介電層以形成一閘極介電結構。
  14. 如申請專利範圍第13項所述之半導體結構的製造方法，更包括：於該矽材料層上形成一額外的閘極介電層；於該額外的閘極介電層上形成一額外的閘極電極層；在移除該矽材料層前，移除該額外的閘極介電層及該額外的閘極電極層；於該閘極介電層上形成一閘極電極層；以及圖案化該閘極電極層以形成一閘極電極結構。
  15. 如申請專利範圍第13項所述之半導體結構的製造方法，其中該第二矽鍺材料層所具有的一第二鍺原子百分比，是不同於該第一矽鍺材料層的一第一鍺原子百分比。
  16. 如申請專利範圍第13項所述之半導體結構的製造方法，其中該閘極介電層包含鋁元素。
  17. 一種半導體結構，包括：一半導體基底，包含一第一區及一第二區；一第一MOS元件，包括：一第一矽鍺材料層，位於該半導體基底的該第一區上；一矽材料層，位於該第一矽鍺材料層上；以及一第一閘極介電結構，位於該矽材料層上，其中該第一閘極介電結構包含鑭元素；以及一第二MOS元件，包括：一第二矽鍺材料層，位於該半導體基底的該第二區上；以及一第二閘極介電結構，位於該第二矽鍺材料層上，其中該第二閘極介電結構包含鋁元素；其中該第二MOS元件中的該第二矽鍺材料層及該第二閘極介電結構之間並不具有一大體上的純矽材料層。
  18. 如申請專利範圍第17項所述的半導體結構，其中該第二MOS元件更包括一第三矽鍺材料層，位於該第二矽鍺材料層及該第二閘極介電結構之間，其中該第三矽 鍺材料層的鍺原子百分比不同於該第二矽鍺材料層的鍺原子百分比。
  19. 如申請專利範圍第17項所述的半導體結構，其中該第二矽鍺材料層的頂表面低於該第一矽鍺材料層的頂表面。
  20. 如申請專利範圍第17項所述的半導體結構，其中該第一MOS元件是一NMOS元件，該第二MOS元件是一PMOS元件。
  21. 如申請專利範圍第17項所述的半導體結構，其中該半導體基底是矽基底。
  22. 如申請專利範圍第17項所述的半導體結構，其中該第一矽鍺材料層及該第二矽鍺材料層具有相同的鍺原子百分比。
  23. 一種半導體結構，包括：一矽基底，包含一第一區及一第二區；一NMOS元件，包括：一第一矽鍺材料層，位於該矽基底的該第一區上；一矽材料層，位於該第一矽鍺材料層上，其中該矽材料層包含大體上的純矽；以及一第一閘極介電結構，位於該矽材料層上；以及一PMOS元件，包括：一第二矽鍺材料層，位於該矽基底的該第二區上，其中該第一矽鍺材料層及該第二矽鍺材料層具有相同的鍺原子百分比； 一第三矽鍺材料層，位於該第二矽鍺材料層上；以及一第二閘極介電結構，位於該第三矽鍺材料層上。
  24. 如申請專利範圍第23項所述的半導體結構，其中該第二矽鍺材料層與該第三矽鍺材料層具有不同的鍺原子百分比。
  25. 如申請專利範圍第24項所述的半導體結構，其中該第二矽鍺材料層與該第一矽鍺材料層具有不同的鍺原子百分比。
  26. 如申請專利範圍第23項所述的半導體結構，其中該第三矽鍺材料層的頂表面高於該第一矽鍺材料層的頂表面。
  27. 如申請專利範圍第23項所述的半導體結構，其中該第三矽鍺材料層的頂表面高度等於該第一矽鍺材料層的頂表面高度。
  28. 如申請專利範圍第23項所述的半導體結構，其中該第三矽鍺材料層的頂表面低於該第一矽鍺材料層的頂表面。
  29. 如申請專利範圍第23項所述的半導體結構，其中該第一閘極介電結構包含鑭元素且不包含鋁元素，該第二閘極介電結構包含鋁元素且不包含鑭元素。
  30. 如申請專利範圍第23項所述的半導體結構，其中該PMOS元件中的該第二矽鍺材料層及該第二閘極介電結構之間並不具有一大體上的純矽材料層。
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