TWI428996B - 封裝結構及其製造方法 - Google Patents

封裝結構及其製造方法 Download PDF

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Publication number
TWI428996B
TWI428996B TW099100073A TW99100073A TWI428996B TW I428996 B TWI428996 B TW I428996B TW 099100073 A TW099100073 A TW 099100073A TW 99100073 A TW99100073 A TW 99100073A TW I428996 B TWI428996 B TW I428996B
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Taiwan
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layer
wafers
composite
gold
substrate layer
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TW099100073A
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TW201112338A (en
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Geng Shin Shen
Jun Yong Wang
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Chipmos Technologies Inc
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Description

封裝結構及其製造方法
本發明係關於一種封裝結構及其製造方法。更具體而言，本發明係關於一種具複合凸塊之封裝結構及一種以捲帶式傳輸(reel-to-reel)方式製造該封裝結構之方法，以便進行大規模生產。
在現代的先進半導體製造製程中，半導體裝置已於大規模生產中被最小化至奈米規模。適用於此等半導體裝置之奈米規模封裝技術亦已出現，用以適應不同產品之需求。於一晶圓(wafer)上完成一積體電路(integrated circuit；IC)之製作後，須將晶圓傳送至一封裝工廠以執行後續切割及封裝步驟。又，封裝製程之效率關乎生產成本及影響所封裝晶片之運作效能。因此，封裝結構及其材料選用變得更加重要。
傳統上，一晶片係電性連接且結合至一基材，此時晶片之各凸塊分別電性連接至基材之各接點。因為金具有良好導電性之優點，故傳統之凸塊係由金製成。而且，於傳統製程中，於晶片設置於基材上之後，尚需利用封膠材封裝該晶片。
由於金價格昂貴且分別以封膠材包覆各晶片之製程亦頗為複雜，故封裝結構之製造成本因而提高。因此，在本領域中仍需要開發一種新穎之封裝結構及其製造方法。
本發明之主要目的在於提供一種封裝結構以及其製造方法。該封裝結構包含由金/銅或金/鎳/銅製成之複合凸塊，其中金之厚度係小於該複合凸塊之總高度之一半。故可藉由減少金之使用，以降低製造成本。
本發明之另一目的在於提供一種封裝結構以及其製造方法。其包括：一捲筒狀之第一帶體上係設置有晶片；一捲筒狀之第二帶體上係大面積地預先形成複合樹脂至一支撐層上。接著，傳輸第一帶體及第二帶體並朝向一對滾輪輸送，以進行加熱並相互施加壓力，使第二帶體上之複合樹脂與第一帶體上之晶片結合。藉此，可簡化封裝結構之製程。
為達成上述目的，本發明之封裝結構包含一基材層、複數個晶片、一複合樹脂層以及一支撐層。該基材層上形成有一電路及一防焊層，該電路受防焊層覆蓋，並暴露出該電路之複數個接點。該等晶片結合至該基材層上。各該晶片具有複數個接墊、形成於該等接墊上之複數個凸塊下金屬層(under bump metal,UBM)以及設置於該等凸塊下金屬層上之複數個複合凸塊，其中該等複合凸塊係由金/銅、或金/鎳/銅所製成，且分別與該等接點電性連接。複合樹脂層形成於基材層上，用以封裝該等晶片。
本發明之另一封裝結構包含一基材層、一覆蓋層以及複數個晶片。基材層形成有一電路及防焊層，該電路受防焊層覆蓋，並暴露出電路之複數個接點。覆蓋層形成於該接點上，其中覆蓋層係由鎳/金或錫所製成。該等晶片結合至基材層上。各晶片具有複數個接墊、形成於該等接墊上之複數個凸塊下金屬層(under bump metal,UBM)以及設置於該等凸塊下金屬層上之複數個複合凸塊。該等複合凸塊係由金/銅、或金/鎳/銅所製成，分別與該等接點電性連接。該等凸塊下金屬層延伸且部分顯露以形成一測試墊。
本發明之另一目的在於提供一種製造一封裝結構之方法。而此方法包含下列步驟：提供一基材層，基材層形成有一電路及一防焊層，該電路受防焊層覆蓋並暴露出電路之複數個接點，；提供複數個晶片，各晶片具有複數個接墊及設置於該等接墊上之複數個複合凸塊；將該等晶片結合至該基材層上，以形成一第一帶體，其中，該等複合凸塊分別與該等接點電性連接；提供一支撐層，其具有塗覆於該支撐層上之一複合樹脂層以形成一第二帶體；分別將該第一帶體及該第二帶體形成一捲筒狀結構；將第一帶體及第二帶體展開且輸送至一對滾輪；將第二帶體進行預熱，以軟化其上之複合樹脂層；以及，對該第一帶體及該第二帶體進行加熱及加壓至攝氏100~250度，以使該等晶片埋覆於複合樹脂層內。
為讓上述目的、技術特徵、和優點能更明顯易懂，下文係以較佳實施例配合所附圖式進行詳細說明。
請參考第1A圖及第1B圖，第1A圖顯示用於製造封裝結構1之系統，而第1B圖繪示藉由切割封裝結構1所形成之一單元1’。於以下圖式中，將先詳細地揭露封裝結構1，而後再說明封裝結構1之製程。
如第1A圖及第1B圖所示，封裝結構1包含一基材層11、形成於基材層11上之一防焊層15、結合至基材層11上之複數個晶片12、形成於基材層11上用以封裝晶片12之一複合樹脂層13、以及覆蓋複合樹脂層13之一支撐層14。
基材層11包含電路(圖未示)及一防焊層15，其中該電路具有複數個接點111自防焊層15顯露出來。基材層11以及支撐層14可由聚醯亞胺(polyimide,PI)或聚對苯二甲酸乙二醇酯(polyethylene terephthalate,PET)所製成。請再參考第2A圖以及第2B圖，晶片12包含複數個接墊121、複數個凸塊下金屬層(under bump metal,UBM)122、以及複數個複合凸塊123。其中，凸塊下金屬層122係形成於接墊121上，且複合凸塊123接續分別設置於凸塊下金屬層122上。較佳地，各凸塊下金屬層122係延伸並部分顯露以形成一測試墊124。在本實施例中，如第2A圖所示，其特徵在於，複合凸塊123可由金/銅所製成。然而複合凸塊123亦可選擇由金/鎳/銅來製成，其中鎳係作為一屏障層並形成於金與銅之間，如第2B圖所示。應注意，複合凸塊123之金所形成之厚度係小於複合凸塊123之總高度之一半，藉以降低成本。如第2C圖所示，複合凸塊123之另一較佳實施例更包含由金所製成之一保護層125用以覆蓋凸塊123外緣。該等晶片12藉由該等複合凸塊以結合至基材層11，藉以分別電性連接至該等接點111。為增強導電性，由鎳/金或錫所製成之一覆蓋層113係形成於接點111上。
為防止濕氣滲透入封裝結構1中並影響導電性，封裝結構1更包含形成於晶片12與接點111間之非導電膠(non-conductive paste；NCP)112。此外，如第1C圖所示，封裝結構1可更包含複數個焊球16，設置於基材層11之一表面上且與該等晶片12相對。
以下，關於上述封裝結構1之製造方法之本發明另一實施例說明如下。請同時參見第3圖及第6A圖。在步驟601中，提供一基材層11，基材層11形成有一電路及一防焊層15，且電路受防焊層15覆蓋，並暴露出該電路之複數個接點111。較佳地，一覆蓋層113形成於接點111上，其中覆蓋層113可由鎳/金或錫來製成。接著，在步驟602中，施加一非導電膠(NCP)112至基材層11上，用以覆蓋該等接點111。如第1B至2C圖所示，在步驟603中，提供複數個晶片12，其中各晶片12具有複數個接墊121及設置於該等接墊121上之複數個複合凸塊123。於本實施例中，晶片12更包含一凸塊下金屬層(under bump metal；UBM)122覆蓋於接墊121上。類似於前述實施例，各複合凸塊123可由金/銅或金/鎳/銅所製成，其中金形成之厚度小於複合凸塊123之高度之一半，藉以降低成本。
在步驟604中，將該等晶片12結合至基材層11上，其中該等複合凸塊123分別與該等接點111電性連接。更具體而言，如第4圖所示，將該等晶片12結合至基材層11上之步驟係利用施加超音波於晶片12上，藉此使複合凸塊123穿過非導電膠112而與接點111電性連接。接著，在步驟605中，如第5A圖所示，固化非導電膠112以於第一帶體1a上形成乾膜狀。
接下來，請參考第5B圖，在步驟606中，提供一第二帶體1b，其具有一支撐層14及塗覆於支撐層14上之一複合樹脂層13。在步驟607中，分別將第一帶體1a及第二帶體1b形成捲筒狀結構2a及2b，以利於後續製程。
請參考第6B圖及第1圖，在步驟608中，將第一帶體1a及第二帶體1b展開且輸送至一對滾輪3。在步驟609中，可利用一預熱裝置4將第二帶體1b進行預熱，以軟化其上之複合樹脂層13。接著，執行步驟610，以該對滾輪3對第一帶體1a及第二帶體1b進行加熱及相互加壓，以使晶片12埋覆於複合樹脂層13內。較佳地，該對滾輪3可對第一帶體1a及第二帶體1b加熱至溫度約攝氏100~250度之間。接著，在步驟611中，利用一固化裝置5以固化第一帶體1a及第二帶體1b。於步驟611之後可進一步的移除支撐層14如步驟612所示。
最後，在步驟613中，將相結合之第一帶體1a與第二帶體1b切割成複數單元1’。請再參考第1C圖，在步驟614中，各單元1’中將複數個焊球16設置於相對於晶片12之基材層11之表面上。
綜上所述，由於金之使用量已最小化，故封裝結構中所用之複數個複合凸塊之製造成本可因此被降低。又，本發明以捲帶式傳輸(reel-to-reel)方式製造封裝結構之製程可運用於大規模生產中。
上述之實施例僅用來例舉本發明之實施態樣，以及闡釋本發明之技術特徵，並非用來限制本發明之保護範疇。任何熟悉此技術者可輕易完成之改變或均等性之安排均屬於本發明所主張之範圍，本發明之權利保護範圍應以申請專利範圍為準。
1．．．封裝結構
1’．．．單元
1a．．．第一帶體
1b．．．第二帶體
2a．．．捲筒狀結構
2b．．．捲筒狀結構
3．．．滾輪
4．．．預熱裝置
5．．．固化裝置
11．．．基材層
12．．．晶片
13．．．複合樹脂層
14．．．支撐層
15．．．防焊層
16．．．焊球
111．．．接點
112．．．非導電膠
113．．．覆蓋層
121．．．接墊
122．．．凸塊下金屬層
123．．．複合凸塊
124．．．測試墊
125．．．保護層
第1A圖係為本發明之封裝結構之製造系統之示意圖；
第1B圖係為經剖切封裝結構形成一單元之示意圖；
第1C圖係為顯示具有焊球之單元之示意圖；
第2A至2C圖係為複合凸塊之各種實施例之示意圖；
第3圖係為施加非導電膠於基材層上之步驟之示意圖；
第4圖係為施加超音波至晶片上之步驟之示意圖；
第5A圖係為第一帶體之示意圖；
第5B圖係為第二帶體之示意圖；以及
第6A至6B圖係為本發明封裝結構製造方法之流程圖。
1．．．封裝結構
1’．．．單元
1a．．．第一帶體
1b．．．第二帶體
2a．．．捲筒狀結構
2b．．．捲筒狀結構
3．．．對滾輪
4．．．預熱裝置
5．．．固化裝置
11．．．基材層
12．．．晶片
13．．．複合樹脂層
14．．．支撐層
15．．．防焊層

Claims (24)

  1. 一種製造一封裝結構之方法，包含下列步驟：提供一基材層，該基材層上形成有一電路及一防焊層，該電路受該防焊層覆蓋並暴露出該電路之複數個接點；提供複數個晶片，各該晶片具有複數個接墊及設置於該等接墊上之複數個複合凸塊；將該等晶片結合至該基材層上，以形成一第一帶體，其中，該等複合凸塊分別與該等接點電性連接；提供一第二帶體，其具有一支撐層以及塗覆於該支撐層上之一複合樹脂層；分別將該第一帶體以及該第二帶體形成一捲筒狀結構；將該第一帶體及該第二帶體展開且輸送至一對滾輪；將該第二帶體進行預熱，以軟化其上之該複合樹脂層；以該對滾輪對該第一帶體及該第二帶體進行加熱以及加壓，至攝氏100~250度，以使該等晶片埋覆於該複合樹脂層內。
  2. 如請求項1所述之方法，於該提供一基材層之步驟後，更包含一步驟：施加一非導電膠(non-conductive paste,NCP)於該基材層上，以覆蓋該等接點。
  3. 如請求項2所述之方法，其中該將該等晶片結合至該基材層上之步驟，係施加超音波於該等晶片上，以使該等複合凸塊穿過該非導電膠，與該等接點電性連接。
  4. 如請求項3所述之方法，於該施加超音波於該等晶片上之步驟後，更包含一步驟：固化該非導電膠。
  5. 如請求項4所述之方法，在對該第一帶體及該第二帶體進行 加熱及加壓之步驟後，更包含一步驟：固化該第一帶體及該第二帶體。
  6. 如請求項5所述之方法，在固化該第一帶體及該第二帶體之步驟之後，更包含下列步驟；移除該支撐層；切割該第一帶體及該第二帶體以形成複數個單元；以及於各該單元中，在該基材層上且與該等晶片之相對之面上，設置複數個焊球。
  7. 如請求項1所述之方法，其中該提供複數個晶片之步驟，更包含一步驟：形成一凸塊下金屬層(under bump metal,UBM)覆蓋於該接墊上。
  8. 如請求項1所述之方法，其中該等複合凸塊係由金/銅、或金/鎳/銅所製成。
  9. 如請求項8所述之方法，其中該複合凸塊之金形成一厚度，該厚度係小於該複合凸塊之高度的一半。
  10. 如請求項1所述之方法，其中該提供一基材層之步驟，更包含一步驟：形成一覆蓋層於該接點上，其中該覆蓋層係由鎳/金、或錫所製成。
  11. 如請求項1所述之方法，其中各該基材層及該支撐層，係由聚醯亞胺(polyimide,PI)或聚對苯二甲酸乙二醇酯(polyethylene terephthalate,PET)所製成。
  12. 一封裝結構，包含：一基材層，該基材層形成有一電路及一防焊層，該電路受該防焊層覆蓋並暴露出該電路之複數個接點；複數個晶片，結合至該基材層上，其中各該晶片具有複 數個接墊、形成於該等接墊上之複數個凸塊下金屬層(under bump metal,UBM)以及設置於該等凸塊下金屬層上之複數個複合凸塊，其中該等複合凸塊係由金/銅、或金/鎳/銅所製成，分別與該等接點電性連接；一複合樹脂層，形成於該基材層上，以封裝該等晶片；以及複數個非導電膠(non-conductive paste,NCP)，分別形成於該等晶片與該等接點之間。
  13. 如請求項12所述之封裝結構，更包含複數個焊球，設置於該基材層上與該等晶片相對之面上。
  14. 如請求項12所述之封裝結構，其中該凸塊下金屬層延伸且部分顯露以形成一測試墊。
  15. 如請求項12所述之封裝結構，其中各該複合凸塊外緣係由一金層所包覆。
  16. 如請求項12所述之封裝結構，其中該複合凸塊之金形成一厚度，該厚度係小於該複合凸塊之高度的一半。
  17. 如請求項12所述之封裝結構，更包含一覆蓋層，形成於該接點上，其中該覆蓋層係由鎳/金、或錫所製成。
  18. 如請求項12所述之封裝結構，其中該基材層係由聚醯亞胺(polyimide,PI)或聚對苯二甲酸乙二醇酯(polyethylene terephthalate,PET)所製成。
  19. 一封裝結構，包含：一基材層，該基材層形成有一電路及一防焊層，該電路受該防焊層覆蓋並暴露出該電路之複數個接點；一覆蓋層，形成於該接點上，該覆蓋層係由鎳/金、或錫 所製成；以及複數個晶片，結合至該基材層上，其中各該晶片具有複數個接墊、形成於該等接墊上之複數個凸塊下金屬層(under bump metal,UBM)以及設置於該等凸塊下金屬層上之複數個複合凸塊，其中該等複合凸塊係由金/銅、或金/鎳/銅所製成，分別與該等接點電性連接，且該等凸塊下金屬層延伸且部分顯露以形成一測試墊。
  20. 如請求項19所述之封裝結構，更包含複數個非導電膠(non-conductive paste,NCP)，分別形成於該等晶片與該等接點之間。
  21. 如請求項19所述之封裝結構，更包含複數個焊球，設置於該基材層上且與該等晶片相對之面上。
  22. 如請求項19所述之封裝結構，各該複合凸塊外緣係由一金層所包覆。
  23. 如請求項19所述之封裝結構，其中該複合凸塊之金形成一厚度，該厚度係小於該複合凸塊之一高度的一半。
  24. 如請求項19所述之封裝結構，其中該基材層係由聚醯亞胺(polyimide,PI)或聚對苯二甲酸乙二醇酯(polyethylene terephthalate,PET)所製成。
TW099100073A 2009-09-23 2010-01-05 封裝結構及其製造方法 TWI428996B (zh)

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US7569250B2 (en) * 2004-05-17 2009-08-04 Hewlett-Packard Development Company, L.P. Method, system, and apparatus for protective coating a flexible circuit
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