CN102024712B - 封装结构及其制造方法 - Google Patents

封装结构及其制造方法 Download PDF

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CN102024712B
CN102024712B CN201010128175.2A CN201010128175A CN102024712B CN 102024712 B CN102024712 B CN 102024712B CN 201010128175 A CN201010128175 A CN 201010128175A CN 102024712 B CN102024712 B CN 102024712B
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layer
belt body
chips
gold
composite
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CN102024712A (zh
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沈更新
王骏泳
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Chipmos Technologies Inc
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Chipmos Technologies Inc
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Abstract

本发明是关于一种封装结构以及其制造方法。该封装结构包含一基材层、多个芯片、一复合树脂层以及一支撑层。该基材层形成有一电路，该电路具有多个接点，自一防焊层显露出来。这些芯片结合至该基材层上，以形成一第一带体。其中，各该芯片具有多个接垫、形成于这些接垫上的多个凸块下金属层以及设置于这些凸块下金属层上的多个复合凸块。该第二带体包含支撑层及形成于支撑层上的复合树脂层。又第一带体与第二带体皆为卷带结构受滚轮传动展开，以于被加热和加压后封装这些芯片。本发明的优点是：可通过减少金的使用，以降低制造成本；其工艺可运用于大规模生产中。

Description

封装结构及其制造方法
技术领域
本发明是关于一种封装结构及其制造方法。更具体而言，本发明是关于一种具复合凸块的封装结构及一种以卷带式传输(reel-to-reel)方式制造该封装结构的方法，以便进行大规模生产。
背景技术
在现代的先进半导体制造工艺中，半导体装置已于大规模生产中被最小化至纳米规模。适用于这种半导体装置的纳米规模封装技术亦已出现，用以适应不同产品的需求。于一晶片(wafer)上完成一集成电路(integrated circuit；IC)的制作后，须将晶片传送至一封装工厂以执行后续切割及封装步骤。又封装工序的效率关乎生产成本及影响所封装芯片的运作效能。因此，封装结构及其材料选用变得更加重要。
传统上，一芯片是电性连接且结合至一基材，此时芯片的各凸块分别电性连接至基材的各接点。因为金具有良好导电性的优点，故传统的凸块是由金制成。而且，于传统工艺中，于芯片设置于基材上之后，尚需利用封胶材封装该芯片。
由于金价格昂贵且分别以封胶材包覆各芯片的工艺亦颇为复杂，故封装结构的制造成本因而提高。因此，在本领域中仍需要开发一种新颖的封装结构及其制造方法。
发明内容
本发明的主要目的在于提供一种封装结构以及其制造方法，可通过减少金的使用和简化封装结构的工艺，以降低制造成本。
根据本发明一方面提供一种制造封装结构的方法，其特征在于，包含下列步骤：提供一基材层，该基材层上形成有一电路及一防焊层，该电路受该防焊层覆盖并暴露出该电路的多个接点；提供多个芯片，各该芯片具有多个接垫及设置于这些接垫上的多个复合凸块；将这些芯片结合至该基材层上，以形成一第一带体，其中，这些复合凸块分别与这些接点电性连接；提供一第二带体，其具有一支撑层以及涂覆于该支撑层上的一复合树脂层；分别将该第一带体以及该第二带体形成一卷筒状结构；将该第一带体及该第二带体展开且输送至一对滚轮；将该第二带体进行预热，以软化其上的该复合树脂层；以该对滚轮对该第一带体及该第二带体进行加热以及加压，至摄氏100～250度，以使这些芯片埋覆于该复合树脂层内。
根据本发明另一方面提供一种封装结构，其特征在于，包含：一基材层，该基材层形成有一电路及一防焊层，该电路受该防焊层覆盖并暴露出该电路的多个接点；多个芯片，结合至该基材层上，其中各该芯片具有多个接垫、形成于这些接垫上的多个凸块下金属层(under bump metal，UBM)以及设置于这些凸块下金属层上的多个复合凸块，其中这些复合凸块是由金/铜、或金/镍/铜所制成，分别与这些接点电性连接；一复合树脂层，形成于该基材层上，以封装这些芯片。
根据本发明又一方面提供一种一种封装结构，其特征在于，包含：一基材层，该基材层形成有一电路及一防焊层，该电路受该防焊层覆盖并暴露出该电路的多个接点；一覆盖层，形成于该接点上，该覆盖层是由镍/金、或锡所制成；以及多个芯片，结合至该基材层上，其中各该芯片具有多个接垫、形成于这些接垫上的多个凸块下金属层以及设置于这些凸块下金属层上的多个复合凸块，其中这些复合凸块是由金/铜、或金/镍/铜所制成，分别与这些接点电性连接，且这些凸块下金属层延伸且部分显露以形成一测试垫。
本发明的有益技术效果是：该封装结构包含由金/铜或金/镍/铜制成的复合凸块，其中金的厚度是小于该复合凸块的总高度的一半，故可通过减少金的使用，以降低制造成本；由于金的使用量已最小化，故封装结构中所用的多个复合凸块的制造成本可因此被降低；本发明以卷带式传输(reel-to-reel)方式制造封装结构的工艺可运用于大规模生产中。
附图说明
为让上述目的、技术特征、和优点能更明显易懂，下面将结合附图对本发明的较佳实施例进行详细说明，其中：
图1A是本发明的封装结构的制造系统的示意图；
图1B是经剖切封装结构形成一单元的示意图；
图1C是显示具有焊球的单元的示意图；
图2A至图2C是复合凸块的各种实施例的示意图；
图3是施加非导电胶于基材层上的步骤的示意图；
图4是施加超声波至芯片上的步骤的示意图；
图5A是第一带体的示意图；
图5B是第二带体的示意图；以及
图6A至图6B是本发明封装结构制造方法的流程图。
具体实施方式
请参考图1A及图1B，图1A显示用于制造封装结构1的系统，而图1B绘示通过切割封装结构1所形成的一单元1’。于以下附图中，将先详细地揭露封装结构1，而后再说明封装结构1的制作工艺。
如图1A及图1B所示，封装结构1包含一基材层11、形成于基材层11上的一防焊层15、结合至基材层11上的多个芯片12、形成于基材层11上用以封装芯片12的一复合树脂层13、以及覆盖复合树脂层13的一支撑层14。
基材层11包含电路(图未示)及一防焊层15，其中该电路具有多个接点111自防焊层15显露出来。基材层11以及支撑层14可由聚酰亚胺(polyimide，PI)或聚对苯二甲酸乙二醇酯(polyethylene terephthalate，PET)所制成。请再参考图2A以及图2B，芯片12包含多个接垫121、多个凸块下金属层(under bump metal，UBM)122、以及多个复合凸块123。其中，凸块下金属层122形成于接垫121上，且复合凸块123接续分别设置于凸块下金属层122上。较佳地，各凸块下金属层122是延伸并部分显露以形成一测试垫124。在本实施例中，如图2A所示，其特征在于，复合凸块123可由金/铜所制成。然而复合凸块123亦可选择由金/镍/铜来制成，其中镍是作为一屏障层并形成于金与铜之间，如图2B所示。应注意，复合凸块123的金所形成的厚度是小于复合凸块123的总高度的一半，藉以降低成本。如图2C所示，复合凸块123的另一较佳实施例还包含由金所制成的一保护层125用以覆盖凸块123外缘。这些芯片12通过这些复合凸块以结合至基材层11，藉以分别电性连接至这些接点111。为增强导电性，由镍/金或锡所制成的一覆盖层113形成于接点111上。
为防止湿气渗透入封装结构1中并影响导电性，封装结构1还包含形成于芯片12与接点111间的非导电胶(non-conductive paste；NCP)112。此外，如图1C所示，封装结构1可还包含多个焊球16，设置于基材层11的一表面上且与这些芯片12相对。
以下，关于上述封装结构1的制造方法的本发明另一实施例说明如下。请同时参见图3及图6A。在步骤601中，提供一基材层11，基材层11形成有一电路及一防焊层15，且电路受防焊层15覆盖，并暴露出该电路的多个接点111。较佳地，一覆盖层113形成于接点111上，其中覆盖层113可由镍/金或锡来制成。接着，在步骤602中，施加一非导电胶(NCP)112至基材层11上，用以覆盖这些接点111。如图1B至图2C所示，在步骤603中，提供多个芯片12，其中各芯片12具有多个接垫121及设置于这些接垫121上的多个复合凸块123。于本实施例中，芯片12还包含一凸块下金属层(under bump metal；UBM)122覆盖于接垫121上。类似于前述实施例，各复合凸块123可由金/铜或金/镍/铜所制成，其中金形成的厚度小于复合凸块123的高度的一半，藉以降低成本。
在步骤604中，将这些芯片12结合至基材层11上，其中这些复合凸块123分别与这些接点111电性连接。更具体而言，如图4所示，将这些芯片12结合至基材层11上的步骤是利用施加超声波于芯片12上，藉此使复合凸块123穿过非导电胶112而与接点111电性连接。接着，在步骤605中，如图5A所示，固化非导电胶112以于第一带体1a上形成干膜状。
接下来，请参考图5B，在步骤606中，提供一第二带体1b，其具有一支撑层14及涂覆于支撑层14上的一复合树脂层13。在步骤607中，分别将第一带体1a及第二带体1b形成卷筒状结构2a及2b，以利于后续工序。
请参考图6B及图1A至图1C，在步骤608中，将第一带体1a及第二带体1b展开且输送至一对滚轮3。在步骤609中，可利用一预热装置4将第二带体1b进行预热，以软化其上的复合树脂层13。接着，执行步骤610，以该对滚轮3对第一带体1a及第二带体1b进行加热及相互加压，以使芯片12埋覆于复合树脂层13内。较佳地，该对滚轮3可对第一带体1a及第二带体1b加热至温度约摄氏100～250度之间。接着，在步骤611中，利用一固化装置5以固化第一带体1a及第二带体1b。于步骤611之后可进一步的移除支撑层14如步骤612所示。
最后，在步骤613中，将相结合的第一带体1a与第二带体1b切割成多个单元1’。请再参考图1C，在步骤614中，各单元1’中将多个焊球16设置于相对于芯片12的基材层11的表面上。
综上所述，由于金的使用量已最小化，故封装结构中所用的多个复合凸块的制造成本可因此被降低。又本发明以卷带式传输(reel-to-reel)方式制造封装结构的工艺可运用于大规模生产中。
上述的实施例仅用来例举本发明的实施态样，以及阐释本发明的技术特征，并非用来限制本发明的保护范畴。任何熟悉此技术者可轻易完成的改变或均等性的安排均属于本发明所主张的范围，本发明的权利保护范围应以申请专利范围为准。

Claims (12)

1.一种制造封装结构的方法，其特征在于，包含下列步骤：
提供一基材层，该基材层上形成有一电路及一防焊层，该电路受该防焊层覆盖并暴露出该电路的多个接点；
提供多个芯片，各该芯片具有多个接垫及设置于这些接垫上的多个复合凸块，这些复合凸块是由金层及铜层所制成、或由金层、镍层及铜层所制成，且该复合凸块中的金所形成的一厚度是小于该复合凸块的总高度的一半；
将这些芯片结合至该基材层上，以形成一第一带体，其中，这些复合凸块分别与这些接点电性连接；
提供一第二带体，其具有一支撑层以及涂覆于该支撑层上的一复合树脂层；
分别将该第一带体以及该第二带体形成一卷筒状结构；
将该第一带体及该第二带体展开且输送至一对滚轮；
将该第二带体进行预热，以软化其上的该复合树脂层；
以该对滚轮对该第一带体及该第二带体进行加热以及加压，至摄氏100～250度，以使这些芯片埋覆于该复合树脂层内。
2.根据权利要求1所述的方法，其特征在于，于该提供一基材层的步骤后，还包含一步骤：施加一非导电胶于该基材层上，以覆盖这些接点。
3.根据权利要求2所述的方法，其特征在于，该将这些芯片结合至该基材层上的步骤，是施加超声波于这些芯片上，以使这些复合凸块穿过该非导电胶，与这些接点电性连接，以及于该施加超声波于这些芯片上的步骤后，还包含一步骤：固化该非导电胶。
4.根据权利要求3所述的方法，其特征在于，在对该第一带体及该第二带体进行加热及加压的步骤后，还包含一步骤：固化该第一带体及该第二带体。
5.根据权利要求4所述的方法，其特征在于，在固化该第一带体及该第二带体的步骤之后，还包含下列步骤；
移除该支撑层；
切割该第一带体及该第二带体以形成多个单元；以及
于各该单元中，在该基材层上且与这些芯片的相对的面上，设置多个焊球。
6.根据权利要求1所述的方法，其特征在于，该提供多个芯片的步骤，还包含一步骤：形成一凸块下金属层覆盖于该接垫上。
7.根据权利要求1所述的方法，其特征在于，该提供一基材层的步骤，还包含一步骤：形成一覆盖层于该接点上，其中该覆盖层是由镍层及金层所制成、或由锡层所制成。
8.一种封装结构，其特征在于，包含：
一基材层，该基材层形成有一电路及一防焊层，该电路受该防焊层覆盖并暴露出该电路的多个接点；
多个芯片，结合至该基材层上，其中各该芯片具有多个接垫、形成于这些接垫上的多个凸块下金属层以及设置于这些凸块下金属层上的多个复合凸块，其中这些复合凸块是由金层及铜层、或金层、镍层及铜层所制成，分别与这些接点电性连接且该复合凸块的金形成一厚度，该厚度是小于该复合凸块的高度的一半；
一复合树脂层，形成于该基材层上，以封装这些芯片。
9.根据权利要求8所述的封装结构，其特征在于，还包含多个非导电胶，分别形成于这些芯片与这些接点之间。
10.根据权利要求8所述的封装结构，其特征在于，该凸块下金属层延伸且部分显露以形成一测试垫。
11.根据权利要求8所述的封装结构，其特征在于，各该复合凸块外缘是由一金层所包覆。
12.根据权利要求8所述的封装结构，其特征在于，还包含一覆盖层，形成于该接点上，其中该覆盖层是由镍层及金层所制成、或由锡层所制成。
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