TWI424491B - 無限選擇性光阻遮罩蝕刻 - Google Patents

無限選擇性光阻遮罩蝕刻 Download PDF

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TWI424491B
TWI424491B TW096104475A TW96104475A TWI424491B TW I424491 B TWI424491 B TW I424491B TW 096104475 A TW096104475 A TW 096104475A TW 96104475 A TW96104475 A TW 96104475A TW I424491 B TWI424491 B TW I424491B
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etch
providing
features
sidewalls
deposition
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TW200735210A (en
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Ji Soo Kim
Peter Cirigliano
Sangheon Lee
Dongho Heo
Daehan Choi
S M Reza Sadjadi
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Lam Res Corp
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    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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Description

無限選擇性光阻遮罩蝕刻
本發明係關於半導體裝置的形成;比較明確地,本發明係關於藉由在一蝕刻層內蝕刻特徵以形成半導體裝置。
在半導體晶圓處理的過程中,半導體裝置的特徵是由熟知的印製圖樣和蝕刻步驟在該晶圓上界定。這些步驟中,在該晶圓上沉積一光阻(PR)材料,然後曝露在經由一主光罩所過濾的光。該主光罩可以是印製有範例幾何特徵的一玻璃板,其阻擋光無法通過該主光罩。
通過該主光罩之後,該光接觸到該光阻材料的表面,並且改變了該光阻材料的化學組成,使得一顯影劑能夠移除一部分的該光阻材料。於正光阻材料的情況,將曝光的區域移除;而負光阻材料的情況,則將未曝光的區域移除。在此之後,蝕刻晶圓以移除將不再受到該光阻材料保護的區域之下層材料,因此把想要的特徵界定在該晶圓上。
製造以半導體為基的裝置(即積體電路或平面顯示器)的過程中,雙重鑲嵌結構可以用於連接銅質導體材料,以降低相關於訊號在上一代技術以鋁質為基材料中傳輸的RC延遲。於雙重鑲嵌,取代蝕刻導電材料而是可以在該介電質材料中蝕刻通道和溝渠,並且將銅填入其中。
通常在蝕刻下層材料的過程中會移除一些光阻材料,而被移除的下層材料量相對於被蝕刻的光阻之比值是用於決定蝕刻選擇性。
為能達到上述以及根據本發明之目的,提供一種用於將特徵蝕刻至配置在一光阻遮罩下方的一蝕刻層內而沒有一中間硬遮罩之方法;也提供複數個蝕刻循環。每個蝕刻循環包含提供一沉積蝕刻階段,其將特徵蝕刻至該蝕刻層內並且在該些特徵的側壁和該光阻上方沉積聚合物;也包含一清潔階段,將沉積在該側壁上的聚合物移除。
於本發明之另一方面,提供一種用於將特徵蝕刻至配置在一光阻遮罩下方的一蝕刻層內而沒有一中間硬遮罩之方法;也提供具有無限選擇性的15至50個蝕刻循環。每個蝕刻循環包含提供一沉積蝕刻階段,其將特徵蝕刻至該蝕刻層內並且在該特徵的側壁上和該光阻上方沉積聚合物;也提供一清潔階段,將沉積在該側壁上的聚合物移除。
於本發明之另一方面,提供一種用於在一蝕刻層內形成特徵的設備,其中該蝕刻層是以一基板所支承,且其中該蝕刻層是以一光阻遮罩所覆蓋但沒有一中間硬遮罩。一電漿處理室是以形成一電漿處理室封閉體的一室壁所提供,一基板支承物支承著在該電漿處理室封閉體內的一基板。一壓力調節器用以調節該電漿處理室封閉體內的壓力。至少有一個電極提供電力至該電漿處理室封閉體用以維持一電漿。一氣體入口提供氣體至該電漿處理室封閉體,一氣體出口從該電漿處理室封閉體排出氣體。一氣體源與該氣體入口作流體連接,並且包含一蝕刻氣體源、一沉積氣體源、以及一清潔階段氣體源。一控制器可控制地連接至該氣體源和該至少一個電極,該控制器包含至少一個處理器和電腦可讀取媒體。該電腦可讀取媒體包含用於提供15至50個蝕刻循環的電腦可讀取碼,其含有用於提供一沉積蝕刻階段的電腦可讀取碼,將特徵蝕刻至該蝕刻層內並且在該特徵的側壁上和該光阻上方沉積聚合物;也含有用於從該蝕刻氣體源提供一蝕刻氣體的電腦可讀取碼、用於從該蝕刻氣體產生一電漿的電腦可讀取碼、用於從該沉積氣體源提供一沉積氣體的電腦可讀取碼、用於從該沉積氣體產生一電漿的電腦可讀取碼、和用於停止該沉積和蝕刻階段的電腦可讀取碼,以及用於提供一清潔階段的電腦可讀取碼,將沉積在該側壁上的聚合物移除,其含有用於從該清潔階段氣體源提供一清潔階段氣體的電腦可讀取碼、用於從該清潔階段氣體產生一電漿的電腦可讀取碼、和用於停止該清潔階段的電腦可讀取碼。
本發明之這些和其他特性將詳細敘述於後,並參考下列所附圖式且敘述其細節部分。
現在將詳細敘述本發明並參考如圖式所呈現的一些較佳實施例。以下的敘述中,鋪陳許多細節為能提供全面瞭解本發明。然而,對於本技術領域的技術人員明顯的是本發明沒有這一些或全部的細節部分也能夠實施。其他的實例中,熟知的處理步驟和/或結構將不會詳細敘述,以避免對本發明產生不必要的混淆。
為有助於瞭解本發明,圖1是用於本發明之實施例中一處理步驟的一高階流程圖。一通道遮罩提供於一蝕刻層上方(步驟104)。圖2A是具有在一阻障層212上所形成一蝕刻層220的一堆疊層200之截面圖,而該阻障層形成於一晶圓210上方。此實例中配置在該阻障層212與該晶圓210之間的是層208。雖然該層208是顯示為形成於該晶圓210上方,在該蝕刻層220與該晶圓210之間可以有任何數目的材料層。此實例中,該阻障層212可以是碳化矽(SiC)層,或也可以是SiN。該蝕刻層220可以是一低k值的介電質,比如矽化有機的介電質和硼介電質,包括來自美國加州San Jose市Novellus公司的CORALTM ;來自美國加州Santa Clara市Applied Material公司的Black DiamondTM ;由荷蘭ASM International N.V.公司銷售的AuroraTM ;美國加州Santa Clara市Sumitomo Chemical America公司銷售的Sumika FirmR ;來自美國新澤西州Mirristown市Allied Signal公司的HOSPTM ;來自DOW Chemical公司的SiLKTM 或先進硼製SiLKTM ;來自Trikon公司的OrionR FlowfillTM ;以及來自JSR公司的LKDTM
通道圖樣的形成可以經由在該蝕刻層220上形成一抗反射層(ARL)216來進行,該ARL 216可以由旋轉塗佈而形成。
一光阻遮罩232是形成於該ARL 216上方(步驟104)。該光阻遮罩可以經由將一光阻層曝光至一附帶圖樣的光線來印製圖樣,然後將該光阻層232顯影,以得到在該光阻層內的通道開口224。
特徵是選擇性地被蝕刻至該蝕刻層220內(步驟108)。該選擇性蝕刻包括複數個循環,其中每個循環含有一沉積蝕刻階段(步驟112)和一聚合物清潔階段(步驟116)。
該沉積蝕刻階段(步驟112)相關於該光阻遮罩232選擇性蝕刻該蝕刻層220,並在該特徵的側壁上和該光阻上方沉積聚合物。圖2B是該堆疊200在一沉積蝕刻階段(步驟112)之後的截面圖。可以是已經進行一或多個蝕刻循環,該沉積蝕刻階段蝕刻部分的該特徵234,同時在該些特徵234的側壁上和該光阻遮罩232上方沉積一聚合物層236。如此一沉積蝕刻階段最好是一無限選擇性,因為如此一階段中蝕刻該蝕刻層220但沒有蝕刻該光阻層232,取而代之在該光阻遮罩232上方形成該聚合物236。
該聚合物清潔階段(步驟116)將該沉積的聚合物移除。圖2C是該堆疊200在一聚合物清潔階段之後的一截面圖。可以是已經進行一或多個蝕刻循環。該聚合物清潔階段將沉積在該特徵側壁上的聚合物移除。在一較佳實施例,該蝕刻層在該聚合物清潔階段過程中是不蝕刻該蝕刻層;但另一實施例,該聚合物清潔階段可以蝕刻在該特徵底部的蝕刻層。
該蝕刻循環最好是進行10至100個循環。比較理想地,該蝕刻循環進行15至50個循環;比較理想地,該蝕刻循環進行約20個循環。
圖2D是該堆疊200在完成該選擇性蝕刻(步驟108)之後的一截面圖。此實例中,該特徵234是被蝕刻穿過整個該蝕刻層220,而該光阻遮罩232還沒有被蝕刻,其提供無限的選擇性。
然後鬆脫該光阻遮罩232(步驟120)。
理想地,該特徵234的側壁是垂直的。最好地,該垂直側壁是從底部到頂部與該特徵底部形成為介於88度至90度之間一角度的側壁。
理想地,該蝕刻層是一介電質層。比較理想地,該蝕刻層是一低k值的介電質層。比較理想地,該介電質層是一低k值的氧化矽為基介電質層。
沒有該聚合物清潔階段(步驟116),可以繼續進行一連續的沉積蝕刻階段,以能夠在該特徵的側壁上增加較多的聚合物。結果,該特徵的寬度就會降低而產生錐狀但非取代垂直的側壁。如此一處理將導致一停止蝕刻,也就限制該蝕刻的深度。
單一步驟沉積蝕刻階段的實例
本發明之一較佳實施例的範例中,該基板210是一矽質晶圓,以及該介電質蝕刻層220是一OSG(矽化有機玻璃)或Coral。一較佳實例中,該阻障層是SiC(碳化矽)。該遮罩是利用一ArF(193奈米PR)光阻形成(步驟104)。一較佳實施例中,該ARC層是一底部的抗反射鍍層(BARC),而該基板210是放置在一電漿處理室內。
圖4是可以用於蝕刻和鬆脫的一電漿處理室400之一繪示圖。該電漿處理室400包含限制環402、一上方電極404、一下方電極408、一氣體源410、以及一抽氣幫浦420。該氣體源410可以包含一蝕刻氣體源、一沉積氣體源、和一清潔階段氣體源。在電漿處理室400內該基板210是位於該下方電極408之上,該下方電極408與一適合的基板夾頭機構(例如:靜電、機械夾合或類似物)組合用於支承該基板210。該反應器頂部428與配置在該下方電極正對面的該上方電極404組合。該上方電極404、該下方電極408、以及限制環402界定了所限定的電漿體積440。將氣體經由該氣體源410供給至該限定的電漿體積,並且經由該限制環402和該抽氣幫浦420的一抽氣口從所限定的電漿體積抽氣。一第一RF源444是電連接至該上方電極404,而一第二RF源448是電連接至該下方電極408。室壁452圍繞著該限制環402、該上方電極404、以及該下方電極408。該第一RF源444和該第二RF源448兩者可以包含一個27百萬赫茲(MHz)的電力源、一個60MHz的電力源、和一個2MHz的電力源。以不同的組合將RF電力連接至電極都是可能的。本發明之一較佳實施例中,該27MHz,60MHz和2MHz的電力源組成連接至該下方電極的該第二RF電力源448,且該上方電壓是接地的。一控制器435可控制地連接至該RF源444和448以及抽氣幫浦420和該氣體源410。此一裝置能夠調變該室內的壓力、氣體流動、氣體組合、RF電力以及每個階段的時間長短。
圖5A和5B呈現一電腦系統500,其適用於實施本發明之實施例中使用的一控制器435。圖5A顯示該電腦系統之一可能的實體形式,當然該電腦系統可以具有許多實體形式,範圍從一積體電路、一印刷電路板、和一小型的手持裝置到一巨型的超級電腦。電腦系統500包括一監視器502、一顯示器504、一外殼506、一磁碟機508、一鍵盤510、和一滑鼠512。碟片514是一電腦可讀取的媒體,用於將資料傳送至電腦系統500以及從中取得資料。
圖5B是用於電腦系統500的一方塊圖之實例。附加至系統匯流排520是一種類廣泛的子系統。處理器522(也稱為中央處理單元或CPUs)是耦接至儲存裝置,包括記憶體524。記憶體524包括隨機存取記憶體(RAM)和唯讀記憶體(ROM)。如本技術領域所熟悉,ROM的功能是單向地將資料和指令傳輸至該CPU,而RAM通常則是以雙向的方式傳輸資料和指令。此兩種型式的記憶體可以包括以下所敘述任何適合的電腦可讀取媒體。一固定的碟片526也是雙向耦接至CPU522,其提供額外的資料儲存能力,而且也可以包括以下所敘述任何適合的電腦可讀取媒體。固定碟片526可以用於儲存程式、資料、和類似物,且通常是比首要儲存較慢的第二儲存媒體(比如一硬碟)。在此將會理解到保留在固定碟片526內的資訊於適當的情況下可以整合為一標準形式,當做記憶體524中的虛擬記憶體。可移除碟片514可以是以下所敘述的電腦可讀取媒體之型式。
CPU 522也是耦接至各種型式的輸入/輸出裝置,比如顯示器504、鍵盤510、滑鼠512、和喇叭530。一般來說,一輸入/輸出裝置可以是影像顯示器、軌跡球、滑鼠、鍵盤、麥克風、觸控顯示器、轉換讀卡機、磁性或紙捲讀取機、平板電腦、光筆、聲音或手寫辨識器、生物測定讀取機、或其他電腦等任何之一。CPU 522可以選擇性地耦接至另外一個電腦或使用網路介面540的電訊網路。具有此一網路介面,目的在於該CPU可以接收來自該網路的資訊,或輸出資訊至執行上述方法步驟中的網路項目。此外,本發明之實施例方法可以僅在CPU上執行或可以在一網路上執行,比如連接能夠分享一部分處理的遠端CPU之網際網路。
此外,本發明之實施例進一步關於以一電腦可讀取媒體的電腦儲存產品,其上具有電腦碼用於進行各種電腦執行的操作。該媒體和電腦碼可以是那些用於本發明之目的而特別設計和結構,或者可以是電腦軟體技術領域中技術人員所熟知和可用的任何型式。電腦可讀取媒體的實例包括,但不限於,磁性媒體比如硬碟、軟碟、和磁帶;光學媒體比如CD-ROMs和全像裝置;磁性光學媒體比如軟光碟;以及特別架構用以儲存和執行程式碼的硬體裝置,比如特定應用的積體電路(ASICs)、可程式邏輯裝置(PLDs)、以及ROM和RAM裝置。電腦碼的實例包括機械碼,比如由一編輯器所產生和含有由一電腦使用一解讀器所執行的高階碼之檔案。電腦可讀取媒體也可以是由包含在一載波中一電腦訊號資料所傳送的電腦碼,且代表能夠由一處理器可執行的一連串指令。
特徵是選擇性地蝕刻至該蝕刻層220內(步驟108)。該選擇性蝕刻包括複數個循環,其中每個循環包含一沉積蝕刻階段(步驟112)和一聚合物清潔階段(步驟116)。
用於一沉積蝕刻階段(步驟112)的一實例配方如下:一沉積蝕刻階段氣體是提供40sccm的CF4 和90sccm的H2 。該室壓力設定在90mTorr(毫托耳)。由該27MHz的RF源提供1200瓦(W),而且由該2MHz的電力源提供400W。此實例中該沉積蝕刻是同時完成為一單一步驟。
用於一聚合物清潔階段(步驟116)的一實例配方如下:一聚合物清潔階段氣體是提供300sccm的O2 。該室壓力設定在250mTorr。由該27MHz的RF源提供100W,而且沒有電力是由該2MHz的電力源所提供。
然後鬆脫該溝渠遮罩(步驟120)。一遮罩鬆脫的實例提供10至3000sccm的O2 為鬆脫氣體。該室壓力設定在5至500mTorr。由該2MHz和該27MHz的RF源或2MHz和該27MHz的RF電力源兩者的組合提供100至1000W。
兩步驟的沉積蝕刻階段的實例
使用兩步驟沉積蝕刻階段的另一實例中,第一步驟是用以沉積聚合物且第二步驟是用以蝕刻該蝕刻層,可以如先前的實例使用相同的基板和蝕刻層。一遮罩是形成在該蝕刻層上方(步驟104),特徵是選擇性蝕刻至該蝕刻層220內(步驟108)。圖3是此實例中該沉積蝕刻階段(步驟112)的一詳細流程圖。此實例中,每個沉積蝕刻階段包含一連串在光阻和側壁上沉積聚合物的步驟(步驟304),以及然後一蝕刻特徵步驟(步驟308)。此一實施例中,每個沉積蝕刻階段(步驟112)進行一單一沉積聚合物步驟(步驟304),然後再進行一單一蝕刻特徵步驟(步驟308)。另一實施例中,每個沉積蝕刻階段(步驟112)重複進行複數次的一單一沉積聚合物步驟(步驟304),然後是一單一蝕刻特徵步驟(步驟308)。
用於在光阻和側壁上沉積聚合物步驟(步驟304)的一實例配方如下:一沉積聚合物的氣體是提供50sccm的CH3 F和250sccm的Ar。該室壓力設定在40mTorr。由該27MHz的RF源提供500W,而且由該2MHz的電力源提供200W,用以從該沉積聚合物的氣體產生一電漿。
用於一蝕刻特徵步驟(步驟308)的一實例配方如下:一蝕刻氣體是提供25sccm的C4 F6 和24sccm的O2 和200sccm的Ar。該室壓力設定在40mTorr。由該27MHz的RF源提供1200W而且由該2MHz的電力源提供1200W用以從該蝕刻氣體產生一電漿。
用於一聚合物清潔階段(步驟116)的一實例配方如下:一聚合物清潔階段氣體是提供25sccm的C4 F6 和35sccm的O2 和200sccm的Ar。該室壓力設定在35mTorr。由該27MHz的RF源提供1200W而且由該2MHz的電力源提供1200W,用以從該聚合物清潔階段氣體產生一電漿。
然後鬆脫該遮罩(步驟120)。上述實例中的配方可以用於鬆脫該遮罩。
這些實例中,該電漿處理室應該能夠調變該室內的壓力、氣體流動、氣體組合、RF電力以及每個階段的時間長短。
於本發明以數個較佳實施例敘述之時,也能夠有變化、交換、和各種的替代等同物是在本發明之範圍內。應該注意到有許多變化的方式以實施本發明之方法和設備,所以刻意地將以下所附的申請專利範圍解讀為包括所有變化、交換、和各種替代等同物為在本發明之真實精神與範圍內。
200...堆疊層
208...層
210...晶圓
212...阻障層
216...抗反射層
220...蝕刻層
224...開口
232...光阻遮罩
234...特徵
236...聚合物層
400...電漿處理室
402...限制環
404...上方電極
408...下方電極
410...氣體源
420...抽氣幫浦
428...反應器頂部
435...控制器
440...電漿體積
444...第一RF源
448...第二RF源
452...室壁
500...電腦系統
502...監視器
504...顯示器
506...外殼
508...磁碟機
510...鍵盤
512...滑鼠
514...可移除碟片
520...系統匯流排
522...處理器(中央處理單元)
524...記憶體
526...固定碟片
530...喇叭
540...網路介面
本發明以實例呈現,於所附圖式並非以此方式為限制,其中相似的參考數字代表相似的元件,其圖式有:圖1是用於本發明之實施例中在一蝕刻層內形成特徵的高階流程圖;圖2A-D是根據本發明之圖1呈現實施例中形成特徵的繪示圖;圖3是一個兩步驟沉積蝕刻階段的一較詳細流程圖;圖4是可以用於蝕刻和鬆脫的一電漿處理室之繪示圖;圖5A-B呈現一電腦系統,其適於執行用於本發明之一實施例中的一控制器。

Claims (10)

  1. 一種用於將特徵蝕刻至配置在一光阻遮罩下方的一蝕刻層內而沒有一中間硬遮罩之方法,包含:提供複數個蝕刻循環,其中每個蝕刻循環包含:提供一沉積蝕刻階段,其將特徵蝕刻至該蝕刻層內,並在該些特徵的側壁上和該光阻上方沉積聚合物,其中該沉積蝕刻階段包含同時蝕刻該蝕刻層並在該些特徵的側壁上沉積聚合物之一單一步驟,其中該沉積蝕刻階段包含提供含有CF4 和H2 的氣體;以及提供一清潔階段,其將沉積在該些側壁上的聚合物移除;其中,該複數個蝕刻循環之後,該些蝕刻特徵具有底部和從底部到頂部的側壁,該些側壁相對於該些特徵的底部形成88度至90度之間的一角度,其中該提供複數個循環包含提供10至100個循環。
  2. 一種用於將特徵蝕刻至配置在一光阻遮罩下方的一蝕刻層內而沒有一中間硬遮罩之方法,包含:提供複數個蝕刻循環,其中每個蝕刻循環包含:提供一沉積蝕刻階段,其將特徵蝕刻至該蝕刻層內,並在該些特徵的側壁上和該光阻上方沉積聚合物,其中該沉積蝕刻階段包含同時蝕刻該蝕刻層並在該些特徵的側壁上沉積聚合物之一單一步驟,其中該沉積蝕刻階段包含提供含有CF4 和H2 的氣體;以及提供一清潔階段,其將沉積在該些側壁上的聚合 物移除;其中,該複數個蝕刻循環之後,該些蝕刻特徵具有底部和從底部到頂部的側壁,該些側壁相對於該些特徵的底部形成88度至90度之間的一角度,其中該提供複數個循環包含提供15至50個循環。
  3. 如申請專利範圍第2項之方法,其中該沉積蝕刻階段選擇性蝕刻有關該光阻遮罩的該蝕刻層。
  4. 如申請專利範圍第3項之方法,其中該清潔階段選擇性移除沉積在有關該蝕刻層之該些側壁上的聚合物。
  5. 如申請專利範圍第4項之方法,其中該沉積蝕刻階段不移除該光阻遮罩提供一無限選擇性的該光阻遮罩。
  6. 一種用於將特徵蝕刻至配置在一光阻遮罩下方的一蝕刻層內而沒有一中間硬遮罩之方法,包含:提供15至50個蝕刻循環,其無限選擇性地蝕刻有關該光阻遮罩的該蝕刻層,其中每個蝕刻循環包含:提供一沉積蝕刻階段,其將特徵蝕刻至該蝕刻層內,並在該些特徵的側壁上和該光阻上方沉積聚合物,其中該沉積蝕刻階段包含同時蝕刻該蝕刻層並在該些特徵的側壁上沉積聚合物之一單一步驟;以及提供一清潔階段,其將沉積在該些側壁上的聚合物移除;其中,該複數個蝕刻循環之後,該些蝕刻特徵具有底部和從底部到頂部的側壁,該些側壁相對於該些特徵的底部形成88度至90度之間的一角度。
  7. 如申請專利範圍第6項之方法,其中該提供一沉積蝕刻階段包含:提供一蝕刻氣體;從該蝕刻氣體產生一電漿;提供一沉積氣體;從該沉積氣體產生一電漿;以及停止該沉積蝕刻階段,且其中該提供一清潔階段包含:提供一清潔階段氣體;從該清潔階段氣體產生一電漿;以及停止該清潔階段。
  8. 如申請專利範圍第6項之方法,其中該沉積蝕刻階段包含提供含有CF4 和H2 的氣體,其中該提供含有提供大約40sccm的CF4 和大約90sccm的H2
  9. 如申請專利範圍第6項之方法,其中該沉積蝕刻階段包含提供一基本上含有CF4 和H2 的氣體。
  10. 一種用於將特徵蝕刻至配置在一光阻遮罩下方的一蝕刻層內而沒有一中間硬遮罩之方法,包含:提供複數個蝕刻循環,其中每個蝕刻循環包含:提供一沉積蝕刻階段,其將特徵蝕刻至該蝕刻層內,並在該些特徵的側壁上和該光阻上方沉積聚合物,其中該沉積蝕刻階段包含同時蝕刻該蝕刻層並在該些特徵的側壁上沉積聚合物之一單一步驟,其中該沉積蝕刻階段包含提供含有CF4 和H2 的氣體;以及 提供一清潔階段,其將沉積在該些側壁上的聚合物移除;其中,該複數個蝕刻循環之後,該些蝕刻特徵具有底部和從底部到頂部的側壁,該些側壁相對於該些特徵的底部形成88度至90度之間的一角度,其中該提供含有CF4 和H2 的氣體,包含提供大約40sccm的CF4 和大約90sccm的H2
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Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7682516B2 (en) * 2005-10-05 2010-03-23 Lam Research Corporation Vertical profile fixing
JP5103006B2 (ja) 2006-11-16 2012-12-19 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US20080203056A1 (en) * 2007-02-26 2008-08-28 Judy Wang Methods for etching high aspect ratio features
US8901004B2 (en) * 2009-07-27 2014-12-02 Lam Research Corporation Plasma etch method to reduce micro-loading
KR101082134B1 (ko) 2010-03-16 2011-11-09 삼성모바일디스플레이주식회사 드라이 에칭 장치를 이용한 터치 스크린 패널의 제작방법
JP5802454B2 (ja) * 2011-06-30 2015-10-28 株式会社日立ハイテクノロジーズ プラズマ処理方法
US8608973B1 (en) * 2012-06-01 2013-12-17 Lam Research Corporation Layer-layer etch of non volatile materials using plasma
US20140051256A1 (en) * 2012-08-15 2014-02-20 Lam Research Corporation Etch with mixed mode pulsing
JP6267953B2 (ja) * 2013-12-19 2018-01-24 東京エレクトロン株式会社 半導体装置の製造方法
US9159561B2 (en) 2013-12-26 2015-10-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method for overcoming broken line and photoresist scum issues in tri-layer photoresist patterning
CN105565252B (zh) * 2014-10-10 2018-03-30 中芯国际集成电路制造(上海)有限公司 一种mems器件及其制备方法、电子装置
US9595451B1 (en) 2015-10-19 2017-03-14 Applied Materials, Inc. Highly selective etching methods for etching dielectric materials
US9728501B2 (en) 2015-12-21 2017-08-08 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming trenches
US10497578B2 (en) 2016-07-22 2019-12-03 Applied Materials, Inc. Methods for high temperature etching a material layer using protection coating
US20180323061A1 (en) * 2017-05-03 2018-11-08 Tokyo Electron Limited Self-Aligned Triple Patterning Process Utilizing Organic Spacers
JP6878174B2 (ja) * 2017-06-29 2021-05-26 東京エレクトロン株式会社 プラズマエッチング方法及びプラズマエッチング装置
US10727045B2 (en) * 2017-09-29 2020-07-28 Taiwan Semiconductor Manufacturing Company, Ltd. Method for manufacturing a semiconductor device
US10727075B2 (en) 2017-12-22 2020-07-28 Applied Materials, Inc. Uniform EUV photoresist patterning utilizing pulsed plasma process
KR20200108361A (ko) * 2018-02-05 2020-09-17 램 리써치 코포레이션 비정질 탄소 층 개방 프로세스
US11177177B2 (en) * 2018-11-30 2021-11-16 Taiwan Semiconductor Manufacturing Company Limited Semiconductor device and method of manufacture

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5401359A (en) * 1990-07-27 1995-03-28 Sony Corporation Dry etching method
US20010012694A1 (en) * 1998-02-24 2001-08-09 Coburn John W. Plasma etching method using low ionization potential gas
US6376382B1 (en) * 1998-11-27 2002-04-23 United Microelectronics Corp. Method for forming an opening
US20020179570A1 (en) * 2001-06-05 2002-12-05 International Business Machines Corporation Method of etching high aspect ratio openings
US20030162395A1 (en) * 2000-08-31 2003-08-28 Micron Technology, Inc. Method to eliminate striations and surface roughness caused by dry etch
US20050048789A1 (en) * 2003-09-03 2005-03-03 Merry Walter R. Method for plasma etching a dielectric layer

Family Cites Families (67)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4414059A (en) * 1982-12-09 1983-11-08 International Business Machines Corporation Far UV patterning of resist materials
JPS6313334A (ja) 1986-07-04 1988-01-20 Hitachi Ltd ドライエツチング方法
KR900007687B1 (ko) * 1986-10-17 1990-10-18 가부시기가이샤 히다찌세이사꾸쇼 플라즈마처리방법 및 장치
US4698128A (en) 1986-11-17 1987-10-06 Motorola, Inc. Sloped contact etch process
JP2918892B2 (ja) * 1988-10-14 1999-07-12 株式会社日立製作所 プラズマエッチング処理方法
JPH04240729A (ja) 1991-01-24 1992-08-28 Toshiba Corp パターン形成方法
DE4241045C1 (de) * 1992-12-05 1994-05-26 Bosch Gmbh Robert Verfahren zum anisotropen Ätzen von Silicium
JP3437863B2 (ja) * 1993-01-18 2003-08-18 株式会社半導体エネルギー研究所 Mis型半導体装置の作製方法
JPH07226397A (ja) 1994-02-10 1995-08-22 Tokyo Electron Ltd エッチング処理方法
DE4317623C2 (de) * 1993-05-27 2003-08-21 Bosch Gmbh Robert Verfahren und Vorrichtung zum anisotropen Plasmaätzen von Substraten und dessen Verwendung
JP2674488B2 (ja) * 1993-12-01 1997-11-12 日本電気株式会社 ドライエッチング室のクリーニング方法
US5545289A (en) * 1994-02-03 1996-08-13 Applied Materials, Inc. Passivating, stripping and corrosion inhibition of semiconductor substrates
US5562801A (en) * 1994-04-28 1996-10-08 Cypress Semiconductor Corporation Method of etching an oxide layer
US5468342A (en) * 1994-04-28 1995-11-21 Cypress Semiconductor Corp. Method of etching an oxide layer
JPH0936089A (ja) 1995-07-19 1997-02-07 Toshiba Corp アッシング方法及びその装置
GB9616225D0 (en) * 1996-08-01 1996-09-11 Surface Tech Sys Ltd Method of surface treatment of semiconductor substrates
EP0822582B1 (en) 1996-08-01 2003-10-01 Surface Technology Systems Plc Method of etching substrates
DE19641288A1 (de) * 1996-10-07 1998-04-09 Bosch Gmbh Robert Verfahren zum anisotropen Plasmaätzen verschiedener Substrate
US5882535A (en) * 1997-02-04 1999-03-16 Micron Technology, Inc. Method for forming a hole in a semiconductor device
DE19706682C2 (de) * 1997-02-20 1999-01-14 Bosch Gmbh Robert Anisotropes fluorbasiertes Plasmaätzverfahren für Silizium
US6010603A (en) * 1997-07-09 2000-01-04 Applied Materials, Inc. Patterned copper etch for micron and submicron features, using enhanced physical bombardment
DE19730644C1 (de) * 1997-07-17 1998-11-19 Bosch Gmbh Robert Verfahren zum Erkennen des Übergangs unterschiedlicher Materialien in Halbleiterstrukturen bei einer anisotropen Tiefenätzung
US6187685B1 (en) * 1997-08-01 2001-02-13 Surface Technology Systems Limited Method and apparatus for etching a substrate
DE19734278C1 (de) * 1997-08-07 1999-02-25 Bosch Gmbh Robert Vorrichtung zum anisotropen Ätzen von Substraten
DE19736370C2 (de) * 1997-08-21 2001-12-06 Bosch Gmbh Robert Verfahren zum anisotropen Ätzen von Silizium
US5942446A (en) * 1997-09-12 1999-08-24 Taiwan Semiconductor Manufacturing Company, Ltd. Fluorocarbon polymer layer deposition predominant pre-etch plasma etch method for forming patterned silicon containing dielectric layer
US6074959A (en) * 1997-09-19 2000-06-13 Applied Materials, Inc. Method manifesting a wide process window and using hexafluoropropane or other hydrofluoropropanes to selectively etch oxide
US5849639A (en) * 1997-11-26 1998-12-15 Lucent Technologies Inc. Method for removing etching residues and contaminants
TW505984B (en) 1997-12-12 2002-10-11 Applied Materials Inc Method of etching patterned layers useful as masking during subsequent etching or for damascene structures
KR100520148B1 (ko) * 1997-12-31 2006-05-12 주식회사 하이닉스반도체 신규한바이시클로알켄유도체와이를이용한포토레지스트중합체및이중합체를함유한포토레지스트조성물
US6387287B1 (en) * 1998-03-27 2002-05-14 Applied Materials, Inc. Process for etching oxide using a hexafluorobutadiene and manifesting a wide process window
US6071822A (en) * 1998-06-08 2000-06-06 Plasma-Therm, Inc. Etching process for producing substantially undercut free silicon on insulator structures
US6127258A (en) 1998-06-25 2000-10-03 Motorola Inc. Method for forming a semiconductor device
US6025255A (en) * 1998-06-25 2000-02-15 Vanguard International Semiconductor Corporation Two-step etching process for forming self-aligned contacts
US6211092B1 (en) * 1998-07-09 2001-04-03 Applied Materials, Inc. Counterbore dielectric plasma etch process particularly useful for dual damascene
KR100639841B1 (ko) 1998-07-23 2006-10-27 서페이스 테크놀로지 시스템스 피엘씨 이방성 에칭 장치 및 방법
US6406995B1 (en) * 1998-09-30 2002-06-18 Intel Corporation Pattern-sensitive deposition for damascene processing
JP2000208767A (ja) * 1998-11-13 2000-07-28 Seiko Epson Corp 半導体装置の製造方法
US6100200A (en) * 1998-12-21 2000-08-08 Advanced Technology Materials, Inc. Sputtering process for the conformal deposition of a metallization or insulating layer
US6187666B1 (en) * 1999-06-08 2001-02-13 Advanced Micro Devices, Inc. CVD plasma process to fill contact hole in damascene process
US6316169B1 (en) * 1999-06-25 2001-11-13 Lam Research Corporation Methods for reducing profile variation in photoresist trimming
US6235453B1 (en) 1999-07-07 2001-05-22 Advanced Micro Devices, Inc. Low-k photoresist removal process
KR100327346B1 (ko) 1999-07-20 2002-03-06 윤종용 선택적 폴리머 증착을 이용한 플라즈마 식각방법 및 이를이용한 콘택홀 형성방법
US6593653B2 (en) * 1999-09-30 2003-07-15 Novellus Systems, Inc. Low leakage current silicon carbonitride prepared using methane, ammonia and silane for copper diffusion barrier, etchstop and passivation applications
US6291357B1 (en) * 1999-10-06 2001-09-18 Applied Materials, Inc. Method and apparatus for etching a substrate with reduced microloading
WO2001029879A2 (en) 1999-10-20 2001-04-26 Mattson Technology, Inc. Systems and methods for photoresist strip and residue treatment in integrated circuit manufacturing
US6326307B1 (en) * 1999-11-15 2001-12-04 Appllied Materials, Inc. Plasma pretreatment of photoresist in an oxide etch process
US6391788B1 (en) * 2000-02-25 2002-05-21 Applied Materials, Inc. Two etchant etch method
US6451703B1 (en) 2000-03-10 2002-09-17 Applied Materials, Inc. Magnetically enhanced plasma etch process using a heavy fluorocarbon etching gas
US6284666B1 (en) * 2000-05-31 2001-09-04 International Business Machines Corporation Method of reducing RIE lag for deep trench silicon etching
JP2002025979A (ja) * 2000-07-03 2002-01-25 Hitachi Ltd 半導体集積回路装置の製造方法
US6500743B1 (en) * 2000-08-30 2002-12-31 Advanced Micro Devices, Inc. Method of copper-polysilicon T-gate formation
US6403491B1 (en) * 2000-11-01 2002-06-11 Applied Materials, Inc. Etch method using a dielectric etch chamber with expanded process window
DE10059836A1 (de) 2000-12-01 2002-06-13 Infineon Technologies Ag Verfahren zur Strukturierung dielektrischer Schichten
US20030027427A1 (en) * 2001-08-06 2003-02-06 Applied Materials, Inc. Integrated system for oxide etching and metal liner deposition
WO2003037497A2 (en) * 2001-10-31 2003-05-08 Tokyo Electron Limited Method of etching high aspect ratio features
US20030118948A1 (en) * 2001-12-21 2003-06-26 Rohit Grover Method of etching semiconductor material to achieve structure suitable for optics
US6647994B1 (en) * 2002-01-02 2003-11-18 Taiwan Semiconductor Manufacturing Company Method of resist stripping over low-k dielectric material
US6846516B2 (en) 2002-04-08 2005-01-25 Applied Materials, Inc. Multiple precursor cyclical deposition system
US6979652B2 (en) * 2002-04-08 2005-12-27 Applied Materials, Inc. Etching multi-shaped openings in silicon
US6784096B2 (en) 2002-09-11 2004-08-31 Applied Materials, Inc. Methods and apparatus for forming barrier layers in high aspect ratio vias
SG152920A1 (en) * 2002-10-11 2009-06-29 Lam Res Corp A method for plasma etching performance enhancement
US6833325B2 (en) 2002-10-11 2004-12-21 Lam Research Corporation Method for plasma etching performance enhancement
US7169695B2 (en) 2002-10-11 2007-01-30 Lam Research Corporation Method for forming a dual damascene structure
US20040097077A1 (en) * 2002-11-15 2004-05-20 Applied Materials, Inc. Method and apparatus for etching a deep trench
US7294580B2 (en) * 2003-04-09 2007-11-13 Lam Research Corporation Method for plasma stripping using periodic modulation of gas chemistry and hydrocarbon addition
US6916746B1 (en) * 2003-04-09 2005-07-12 Lam Research Corporation Method for plasma etching using periodic modulation of gas chemistry

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5401359A (en) * 1990-07-27 1995-03-28 Sony Corporation Dry etching method
US20010012694A1 (en) * 1998-02-24 2001-08-09 Coburn John W. Plasma etching method using low ionization potential gas
US6376382B1 (en) * 1998-11-27 2002-04-23 United Microelectronics Corp. Method for forming an opening
US20030162395A1 (en) * 2000-08-31 2003-08-28 Micron Technology, Inc. Method to eliminate striations and surface roughness caused by dry etch
US20020179570A1 (en) * 2001-06-05 2002-12-05 International Business Machines Corporation Method of etching high aspect ratio openings
US20050048789A1 (en) * 2003-09-03 2005-03-03 Merry Walter R. Method for plasma etching a dielectric layer

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CN101421830A (zh) 2009-04-29
WO2007094957A1 (en) 2007-08-23
KR101442269B1 (ko) 2014-09-19
US20070193973A1 (en) 2007-08-23
US7910489B2 (en) 2011-03-22
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