TWI420645B - 在半導體封裝件形成全表面包覆電磁干擾遮蔽層的方法 - Google Patents
在半導體封裝件形成全表面包覆電磁干擾遮蔽層的方法 Download PDFInfo
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Description
本發明係有關於半導體裝置之製造,特別係有關於一種在半導體封裝件形成全表面包覆電磁干擾遮蔽層的方法。
一般而言,半導體封裝件是利用一電氣絕緣的封裝材料(或稱為封膠體)密封內部的積體電路晶片,隨著積體電路的高頻化與微小化發展,更加容易受到電磁干擾而導致訊號傳輸失敗。故半導體封裝件內會設置電磁干擾遮蔽結構,以防止內部與外部之電磁干擾。目前電磁干擾遮蔽結構大致分為兩類:其一為內置於封膠體且被密封的電磁干擾遮蔽片,如美國專利第6,365,960號所揭示之技術;另一為貼附於封膠體之上表面之電磁干擾遮蔽板片或遮蔽金屬層,如美國專利第5,294,826號所揭示之技術。其中,內置式電磁干擾遮蔽片會有模封困難之問題,外貼式電磁干擾遮蔽板片/金屬層則會有在半導體封裝件之側邊與底部遮蔽效果不佳之問題以及容易電性短路至外接端子之疑慮。
為了解決上述之問題,本發明之主要目的係在於一種在半導體封裝件形成全表面包覆電磁干擾遮蔽層的方法,用以增進對電磁干擾之全表面遮蔽效果,並且能防止電性短路至半導體封裝件之外接端子。
本發明的目的及解決其技術問題是採用以下技術方案來實現的。本發明揭示一種在半導體封裝件形成全表面包覆電磁干擾遮蔽層的方法。首先,提供一半導體封裝件,係包含一晶片、一密封該晶片之封膠體以及複數個顯露於該封膠體外之外接端子,並且該半導體封裝件係具有一上表面、一下表面以及複數個側面。之後,形成一暫時性保護層於該些外接端子之顯露表面,並且該暫時性保護層係接觸至該半導體封裝件圍繞該些外接端子之表面區域。接著,形成一電磁干擾遮蔽層於該半導體封裝件之該上表面、該下表面以及該些側面,而不形成於該些外接端子之顯露表面。
本發明的目的及解決其技術問題還可採用以下技術措施進一步實現。
在前述之方法中,該暫時性保護層係可具有一用以定義該表面區域之厚度,以使該電磁干擾遮蔽層不電性連接至該些外接端子。
在前述之方法中,可另包含之步驟為:以加熱方式移除該暫時性保護層。
在前述之方法中,該暫時性保護層係可為一有機保焊膜(Organic Solderability Preservatives,OSP),而上述移除該暫時性保護層之步驟係可包含助焊劑之使用。
在前述之方法中,該些外接端子係可為一導線架之複數個外引腳。
在前述之方法中,該些外引腳係可由該半導體封裝件之該些側面延伸而出。
在前述之方法中,該半導體封裝件之該上表面、該下表面以及該些側面係可皆由該封膠體所構成。
在前述之方法中,該些外接端子係可包含複數個銲球,其係設置於該半導體封裝件之該下表面。
在前述之方法中,該半導體封裝件係可更包含一基板,用以承載該晶片。
在前述之方法中,該半導體封裝件之該上表面與大部份之該些側面係可由該封膠體所構成,該半導體封裝件之該下表面係由該基板所構成。
以下將配合所附圖示詳細說明本發明之實施例,然應注意的是,該些圖示均為簡化之示意圖,僅以示意方法來說明本發明之基本架構或實施方法,故僅顯示與本案有關之元件與組合關係,圖中所顯示之元件並非以實際實施之數目、形狀、尺寸做等比例繪製,某些尺寸比例與其他相關尺寸比例或已誇張或是簡化處理,以提供更清楚的描述。實際實施之數目、形狀及尺寸比例為一種選置性之設計,詳細之元件佈局可能更為複雜。
依據本發明之第一較佳實施例,一種在半導體封裝件形成全表面包覆電磁干擾遮蔽層的方法舉例說明於第1圖之流程圖與第2A至2D圖各步驟之元件截面示意圖。依照第1圖之流程步驟,本發明之方法係主要包含:「提供半導體封裝件」之步驟1、「形成暫時性保護層於半導體封裝件之外接端子」之步驟2、「形成電磁干擾遮蔽層於半導體封裝件之表面」之步驟3,而「以加熱方式移除暫時性保護層」之步驟4係可在步驟3之後選擇性執行。
首先,在本實施例中,步驟1可配合參閱第2A圖,提供一半導體封裝件110,係包含一晶片111、一密封該晶片111之封膠體112以及複數個顯露於該封膠體112外之外接端子113,並且該半導體封裝件110係具有一上表面116、一下表面117以及複數個側面118。該晶片111係為一主動元件,內包含有所需要的積體電路,例如記憶體或控制器…等等,而該晶片111之數量可為一個或是複數個。在本實施例中,該些外接端子113係可為一導線架之複數個外引腳,作為該半導體封裝件110的對外連接端子。該些外引腳係可由該半導體封裝件110之該些側面118延伸而出。該導線架另具有複數個在該封膠體112內且一體連接該些外引腳之內引腳114。利用該導線架之至少一晶片承座或是連接該些外引腳之該些內引腳114承載該晶片111。再如第2A圖所示,該晶片111係可貼附於該些內引腳114,達到支撐與承載效果,並利用複數個銲線115或其它電性連接元件電性連接該晶片111至該些內引腳。該封膠體112係為由模封方式形成之電絕緣材料,用以密封保護該晶片111。此外,該半導體封裝件110之該上表面116、該下表面117以及該些側面118係可皆由該封膠體112所構成。其中,該下表面117係為該半導體封裝件110供表面接合之底面,即該些外接端子113(即導線架之外引腳)往下彎曲之方向的表面,該上表面116係為該半導體封裝件110在表面接合之後之外露表面,該上表面116上可作產品標記。
之後,步驟2可配合參閱第2B圖,形成一暫時性保護層120於該些外接端子113之顯露表面,該些顯露表面係為金屬外露表面。並且,該暫時性保護層120係接觸至該半導體封裝件110圍繞該些外接端子113之表面區域119(如第3圖所示)。在本實施例中,該些表面區域119係為該些側面118圍繞該些外接端子113之區域。如第3圖所示,較佳地,該暫時性保護層120係可具有一用以定義該表面區域119之厚度T1,以使後續形成之電磁干擾遮蔽層130不電性連接至該些外接端子113(如第2D圖所示)。該暫時性保護層120之厚度T1應介於0.01~0.5微米(um),可大於該電磁干擾遮蔽層130之厚度。較佳地,該暫時性保護層120係可為一有機保焊膜(Organic Solderability Preservatives,OSP),故能夠以化學方式使該暫時性保護層120只形成於該些外接端子113之金屬表面,而不會形成於該封膠體112之絕緣表面,並具有製程中容易清除之優點。而該暫時性保護層120之形成方法係可為浸染(dipping)或是圖案化噴塗。
接著,步驟2可配合參閱第2C圖,形成一電磁干擾遮蔽層130於該半導體封裝件110之該上表面116、該下表面117以及該些側面118,而不形成於該些外接端子113之顯露表面。該電磁干擾遮蔽層130係具有遮蔽電磁干擾效應之特性,一般為導電材質,例如銀、鋁、導電碳黑或由樹脂與導電添加劑所製成的導電性高分子層,或銀銅導電漆等已知導電材料構成之複合結構。該電磁干擾遮蔽層130之厚度可介於0.1~100微米(um),該電磁干擾遮蔽層130之形成方法可為塗佈、噴灑、浸染等方法。故該電磁干擾遮蔽層130之包覆效果優於傳統的內置式或單表面外貼式電磁干擾遮蔽層,且不會影響該些外接端子113的接合。
因此,本發明之一種在半導體封裝件形成全表面包覆電磁干擾遮蔽層的方法係用以增進對電磁干擾之全表面遮蔽效果,並且能防止電性短路至半導體封裝件之外接端子。
此外,在製程中尚可進行步驟4,可配合參閱第2D圖,本方法係可另包含之步驟為:以加熱方式移除該暫時性保護層120,此一步驟具有一附加功效為:使該電磁干擾遮蔽層130可更強力地黏附於該封膠體112。另外,當該暫時性保護層120係為一有機保焊膜時,而上述移除該暫時性保護層120之步驟係可包含助焊劑(flux)之配合使用,以徹底且快速地清除該暫時性保護層120。
依據本發明之第二較佳實施例,另一種在半導體封裝件形成全表面包覆電磁干擾遮蔽層的方法舉例說明於第1圖之流程圖與第4A至4D圖各步驟之元件截面示意圖。第二較佳實施例係用以說明本發明之方法可適用於不同類型的半導體封裝產品。
首先,在本實施例中,步驟1可配合參閱第4A圖,提供一半導體封裝件210,係包含一晶片211、一密封該晶片211之封膠體212以及複數個顯露於該封膠體212外之外接端子213,並且該半導體封裝件210係具有一上表面216、一下表面217以及複數個側面218。在本實施例中,該些外接端子213係可包含複數個銲球,其係設置於該半導體封裝件210之該下表面217。該半導體封裝件210係可更包含一基板214,用以承載該晶片211。再如第4A圖所示,該晶片211係可貼附於該基板214,達到支撐與承載效果,並利用複數個銲線215或其它電性連接元件電性連接該晶片211至該基板214之接指214A。在本實施例中,該半導體封裝件210之該上表面216與大部份之該些側面218係可由該封膠體212所構成,該半導體封裝件210之該下表面217係由該基板214所構成。其中,該下表面217係為該半導體封裝件210供表面接合之底面,即該些外接端子213(例如銲球)的設置表面,該下表面217可設置有複數個球墊214B,以供該些外接端子213之接合。
之後,步驟2可配合參閱第4B圖,形成一暫時性保護層220於該些外接端子213之顯露表面,該些顯露表面係為銲球金屬成份之外露表面。並且,該暫時性保護層220係接觸至該半導體封裝件210圍繞該些外接端子213之表面區域219(如第5圖所示)。在本實施例中,該些表面區域219係為該下表面217圍繞該些外接端子213之區域。如第5圖所示,較佳地,該暫時性保護層220係可具有一用以定義該表面區域219之厚度T1,以使後續形成之電磁干擾遮蔽層230不電性連接至該些外接端子213(如第4D圖所示)。
接著,步驟2可配合參閱第4C圖,形成一電磁干擾遮蔽層230於該半導體封裝件210之該上表面216、該下表面217以及該些側面218,而不形成於該些外接端子213之顯露表面。
此外,在製程中尚可進行步驟4,可配合參閱第4D圖,本方法係可另包含之步驟為:以加熱方式移除該暫時性保護層220。當該暫時性保護層220係為一有機保焊膜時,而上述移除該暫時性保護層220之步驟係可包含助焊劑(flux)之配合使用,以徹底且快速地清除該暫時性保護層220。故該電磁干擾遮蔽層230之包覆效果優於傳統的內置式或單表面外貼式電磁干擾遮蔽層,且不會影響該些外接端子213的接合。
以上所述,僅是本發明的較佳實施例而已,並非對本發明作任何形式上的限制,雖然本發明已以較佳實施例揭露如上,然而並非用以限定本發明,任何熟悉本項技術者,在不脫離本發明之技術範圍內,所作的任何簡單修改、等效性變化與修飾,均仍屬於本發明的技術範圍內。
1...提供半導體封裝件
2...形成暫時性保護層於半導體封裝件之外接端子
3...形成電磁干擾遮蔽層於半導體封裝件之表面
4...以加熱方式移除暫時性保護層
110...半導體封裝件
111...晶片
112...封膠體
113...外接端子
114...內引腳
115...銲線
116...上表面
117...下表面
118...側面
119...表面區域
120...暫時性保護層
130...電磁干擾遮蔽層
210...半導體封裝件
211...晶片
212...封膠體
213...外接端子
214...基板
214A...接指
214B...球墊
215...銲線
216...上表面
217...下表面
218...側面
219...表面區域
220...暫時性保護層
230...電磁干擾遮蔽層
T1...暫時性保護層之厚度
第1圖:依據本發明之一種在半導體封裝件形成全表面包覆電磁干擾遮蔽層的方法之流程圖。
第2A至2D圖:依據本發明之一第一實施例,繪示一種在半導體封裝件形成全表面包覆電磁干擾遮蔽層的方法之主要步驟中之元件截面示意圖。
第3圖:依據本發明之一第一實施例,在形成暫時性保護層之步驟之後之半導體封裝件之局部側面示意圖。
第4A至4D圖:依據本發明之一第二實施例,繪示另一種在半導體封裝件形成全表面包覆電磁干擾遮蔽層的方法之主要步驟中之元件截面示意圖。
第5圖:依據本發明之一第二實施例,在形成暫時性保護層之步驟之後之半導體封裝件之局部下表面示意圖。
110...半導體封裝件
111...晶片
112...封膠體
113...外接端子
114...內引腳
115...銲線
116...上表面
117...下表面
118...側面
120...暫時性保護層
130...電磁干擾遮蔽層
Claims (10)
- 一種在半導體封裝件形成全表面包覆電磁干擾遮蔽層的方法,包含:提供一半導體封裝件,係包含一晶片、一密封該晶片之封膠體以及複數個顯露於該封膠體外之外接端子,並且該半導體封裝件係具有一上表面、一下表面以及複數個側面;形成一暫時性保護層於該些外接端子之複數個顯露表面,並且該暫時性保護層係接觸至該半導體封裝件圍繞與鄰近於該些外接端子之複數個環形表面區域;形成一電磁干擾遮蔽層於該半導體封裝件之該上表面、該下表面以及該些側面,而不形成於該些外接端子之該些顯露表面;以及移除該暫時性保護層,以創造一間隙在該電磁干擾遮蔽層與該些外接端子之間,其中該間隙係由該暫時性保護層之厚度予以界定。
- 依據申請專利範圍第1項所述之在半導體封裝件形成全表面包覆電磁干擾遮蔽層的方法,其中該暫時性保護層之厚度係定義該些環形表面區域之寬度,以使該電磁干擾遮蔽層不電性連接至該些外接端子。
- 依據申請專利範圍第2項所述之在半導體封裝件形成全表面包覆電磁干擾遮蔽層的方法,其中移除該 暫時性保護層之步驟係在該電磁干擾遮蔽層形成之後以加熱方式移除該暫時性保護層。
- 依據申請專利範圍第3項所述之在半導體封裝件形成全表面包覆電磁干擾遮蔽層的方法,其中該暫時性保護層之厚度係大於該電磁干擾遮蔽層之厚度。
- 依據申請專利範圍第3項所述之在半導體封裝件形成全表面包覆電磁干擾遮蔽層的方法,其中該暫時性保護層係為一有機保焊膜(Organic Solderability Preservatives,OSP),而上述移除該暫時性保護層之步驟係包含助焊劑之使用,在加熱下清潔該些外接端子之該些顯露表面。
- 依據申請專利範圍第1項所述之在半導體封裝件形成全表面包覆電磁干擾遮蔽層的方法,其中該些外接端子係為一導線架之複數個外引腳。
- 依據申請專利範圍第6項所述之在半導體封裝件形成全表面包覆電磁干擾遮蔽層的方法,其中該些外引腳係由該半導體封裝件之該些側面延伸而出。
- 依據申請專利範圍第6項所述之在半導體封裝件形成全表面包覆電磁干擾遮蔽層的方法,其中該半導體封裝件之該上表面、該下表面以及該些側面係皆由該封膠體所構成。
- 依據申請專利範圍第7項所述之在半導體封裝件形成全表面包覆電磁干擾遮蔽層的方法,其中該半導體封裝件係更包含複數個內引腳,其係密封在該封 膠體內且一體連接至該些外引腳,其中該晶片係承載於該些內引腳。
- 依據申請專利範圍第1項所述之在半導體封裝件形成全表面包覆電磁干擾遮蔽層的方法,其中該些外接端子係包含複數個銲球,其係設置於該半導體封裝件之該下表面,其中該半導體封裝件係更包含一基板,用以承載該晶片,其中該半導體封裝件之該上表面與大部份之該些側面係由該封膠體所構成,該半導體封裝件之該下表面係由該基板所構成。
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US20100207259A1 (en) * | 2008-02-05 | 2010-08-19 | Advanced Semiconductor Engineering, Inc. | Semiconductor device packages with electromagnetic interference shielding |
US20100224792A1 (en) * | 2009-03-03 | 2010-09-09 | Nan Zhang | Method for characterizing vibrational performance of charged particle beam microscope system and application thereof |
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US20010035571A1 (en) * | 1997-07-02 | 2001-11-01 | Corisis David J. | Lead frame assemblies with voltage reference plane and IC packages including same |
US20100207259A1 (en) * | 2008-02-05 | 2010-08-19 | Advanced Semiconductor Engineering, Inc. | Semiconductor device packages with electromagnetic interference shielding |
US20100224792A1 (en) * | 2009-03-03 | 2010-09-09 | Nan Zhang | Method for characterizing vibrational performance of charged particle beam microscope system and application thereof |
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