TWI394632B - 藉由添加銅以改善焊料互連 - Google Patents
藉由添加銅以改善焊料互連 Download PDFInfo
- Publication number
- TWI394632B TWI394632B TW099122029A TW99122029A TWI394632B TW I394632 B TWI394632 B TW I394632B TW 099122029 A TW099122029 A TW 099122029A TW 99122029 A TW99122029 A TW 99122029A TW I394632 B TWI394632 B TW I394632B
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- Taiwan
- Prior art keywords
- layer
- nickel
- copper
- bump
- sub
- Prior art date
Links
- 239000010949 copper Substances 0.000 title claims description 152
- 229910000679 solder Inorganic materials 0.000 title claims description 132
- 229910052802 copper Inorganic materials 0.000 title claims description 60
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 title claims description 57
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 135
- 229910000765 intermetallic Inorganic materials 0.000 claims description 52
- 229910052759 nickel Inorganic materials 0.000 claims description 47
- 239000011135 tin Substances 0.000 claims description 45
- 238000000034 method Methods 0.000 claims description 34
- 239000000758 substrate Substances 0.000 claims description 28
- 229910052751 metal Inorganic materials 0.000 claims description 21
- 239000002184 metal Substances 0.000 claims description 21
- 229910001128 Sn alloy Inorganic materials 0.000 claims description 8
- 229910052718 tin Inorganic materials 0.000 claims description 8
- 229910000881 Cu alloy Inorganic materials 0.000 claims description 7
- 229910052709 silver Inorganic materials 0.000 claims description 7
- 229910001316 Ag alloy Inorganic materials 0.000 claims description 4
- 230000008018 melting Effects 0.000 claims description 4
- 238000002844 melting Methods 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims 8
- 229910000990 Ni alloy Inorganic materials 0.000 claims 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims 2
- 239000004332 silver Substances 0.000 claims 1
- 230000008569 process Effects 0.000 description 14
- KDLHZDBZIXYQEI-UHFFFAOYSA-N palladium Substances [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 9
- 239000010931 gold Substances 0.000 description 8
- 150000001875 compounds Chemical class 0.000 description 7
- 238000009713 electroplating Methods 0.000 description 6
- 229910045601 alloy Inorganic materials 0.000 description 5
- 239000000956 alloy Substances 0.000 description 5
- 239000000203 mixture Substances 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 3
- 230000000670 limiting effect Effects 0.000 description 3
- 239000000155 melt Substances 0.000 description 3
- 239000007787 solid Substances 0.000 description 3
- 238000009736 wetting Methods 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 239000011230 binding agent Substances 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 239000002002 slurry Substances 0.000 description 2
- 229910017482 Cu 6 Sn 5 Inorganic materials 0.000 description 1
- -1 Cu 6 Sn 5 Chemical class 0.000 description 1
- 229910000978 Pb alloy Inorganic materials 0.000 description 1
- 238000007792 addition Methods 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000012217 deletion Methods 0.000 description 1
- 230000037430 deletion Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000004100 electronic packaging Methods 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000000383 hazardous chemical Substances 0.000 description 1
- 238000010348 incorporation Methods 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000002829 reductive effect Effects 0.000 description 1
- 239000006104 solid solution Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000010301 surface-oxidation reaction Methods 0.000 description 1
- 229910002058 ternary alloy Inorganic materials 0.000 description 1
- 238000004627 transmission electron microscopy Methods 0.000 description 1
Classifications
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
- B23K35/02—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by mechanical features, e.g. shape
- B23K35/0222—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by mechanical features, e.g. shape for use in soldering, brazing
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- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K2101/00—Articles made by soldering, welding or cutting
- B23K2101/36—Electric or electronic devices
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Description
本申請案基本上係關於電子封裝,及更具體而言覆晶裝配。
覆晶封裝係利用焊料將IC連接至該封裝。此等焊料互連稱為凸塊。傳統上凸塊係由Pb/Sn合金製成。然而,隨著限制鉛使用之法規之出現,電子工業被推向無鉛合金。例如,由歐盟(European Union)於2003年採用之Hazardous Substances(RoHS) directive法規將鉛於任何均質組分中之濃度限制為0.1%(1000 ppm)或更小。最普遍的無鉛凸塊合金係三元體Sn/Ag/Cu及二元體Sn/Ag。Sn/Ag合金通常係電鍍的,而Sn/Ag/Cu合金通常係經焊膏印刷。於電鍍Sn/Ag之情況中,凸塊下金屬化(UBM)一般係Ti/Cu/Ni三層體,就Sn/Ag/Cu合金而言,UBM一般係Al/Ni/Cu。
一態樣提供一種形成電子裝置之方法。提供一具有位於其上之一焊料凸塊墊及位於該焊料凸塊墊上之一含鎳層之電子裝置基板。該方法包括在該電子裝置經受回焊製程之前,於該含鎳層上形成一含銅層。
另一態樣提供一種電子裝置。該電子裝置包含一具有位於其上之一凸塊墊之電子裝置基板。含鎳層係位於該焊料凸塊墊上,及含銅層係位於該含鎳層上。
另一態樣提供一種形成電子裝置之方法。該方法包含提供一具有一位於其上之焊料凸塊之電子裝置基板。含銅層係形成於該焊料凸塊上。
以下將結合隨附圖式來予以說明。
於一些情況下,焊料凸塊會於電子裝置之設計使用壽命結束前失效。一部份失效係歸因於機械弱化區域因固態機構而於失效焊料凸塊中之形成。弱化區域會於(例如)來自於裝置裝配或由裝置操作期間之熱膨脹引起之殘餘機械應力下斷裂。然而,減少凸塊失效之習知方法具有數種缺點。
於一習知方法中,使Cu凸塊墊上之Ni層被製成充分薄以使焊料熔融物可完全移除一些位置中之Ni層,使底層Cu曝露於凸塊。將一部份Cu併入凸塊與墊之間之Sn/Cu IMC區域。於低濃度下,於IMC區域中之一部份Cu可具有益處。然而,由於Cu會與熔融焊料中之Sn及Ag快速反應,故難以控制溶於熔融物中之Cu之量。過度併入Cu會導致另一類可靠性問題。
於另一習知方法中,為避免Cu自墊損耗,於Cu墊頂部形成Ni/Au層或Ni/Pd/Au層。於此情況中,形成具有充足厚度之Ni及/或Pd層以保證Cu於回焊期間不曝露。雖然此方法降低與焊料凸塊中Cu濃度過大有關之可靠性問題,然而上述斷裂問題未得到改善。本文所述之實施例將解決習知技術之此等限制。
現已瞭解在回焊該焊料凸塊前,可藉由在焊料凸塊上或於連接該凸塊之凸塊墊上形成含銅層而以可控方式將Cu添加至Sn/Ag焊料凸塊。焊料熔融物會消耗至少一部份含銅層,於焊料凸塊中形成Sn/Ag/Cu(SAC)三元合金及於焊料凸塊與凸塊墊之間形成金屬間化合物(IMC)區域。該IMC區域相對於習知無鉛凸塊焊料連結具有改善凸塊與墊之間之連結之機械及電可靠性之機械特性。可預期此改善之特性降低凸塊失效之機率並提高經封裝之裝置之計畫操作使用壽命。
首先參見圖1,其顯示經裝配之電子裝置100。該裝置100包含一第一電子裝置100a及第二電子裝置100b。於一些實施例中,裝置100a係積體電路(IC)晶粒,且裝置100b係電子裝置封裝。於所顯示之實施例中,裝置100a係經翻轉且焊料凸塊110係位於裝置100a與裝置100b之間。於一些實施例中,焊料凸塊110符合RoHS標準。如本文及申請專利範圍中所使用,將符合RoHS之焊料凸塊視為無鉛。裝置100a、100b係藉由例如焊料回焊製程而連結,其中焊料凸塊110係經熔融並冷卻。依此組態連接電子裝置之製程統稱為「覆晶」裝配。
裝置100a包含一基板120及複數個焊料凸塊墊130。如本文及申請專利範圍中所使用,凸塊墊係經組態以與焊料凸塊形成連接且位於電子裝置基板上之金屬墊。該電子裝置可為,例如,IC晶粒或電子封裝。該墊之一側可為,例如,50 μm或更大,且可覆蓋有各種金屬層,如凸塊下金屬化、擴散阻障層、或氧化抑制層。於基板120之金屬互連頂層(未顯示)上形成焊料凸塊墊130。於一些實施例中,基板120係一積體電路,且可包含,例如,電晶體及金屬互連層。連接至墊130之金屬互連頂層可為I/O墊或多層互連堆疊之頂部處之互連層。
裝置100b包含一基板140及複數個凸塊墊150。於一些實施例中,裝置100b係一電子裝置封裝。基板140可包含,例如,封裝導體及將該等導體連接至凸塊墊150之信號路由跡線。基板140於裝置封裝基板中可包含多個信號路由層。信號路由層可經由,例如連接,連接至墊150。
圖2A及2B各顯示裝配前之凸塊墊150及一部份基板140之平面圖及截面視圖。如圖所示之墊150係形成並延伸於基板140之上表面上。其他所涵蓋之實施例包括彼等墊150之上表面約與基板140齊平。取決於用於形成裝置100b之加工技術,墊150可為(例如)Al或Cu墊。金屬層210係位於墊150上。使層210沉積或形成於墊150上,然後將焊料凸塊連接至墊150。雖然顯示金屬層210覆蓋墊150之頂部及側面,然而,於其他實施例中,其僅覆蓋墊150之頂部或僅覆蓋足以防止焊料凸塊110與墊150接觸之頂部150之一部份。此外,於金屬層210與墊150之間可存在額外金屬層(未顯示)。於一些情況中,此等金屬層可用於促進黏附或於金屬層210與墊150之間形成擴散阻障層。
如下文進一步描述,層210包括含銅子層及含鎳子層。層210可額外包括經選擇以將特性賦予焊料凸塊110與墊150之間之電及機械連接之一或多層金屬層。例如,層210可包括可改良焊料凸塊110之浸潤之犧牲金屬層,或抑制層210表面氧化之有機塗層。
圖3更詳細地顯示如本發明之一實施例中所組態之金屬層210。含銅子層310係位於焊料凸塊110'與含鎳子層320之間。於以下論述中,針對焊料凸塊110所使用之符號「'」標記係指在將裝置100a連接至裝置100b之前。如本文及申請專利範圍中所使用,含銅層可包括元素銅、含銅化合物,例如,含銅IMC,或非銅黏結劑。此外,含銅層可包含具有不同含銅組分之兩或更多層,例如,元素銅層及含銅IMC層。類似地,如本文及申請專利範圍中所使用,含鎳層可包括元素鎳或含鎳化合物,例如,含鎳IMC。此外,含鎳層可包含具有不同含鎳組分之兩或更多層,例如,元素鎳層及含鎳IMC層。簡明起見,於下文中將子層310稱為Cu子層,及將子層320稱為Ni子層,而不失一般性。
於所顯示之實施例中,Cu子層310係位於Ni子層320上,及子層320與凸塊110'之間。已知之覆晶製程於焊料凸塊與凸塊墊上之含鎳層之間不包含含銅層。Cu子層310具有厚度TCu
,其係經確定以提供於回焊後可於凸塊110中獲得約0.5重量%至約4重量%之Cu濃度之範圍內之Cu量。此態樣將更詳盡地論述如下。Ni子層320具有足以保證於回焊後子層320維持未受損之厚度TNi
,以使墊150不接觸熔融凸塊110。
參照圖3之實施例,視需要一或多個額外金屬層可位於Cu子層310與Ni子層320之間。例如,面層可包含此一或多層,包括,例如,Pd層、Au層或兩者。此等層某些時候係用於防止凸塊墊氧化或促進墊浸潤。如本文及申請專利範圍中所使用,Cu子層310係位於Ni子層320上,甚至當習慣上用作面層之額外金屬層(例如Au及/或Pd)係位於子層310、320之間時。
於以下論述之一些實施例中,可將含銅層沉積或形成於焊料凸塊110'上,然後實施裝配製程。於一些實施例中,在將凸塊110'連接至墊150之前,焊料凸塊110'係實質上不含Cu。實質上不含意指焊料凸塊110'中之Cu濃度不超過約0.1重量%。於一非限制性實例中,焊料凸塊110'於回焊前係約96.5重量% Sn/3.5重量% Ag(低共熔組合物)。由於存在形成於焊料凸塊上之含銅層,因此原本實質上不含Cu之焊料凸塊被視為含Cu。
圖4A顯示於形成焊料連結後,例如回焊後,墊150上之焊料凸塊110。焊料凸塊110之組分與焊料凸塊110'之組分不同,係因焊料凸塊110併入一部份金屬層210。金屬層210係非限制性地顯示為僅包含Cu子層310及Ni子層320。於回焊製程期間,熔融焊料與子層310、320之間之反應會產生含銅IMC區域410,同時焊料凸塊110'中之Sn及/或Ag會與金屬層210中之Ni及/或Cu反應。IMC可包含,例如,含有Cu、Sn、Ag及/或Ni之化合物。各化合物與構成元素之特徵化學計量有關。可預期藉由熔融物消耗焊料凸塊110與子層320之間之實質上所有的子層310並將其併入區域410及焊料凸塊110中。若存在,則亦消耗形成於Cu子層310上之浸潤層。Ni子層320實質上未受損,其意指,例如,Ni子層320之連續部分係位於區域410與墊150之間。
可藉由其中存在之各IMC區別區域410與焊料凸塊110。一般而言,如各種分析技術(例如,穿透式電子顯微鏡)所測定,可預期IMC區域410之邊界清晰。典型上,區域410具有佔焊料凸塊110約0.1%至10%之總質量。
圖4B更詳細地顯示IMC區域410。可預期與Ni子層320共用一界面之第一子區域420實質上係由Ni/Sn化合物(例如,Ni3
Sn4
)組成。可預期位於子區域420與凸塊110之間之第二子區域430實質上係由Cu/Sn化合物,例如,Cu6
Sn5
組成,以一部份Ni置換Cu。可將子區域430中之IMC稱為(Ni,Cu)/Sn化合物以反映一定量之Ni存在。然而,可預期子區域430中之Cu係由實質上少於50%之Ni構成,以使就此實施方式及申請專利範圍之目的而言,子區域430不為含鎳層。於子區域430中之Cu濃度可為,約55重量%至約65重量%的範圍內。
於各實施例中,及就申請專利範圍之目的而言,將子區域430視為含銅層,其反映其中之高Cu濃度。另一方面,不將焊料凸塊110視為含銅層。凸塊110具有小於約5重量%之銅濃度,且其中之銅一般係於固體溶液中且不形成含銅IMC。就任何含銅IMC於凸塊110中形成之程度而言,此IMC會廣泛分散且不形成連續層。
當熔融焊料凸塊110'經放置成與層210接觸時,子層310中之Cu會溶入焊料凸塊110'中並與Sn及/或Ag反應,藉此形成焊料凸塊110。可預期Cu於熔融焊料凸塊110中之擴散速率大於約1 μm/s。典型焊料回焊製程於凸塊裝配製程中將焊料凸塊110維持在大於約220℃之溫度下60至90秒。因此,可預期不與子區域中之IMC結合之子層310中之Cu與焊料凸塊110中之Sn及Ag形成SAC合金。可預期該合金於其中具有均勻的Cu分佈。當熔融焊料消耗Cu子層310時,焊料會接觸Ni子層320。焊料中之Sn與子層320中之Ni反應以於子區域420中形成Ni/Sn IMC,包括Ni3
Sn4
。
子區域420中之Ni/Sn IMC,例如,Ni3
Sn4
可隨著Ni自墊150及Sn自凸塊110擴散進入子區域420,而於裝置100之使用期間繼續形成。因此,子區域420之厚度會隨時間經過而增加。Ni/Sn IMC一般係呈脆性,且若子區域420變得充分厚,則子區域420會於應力下斷裂。該斷裂會導致裝置100於到達其額定使用壽命之前失效。
然而,與習知情況不同,認為子區域430之存在會抑制子區域420生長。據信子區域430中之Cu/Sn IMC亦會藉由固態機構隨時間經過而繼續形成。焊料凸塊110中之Cu於裝置100之使用壽命期間將Cu提供至子區域430,以使子區域430生長。子區域430可用作來自凸塊110之Sn之至少一部份吸入源,否則Sn會擴散進入子區域420。可預期限制Sn進入子區域420之可能性以限制子區域420之生長速率,藉此降低裝置100失效之機率。此外,可預期子區域430中之Cu/Sn IMC於機械上比子區域420之Ni/Sn IMC更堅固,以預期子區域430之生長不會不利地影響裝置100之可靠性。
於回焊前使焊料凸塊110'與Cu冶合不符合較佳製造方法。生產者極期望以低成本及高產出形成焊料凸塊110'之電鍍焊料。然而,Sn、Ag及Cu之電化學電位之固有差異會極大地阻礙具有穩定的Sn、Ag及Cu濃度之焊料凸塊形成。
本發明之實施例藉由提供Cu子層310作為Cu源然後裝配裝置100a、100b來克服此等缺陷。因此,凸塊110'可藉由習知製程(例如,電鍍)來形成,且冶合係於連接裝置100a、100b之回焊期間發生。
Cu子層310可藉由任何習知或新穎方法形成。於一些實施例中,子層310係藉由電鍍形成。於下文進一步論述之另一實施例中,子層310係藉由模版印刷含銅焊膏形成。子層310之厚度一般係由凸塊110中所需之Cu濃度確定。就各種形成方法而言Cu子層310之厚度可不同。例如,電鍍層一般具有大小超過墊150之尺度的極均勻厚度(100 μm)。由於預期熔融物消耗所有Cu,故熟習本技藝者可確定焊料凸塊110'之厚度、體積及組分。
於一非限制性實例中,就100 μm焊料凸塊110'而言,電鍍Cu子層310可具有0.5至2 μm之厚度。此厚度範圍可預期於凸塊110中獲得約0.5重量%至約4重量%之範圍內之Cu濃度。於一些情況中,以至少1 μm之厚度為較佳以考量,例如,焊料凸塊尺寸之變動。於一些情況中,可將Cu濃度限制為3重量%或更小以盡可能減小凸塊因過量Cu而失效之可能性。於本文之一些實施例中,子層310之厚度將可利用之Cu限制至小於Cu於凸塊110之焊料組合物中之溶解度極限。因此,可消除上述因凸塊110中過量之Cu濃度而使裝置100可靠性降低。
可預期含鎳子層320中之Ni溶解進入凸塊110中之速率遠小於Cu之速率,例如,比其10%小。因此,子層320較Cu子層310薄,且仍防止熔融焊料接觸墊150。所消耗之子層320之總量一般亦為回焊溫度及時間之函數。於一些實施例中,子層320之厚度足以在回焊製程之容許極限所預期之最大時間及溫度下維持不受損。然而,一般而言,宜限制子層320之厚度以控制封裝製程之總成本。於一些實施例中,回焊前之子層320之厚度比Ni之最大預期移除量大至少約20%。
可預期於上述回焊製程期間消耗約50 nm之Ni子層320。因此,於一些實施例中,子層320具有約0.5 μm之厚度,其反映上述因素之平衡。習慣上可藉由例如物理氣相沉積製程來形成子層320。
如上所述,層210於子層310、320之間可包含,例如,Pd層及/或Au層。當存在時,習慣上可形成此等額外層。於此等實施例中,可預期完全消耗Cu、Au及Pd層,及如上所述般部份地消耗Ni層。
圖5A及5B各顯示藉由模版印刷於Ni子層320上形成Cu子層510之凸塊墊150之一實施例之平面圖及截面視圖。Cu子層510之厚度可與Cu子層310之厚度不同。例如,由於Cu顆粒之間之自由空間及存在一載體液體或黏結劑,印刷於Ni子層320上之含銅焊膏中之Cu密度可係小於電鍍膜中之Cu密度。此外,焊膏之厚度均勻性可比電鍍Cu之厚度均勻性低。於一些情況中,如上所述,所印刷之Cu子層310可不完全覆蓋凸塊墊150。於此情況中,藉由確定焊膏中之Cu濃度可確定於焊料凸塊110中提供所需之Cu濃度之焊膏層之體積。
圖6A及6B顯示將Cu提供至焊料凸塊110之其他實施例。於圖6A中,於凸塊110'上形成含銅層610。典型上,凸塊110'於含銅層610形成期間維持固態,然而並不一定要如此。於一些實施例中,覆蓋有層610之凸塊110'係與凸塊墊(如凸塊墊150)上之含鎳層接觸。當回焊凸塊110'時,層610以類似於在Ni子層320上形成Cu子層310之實施例之方式將Cu提供至凸塊110。可確定於凸塊110中獲得所需Cu濃度之層610之厚度。圖6A之實施例可於焊料凸塊110中獲得較某些其他實施例更均勻之Cu濃度,這係因Cu擴散至其整個表面上之焊料凸塊110之故。
含銅層610可藉由,例如,電鍍形成於焊料凸塊110'上。於非限制性實例中,將焊料凸塊110'加工成具有100 μm直徑之球形。介於約15 nm至約120 nm之範圍內之層610之厚度可提供可於回焊後於凸塊110中提供介於約0.5%至約4%之範圍內之Cu濃度。可預期約30 nm之厚度之層610於焊料凸塊110中獲得約1重量%之平均濃度。彼等熟習本技藝者可確定於焊料凸塊110中產生所需Cu濃度之層610厚度。
圖6B顯示含銅層係形成於焊料凸塊110'上之Cu焊膏之凸緣620之實施例。該凸緣620可藉由例如將焊料凸塊陣列浸入含銅漿液中而施加於平坦表面上。例如,該漿液可為模版印刷焊膏。此外,當凸緣620與Ni層接觸並回焊時,可預期凸緣620提供Cu以形成如上所述之IMC區域410。此實施例可於回焊期間提供特別經濟的方法以將Cu提供至凸塊110'。
現參照圖7,其顯示本發明之方法700。於步驟710中,提供覆蓋有凸塊墊之電子裝置基板。該裝置可為,例如,IC晶粒。如本文及申請專利範圍中所使用,「提供」意指可裝置、基板、結構元件等可藉由個人或企業實體實施本發明方法製得,或自包括另一個人或企業實體之非個人或實體之來源獲得。凸塊墊上包含一含鎳層,如Ni子層320。於一些實施例中,含鎳層上具有一Au及/或Pd層。
於步驟720中,於該含鎳層上形成含銅層,然後另電子裝置經由回焊製程。含銅層習慣上係如上所述般,例如,藉由電鍍或模版印刷形成。熟習本技藝者將瞭解此等實例並非囊括本發明範圍內之其他等效方法。
於一些實施例中,方法700接以步驟730,其中於凸塊墊上形成焊料凸塊。可熔融凸塊,藉此於凸塊與含鎳層之間形成(Ni,Cu)/Sn IMC區域。該IMC區域可含有介於約55重量%至約65重量%之範圍內之濃度之Cu。此熔融可將電子裝置與裝置封裝連結。凸塊可位於IC晶粒或裝置封裝基板上。焊料凸塊於熔融前可實質上不含Cu,例如,由Sn/Ag焊料合金形成。可藉由例如習知焊料回焊製程來予以熔融。焊料熔融物可預期大大地消耗凸塊與含鎳層之間之任何層,例如金或鈀,並使其等溶解進入焊料熔融物中。於一些實施例中焊料凸塊於熔融後包含具有約0.5重量%至約4重量%之範圍內之濃度之Cu。於一些實施例中,焊料凸塊具有約100 μm之直徑,且含銅層具有約0.5 μm至約2 μm之範圍內的厚度。
最後,圖8顯示,如圖6A及6B之實施例所述般,於焊料凸塊上形成含銅層之方法800。於步驟810中,提供其上配置有焊料凸塊墊之電子裝置基板。此基板可為,例如,一積體電路或裝置封裝。於步驟820中,於焊料凸塊上形成含銅層。
於一些實施例中,方法800繼續至步驟830,其中使焊料凸塊熔融,藉此於焊料凸塊與凸塊墊之間形成(Ni,Cu)/Sn IMC區域。可使焊料凸塊與含鎳層接觸,然後加以熔融。視需要,可於焊料凸塊上形成含銅層後,但使焊料凸塊與含鎳層接觸之前回焊焊料凸塊。IMC區域中之Cu濃度可介於約55重量%至約65重量%之範圍內。於一些實施例中,該基板係IC晶粒,而於一些其他實施例中,該基板係一裝置封裝基板。含銅層可,例如,藉由電鍍或由銅焊膏形成。於一些實施例中,將Cu併入凸塊之前,凸塊上形成之Cu質量係佔焊料凸塊之質量約0.5%至約4%的範圍內。
熟習本申請案有關技藝者將瞭解可對所述之實施例實施其他添加、刪減、替換及修改。
100...電子裝置
100a...電子裝置
100b...電子裝置
110...焊料凸塊
110'...焊料凸塊
120...基板
130...焊料凸塊墊
140...基板
150...焊料凸塊墊
210...金屬層
310...含銅子層
320...含鎳子層
410...金屬間化合物區域
420...第一子區域
430...第二子區域
510...銅子層
610...含銅層
620...凸緣
圖1顯示具有根據本發明形成之焊料凸塊之電子裝置;
圖2A及2B各顯示本發明之凸塊墊之俯視圖及截面圖;
圖3提供凸塊墊之詳細視圖;
圖4A顯示一焊料凸塊及一凸塊墊,其間具有一金屬間化合物(IMC)區域;
圖4B顯示IMC區域之詳細視圖;
圖5A及5B各顯示本發明之凸塊墊之俯視圖及截面圖;
圖6A及6B顯示形成於焊料凸塊上之含銅層;及
圖7及8顯示本發明之方法。
100...電子裝置
100a...電子裝置
100b...電子裝置
110...焊料凸塊
120...基板
130...焊料凸塊墊
140...基板
150...焊料凸塊墊
Claims (10)
- 一種形成一電子裝置之方法,其包含:提供一電子裝置基板,其具有一位於其上之凸塊墊,該凸塊墊包括有包含鋁或銅的側表面及一平坦頂部表面;提供一位於該凸塊墊上且與該凸塊墊之該側表面及頂部表面形成一界面之含鎳層;提供一位於該含鎳層之上的焊料凸塊,其中該焊料凸塊係由一銀、錫及銅之合金所組成;及在該含鎳層及該焊料凸塊之間且與該含鎳層及該焊料凸塊相接觸之處形成一金屬間化合物層(intermetallic compound layer),其中該金屬間化合物層包括:一相鄰於該焊料凸塊之第一金屬間化合物子層(sublayer),該第一金屬間化合物子層係由一鎳、銅及錫之合金所組成,及一相鄰於該第一金屬間化合物子層及該含鎳層之第二金屬間化合物子層,該第二金屬間化合物子層係由一鎳與錫之合金所組成。
- 如請求項1之方法,其中該含鎳層係一元素鎳層(elemental nickel layer)。
- 如請求項1之方法,其中形成該金屬間化合物層包括熔融與一含銅層接觸之該焊料凸塊,其中該金屬間化合物層具有一約55重量%至約65重量%之範圍內之銅濃度。
- 如請求項1之方法,其中該金屬間化合物層係位於該含 鎳層之上且與該含鎳層形成一界面。
- 一種電子裝置,其包含:一電子裝置基板,其具有一位於其上之凸塊墊,該凸塊墊包括有包含鋁或銅的側表面及一平坦頂部表面;一位於該凸塊墊上且與該凸塊墊之該側表面及頂部表面形成一界面之含鎳層;一位於該含鎳層之上的焊料凸塊,其中該焊料凸塊係由一銀、錫及銅之合金所組成;及位於該含鎳層及該焊料凸塊之間且與該含鎳層及該焊料凸塊相接觸之一金屬間化合物層,其中該金屬間化合物層包括:一相鄰於該焊料凸塊之第一金屬間化合物子層,該第一金屬間化合物子層係由一鎳、銅及錫之合金所組成,及一相鄰於該第一金屬間化合物子層及該含鎳層之第二金屬間化合物子層,該第二金屬間化合物子層係由一鎳與錫之合金所組成。
- 如請求項5之裝置,其中該含鎳層係一元素鎳層。
- 如請求項5之裝置,其中該焊料凸塊之內之該銅具有約0.5重量%至約4重量%之範圍內之一濃度。
- 如請求項5之裝置,其中該金屬間化合物層具有約55重量%至約65重量%之範圍內之一銅濃度。
- 如請求項5之裝置,其中該金屬間化合物層係位於該含鎳層之上且與該含鎳層形成一界面。
- 如請求項5之裝置,其中該第一金屬間化合物子層之該鎳、銅及錫之合金包括約五個該錫之原子比約六個該鎳加上該銅之原子之原子比例,且該銅原子數目較該鎳原子數目為多。
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Also Published As
Publication number | Publication date |
---|---|
US8580621B2 (en) | 2013-11-12 |
EP2276063A2 (en) | 2011-01-19 |
CN101958259A (zh) | 2011-01-26 |
TW201107071A (en) | 2011-03-01 |
US20130149857A1 (en) | 2013-06-13 |
CN101958259B (zh) | 2014-09-03 |
KR101704030B1 (ko) | 2017-02-07 |
KR20110006615A (ko) | 2011-01-20 |
JP2011023721A (ja) | 2011-02-03 |
EP2276063A3 (en) | 2011-04-20 |
JP5604665B2 (ja) | 2014-10-08 |
US20110006415A1 (en) | 2011-01-13 |
US8378485B2 (en) | 2013-02-19 |
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