TWI391993B - 形成具矽化物層之半導體裝置之方法 - Google Patents
形成具矽化物層之半導體裝置之方法 Download PDFInfo
- Publication number
- TWI391993B TWI391993B TW094115820A TW94115820A TWI391993B TW I391993 B TWI391993 B TW I391993B TW 094115820 A TW094115820 A TW 094115820A TW 94115820 A TW94115820 A TW 94115820A TW I391993 B TWI391993 B TW I391993B
- Authority
- TW
- Taiwan
- Prior art keywords
- layer
- metal
- forming
- metal telluride
- telluride
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
- H10D30/0213—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation providing different silicide thicknesses on gate electrodes and on source regions or drain regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
- H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
-
- H10D64/0112—
-
- H10D64/0131—
-
- H10D64/01312—
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3215—Doping the layers
- H01L21/32155—Doping polycristalline - or amorphous silicon layers
-
- H10P32/302—
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Chemical & Material Sciences (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/854,389 US7235471B2 (en) | 2004-05-26 | 2004-05-26 | Method for forming a semiconductor device having a silicide layer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW200618067A TW200618067A (en) | 2006-06-01 |
| TWI391993B true TWI391993B (zh) | 2013-04-01 |
Family
ID=35461084
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW094115820A TWI391993B (zh) | 2004-05-26 | 2005-05-16 | 形成具矽化物層之半導體裝置之方法 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US7235471B2 (enExample) |
| JP (1) | JP5103174B2 (enExample) |
| CN (1) | CN100541738C (enExample) |
| TW (1) | TWI391993B (enExample) |
| WO (1) | WO2005119752A1 (enExample) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100587686B1 (ko) * | 2004-07-15 | 2006-06-08 | 삼성전자주식회사 | 질화 티타늄막 형성방법 및 이를 이용한 커패시터 제조방법 |
| US7538026B1 (en) | 2005-04-04 | 2009-05-26 | Advanced Micro Devices, Inc. | Multilayer low reflectivity hard mask and process therefor |
| JP2007048893A (ja) * | 2005-08-09 | 2007-02-22 | Fujifilm Corp | 固体撮像素子およびその製造方法 |
| JP2010003742A (ja) * | 2008-06-18 | 2010-01-07 | Fujitsu Microelectronics Ltd | 半導体装置、及び薄膜キャパシタの製造方法 |
| KR101037495B1 (ko) * | 2008-07-31 | 2011-05-26 | 주식회사 하이닉스반도체 | 고집적 반도체 장치의 제조 방법 및 반도체 장치 |
| US8216436B2 (en) * | 2008-08-25 | 2012-07-10 | The Trustees Of Boston College | Hetero-nanostructures for solar energy conversions and methods of fabricating same |
| EP2324487A4 (en) * | 2008-08-25 | 2014-07-02 | Trustees Boston College | METHOD FOR PRODUCING COMPLEX TWO-DIMENSIONAL CONDUCTIVE SILICIDES |
| US20170170016A1 (en) * | 2015-12-14 | 2017-06-15 | Globalfoundries Inc. | Multiple patterning method for substrate |
| US11424338B2 (en) | 2020-03-31 | 2022-08-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Metal source/drain features |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6306698B1 (en) * | 2000-04-25 | 2001-10-23 | Advanced Micro Devices, Inc. | Semiconductor device having metal silicide regions of differing thicknesses above the gate electrode and the source/drain regions, and method of making same |
| US6657244B1 (en) * | 2002-06-28 | 2003-12-02 | International Business Machines Corporation | Structure and method to reduce silicon substrate consumption and improve gate sheet resistance during silicide formation |
Family Cites Families (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6266679A (ja) * | 1985-09-19 | 1987-03-26 | Fujitsu Ltd | 半導体装置の製造方法 |
| JPS63306665A (ja) * | 1987-06-08 | 1988-12-14 | Nippon Telegr & Teleph Corp <Ntt> | 絶縁ゲ−ト型電界効果トランジスタおよびその製造方法 |
| JPH088317B2 (ja) * | 1990-04-24 | 1996-01-29 | 株式会社東芝 | 半導体記憶装置及びその製造方法 |
| JP3770954B2 (ja) * | 1995-11-13 | 2006-04-26 | エイ・ティ・アンド・ティ・コーポレーション | 装置の製造方法 |
| US6156632A (en) * | 1997-08-15 | 2000-12-05 | Micron Technology, Inc. | Method of forming polycide structures |
| JP4538693B2 (ja) * | 1998-01-26 | 2010-09-08 | ソニー株式会社 | メモリ素子およびその製造方法 |
| US6107211A (en) * | 1999-04-26 | 2000-08-22 | Vanguard International Semiconductor Corporation | Split polysilicon process in CMOS image integrated circuit |
| US20020132478A1 (en) * | 1999-06-29 | 2002-09-19 | Tinghao Frank Wang | Method for selectively etching silicon and/or metal silicides |
| US6391767B1 (en) * | 2000-02-11 | 2002-05-21 | Advanced Micro Devices, Inc. | Dual silicide process to reduce gate resistance |
| KR100327347B1 (en) * | 2000-07-22 | 2002-03-06 | Samsung Electronics Co Ltd | Metal oxide semiconductor field effect transistor having reduced resistance between source and drain and fabricating method thereof |
| JP3676276B2 (ja) * | 2000-10-02 | 2005-07-27 | 松下電器産業株式会社 | 半導体装置及びその製造方法 |
| JP2003077900A (ja) * | 2001-09-06 | 2003-03-14 | Hitachi Ltd | 半導体装置の製造方法 |
| US7449385B2 (en) * | 2002-07-26 | 2008-11-11 | Texas Instruments Incorporated | Gate dielectric and method |
| US6787864B2 (en) * | 2002-09-30 | 2004-09-07 | Advanced Micro Devices, Inc. | Mosfets incorporating nickel germanosilicided gate and methods for their formation |
| CN1219316C (zh) * | 2002-10-16 | 2005-09-14 | 上海宏力半导体制造有限公司 | 可改善接面电性特性的自行对准金属硅化物的制造方法 |
| US6867130B1 (en) * | 2003-05-28 | 2005-03-15 | Advanced Micro Devices, Inc. | Enhanced silicidation of polysilicon gate electrodes |
| US20040238876A1 (en) * | 2003-05-29 | 2004-12-02 | Sunpil Youn | Semiconductor structure having low resistance and method of manufacturing same |
-
2004
- 2004-05-26 US US10/854,389 patent/US7235471B2/en not_active Expired - Fee Related
-
2005
- 2005-04-26 WO PCT/US2005/014324 patent/WO2005119752A1/en not_active Ceased
- 2005-04-26 JP JP2007515098A patent/JP5103174B2/ja not_active Expired - Fee Related
- 2005-04-26 CN CNB2005800171377A patent/CN100541738C/zh not_active Expired - Fee Related
- 2005-05-16 TW TW094115820A patent/TWI391993B/zh not_active IP Right Cessation
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6306698B1 (en) * | 2000-04-25 | 2001-10-23 | Advanced Micro Devices, Inc. | Semiconductor device having metal silicide regions of differing thicknesses above the gate electrode and the source/drain regions, and method of making same |
| US6657244B1 (en) * | 2002-06-28 | 2003-12-02 | International Business Machines Corporation | Structure and method to reduce silicon substrate consumption and improve gate sheet resistance during silicide formation |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2008500728A (ja) | 2008-01-10 |
| WO2005119752A1 (en) | 2005-12-15 |
| US20050277275A1 (en) | 2005-12-15 |
| CN100541738C (zh) | 2009-09-16 |
| US7235471B2 (en) | 2007-06-26 |
| TW200618067A (en) | 2006-06-01 |
| CN1961411A (zh) | 2007-05-09 |
| JP5103174B2 (ja) | 2012-12-19 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MM4A | Annulment or lapse of patent due to non-payment of fees |