TWI381515B - 偏位積體電路封裝層疊堆疊系統 - Google Patents

偏位積體電路封裝層疊堆疊系統 Download PDF

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Publication number
TWI381515B
TWI381515B TW095117222A TW95117222A TWI381515B TW I381515 B TWI381515 B TW I381515B TW 095117222 A TW095117222 A TW 095117222A TW 95117222 A TW95117222 A TW 95117222A TW I381515 B TWI381515 B TW I381515B
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TW
Taiwan
Prior art keywords
base substrate
package
integrated circuit
base
top surface
Prior art date
Application number
TW095117222A
Other languages
English (en)
Chinese (zh)
Other versions
TW200707700A (en
Inventor
沈一權
韓丙濬
鄒勝源
Original Assignee
星科金朋有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
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Application filed by 星科金朋有限公司 filed Critical 星科金朋有限公司
Publication of TW200707700A publication Critical patent/TW200707700A/zh
Application granted granted Critical
Publication of TWI381515B publication Critical patent/TWI381515B/zh

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H10W74/117—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431—Details of mounted components
    • H05K2201/10507—Involving several components
    • H05K2201/10515—Stacked components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10734—Ball grid array [BGA]; Bump grid array
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5524—Materials of bond wires comprising metals or metalloids, e.g. silver comprising aluminium [Al]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/28—Configurations of stacked chips the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/291—Configurations of stacked chips characterised by containers, encapsulations, or other housings for the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/732—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/752—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
TW095117222A 2005-05-16 2006-05-16 偏位積體電路封裝層疊堆疊系統 TWI381515B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US59488705P 2005-05-16 2005-05-16
US11/383,407 US7746656B2 (en) 2005-05-16 2006-05-15 Offset integrated circuit package-on-package stacking system

Publications (2)

Publication Number Publication Date
TW200707700A TW200707700A (en) 2007-02-16
TWI381515B true TWI381515B (zh) 2013-01-01

Family

ID=37418900

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095117222A TWI381515B (zh) 2005-05-16 2006-05-16 偏位積體電路封裝層疊堆疊系統

Country Status (4)

Country Link
US (1) US7746656B2 (https=)
JP (1) JP5052037B2 (https=)
KR (1) KR101130330B1 (https=)
TW (1) TWI381515B (https=)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4828202B2 (ja) * 2005-10-20 2011-11-30 ルネサスエレクトロニクス株式会社 モジュール半導体装置
JP2007116027A (ja) * 2005-10-24 2007-05-10 Elpida Memory Inc 半導体装置の製造方法および半導体装置
US8110899B2 (en) * 2006-12-20 2012-02-07 Intel Corporation Method for incorporating existing silicon die into 3D integrated stack
US8043343B2 (en) * 2007-06-28 2011-10-25 Zimmer Spine, Inc. Stabilization system and method
US7872340B2 (en) * 2007-08-31 2011-01-18 Stats Chippac Ltd. Integrated circuit package system employing an offset stacked configuration
US7812435B2 (en) * 2007-08-31 2010-10-12 Stats Chippac Ltd. Integrated circuit package-in-package system with side-by-side and offset stacking
US7781261B2 (en) * 2007-12-12 2010-08-24 Stats Chippac Ltd. Integrated circuit package system with offset stacking and anti-flash structure
US8084849B2 (en) * 2007-12-12 2011-12-27 Stats Chippac Ltd. Integrated circuit package system with offset stacking
US7985628B2 (en) * 2007-12-12 2011-07-26 Stats Chippac Ltd. Integrated circuit package system with interconnect lock
US8536692B2 (en) * 2007-12-12 2013-09-17 Stats Chippac Ltd. Mountable integrated circuit package system with mountable integrated circuit die
US8067828B2 (en) * 2008-03-11 2011-11-29 Stats Chippac Ltd. System for solder ball inner stacking module connection
US20090243069A1 (en) * 2008-03-26 2009-10-01 Zigmund Ramirez Camacho Integrated circuit package system with redistribution
CN101562952B (zh) * 2008-04-18 2012-04-11 富葵精密组件(深圳)有限公司 线路基板、线路基板的制作方法及电路板的制作方法
KR20100009055A (ko) * 2008-07-17 2010-01-27 삼성전자주식회사 좁은 폭의 쏘우라인을 위한 인쇄회로기판 및 이를 포함하는반도체 패키지
US9293385B2 (en) * 2008-07-30 2016-03-22 Stats Chippac Ltd. RDL patterning with package on package system
US8406004B2 (en) 2008-12-09 2013-03-26 Stats Chippac Ltd. Integrated circuit packaging system and method of manufacture thereof
US7785925B2 (en) * 2008-12-19 2010-08-31 Stats Chippac Ltd. Integrated circuit packaging system with package stacking and method of manufacture thereof
US7968995B2 (en) * 2009-06-11 2011-06-28 Stats Chippac Ltd. Integrated circuit packaging system with package-on-package and method of manufacture thereof
US8518749B2 (en) 2009-06-22 2013-08-27 Stats Chippac, Ltd. Semiconductor device and method of forming prefabricated heat spreader frame with embedded semiconductor die
US10163877B2 (en) * 2011-11-07 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. System in package process flow
WO2013153742A1 (ja) * 2012-04-11 2013-10-17 パナソニック株式会社 半導体装置
US9029234B2 (en) 2012-05-15 2015-05-12 International Business Machines Corporation Physical design symmetry and integrated circuits enabling three dimentional (3D) yield optimization for wafer to wafer stacking
US9041176B2 (en) 2012-10-08 2015-05-26 Qualcomm Incorporated Hybrid semiconductor module structure
KR20160123890A (ko) 2015-04-17 2016-10-26 에스케이하이닉스 주식회사 검증용 인터포저
JP2017022352A (ja) * 2015-07-15 2017-01-26 富士通株式会社 半導体装置

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6433412B2 (en) * 2000-03-17 2002-08-13 Hitachi, Ltd. Semiconductor device and a method of manufacturing the same
US20040090759A1 (en) * 2002-10-24 2004-05-13 Jin-Ho Kim Multi-package stack module

Family Cites Families (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5579207A (en) * 1994-10-20 1996-11-26 Hughes Electronics Three-dimensional integrated circuit stacking
JPH08222692A (ja) 1995-02-09 1996-08-30 Hitachi Ltd 複合形半導体装置およびその実装構造体並びにその実装方法
US5907903A (en) * 1996-05-24 1999-06-01 International Business Machines Corporation Multi-layer-multi-chip pyramid and circuit board structure and method of forming same
US5748452A (en) * 1996-07-23 1998-05-05 International Business Machines Corporation Multi-electronic device package
US5986209A (en) * 1997-07-09 1999-11-16 Micron Technology, Inc. Package stack via bottom leaded plastic (BLP) packaging
JP3644662B2 (ja) * 1997-10-29 2005-05-11 株式会社ルネサステクノロジ 半導体モジュール
JP2000208698A (ja) * 1999-01-18 2000-07-28 Toshiba Corp 半導体装置
US6207474B1 (en) * 1998-03-09 2001-03-27 Micron Technology, Inc. Method of forming a stack of packaged memory die and resulting apparatus
US5854507A (en) * 1998-07-21 1998-12-29 Hewlett-Packard Company Multiple chip assembly
JP3767246B2 (ja) * 1999-05-26 2006-04-19 富士通株式会社 複合モジュール及びプリント回路基板ユニット
JP2001044362A (ja) 1999-07-27 2001-02-16 Mitsubishi Electric Corp 半導体装置の実装構造および実装方法
JP3798597B2 (ja) * 1999-11-30 2006-07-19 富士通株式会社 半導体装置
US6605875B2 (en) * 1999-12-30 2003-08-12 Intel Corporation Integrated circuit die having bond pads near adjacent sides to allow stacking of dice without regard to dice size
US6731009B1 (en) * 2000-03-20 2004-05-04 Cypress Semiconductor Corporation Multi-die assembly
US6518659B1 (en) * 2000-05-08 2003-02-11 Amkor Technology, Inc. Stackable package having a cavity and a lid for an electronic device
US6667544B1 (en) * 2000-06-30 2003-12-23 Amkor Technology, Inc. Stackable package having clips for fastening package and tool for opening clips
US7423336B2 (en) * 2002-04-08 2008-09-09 Micron Technology, Inc. Bond pad rerouting element, rerouted semiconductor devices including the rerouting element, and assemblies including the rerouted semiconductor devices
JP4601892B2 (ja) * 2002-07-04 2010-12-22 ラムバス・インコーポレーテッド 半導体装置および半導体チップのバンプ製造方法
US20040021230A1 (en) * 2002-08-05 2004-02-05 Macronix International Co., Ltd. Ultra thin stacking packaging device
JP2004071947A (ja) * 2002-08-08 2004-03-04 Renesas Technology Corp 半導体装置
US6798057B2 (en) * 2002-11-05 2004-09-28 Micron Technology, Inc. Thin stacked ball-grid array package
JP4110992B2 (ja) * 2003-02-07 2008-07-02 セイコーエプソン株式会社 半導体装置、電子デバイス、電子機器、半導体装置の製造方法および電子デバイスの製造方法
JP4408636B2 (ja) * 2003-02-28 2010-02-03 三洋電機株式会社 回路装置およびその製造方法
JP4069771B2 (ja) * 2003-03-17 2008-04-02 セイコーエプソン株式会社 半導体装置、電子機器および半導体装置の製造方法
TW576549U (en) * 2003-04-04 2004-02-11 Advanced Semiconductor Eng Multi-chip package combining wire-bonding and flip-chip configuration
US6853064B2 (en) * 2003-05-12 2005-02-08 Micron Technology, Inc. Semiconductor component having stacked, encapsulated dice
JP3951966B2 (ja) * 2003-05-30 2007-08-01 セイコーエプソン株式会社 半導体装置
JP4324773B2 (ja) 2003-09-24 2009-09-02 セイコーエプソン株式会社 半導体装置の製造方法
US7030469B2 (en) * 2003-09-25 2006-04-18 Freescale Semiconductor, Inc. Method of forming a semiconductor package and structure thereof
JP2005123463A (ja) * 2003-10-17 2005-05-12 Seiko Epson Corp 半導体装置及びその製造方法、半導体装置モジュール、回路基板並びに電子機器
US7095104B2 (en) * 2003-11-21 2006-08-22 International Business Machines Corporation Overlap stacking of center bus bonded memory chips for double density and method of manufacturing the same
US7091581B1 (en) * 2004-06-14 2006-08-15 Asat Limited Integrated circuit package and process for fabricating the same
JP2006186136A (ja) * 2004-12-28 2006-07-13 Toshiba Corp 両面部品実装回路基板及びその製造方法
US7312519B2 (en) * 2006-01-12 2007-12-25 Stats Chippac Ltd. Stacked integrated circuit package-in-package system
US7420269B2 (en) * 2006-04-18 2008-09-02 Stats Chippac Ltd. Stacked integrated circuit package-in-package system
US7535086B2 (en) * 2006-08-03 2009-05-19 Stats Chippac Ltd. Integrated circuit package-on-package stacking system
US7772683B2 (en) * 2006-12-09 2010-08-10 Stats Chippac Ltd. Stacked integrated circuit package-in-package system
US7635913B2 (en) * 2006-12-09 2009-12-22 Stats Chippac Ltd. Stacked integrated circuit package-in-package system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6433412B2 (en) * 2000-03-17 2002-08-13 Hitachi, Ltd. Semiconductor device and a method of manufacturing the same
US20040090759A1 (en) * 2002-10-24 2004-05-13 Jin-Ho Kim Multi-package stack module

Also Published As

Publication number Publication date
JP2006324666A (ja) 2006-11-30
KR20060118364A (ko) 2006-11-23
TW200707700A (en) 2007-02-16
US20060256525A1 (en) 2006-11-16
KR101130330B1 (ko) 2012-03-26
JP5052037B2 (ja) 2012-10-17
US7746656B2 (en) 2010-06-29

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