JP5052037B2 - オフセット集積回路パッケージオンパッケージ積層システム - Google Patents
オフセット集積回路パッケージオンパッケージ積層システム Download PDFInfo
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- JP5052037B2 JP5052037B2 JP2006136761A JP2006136761A JP5052037B2 JP 5052037 B2 JP5052037 B2 JP 5052037B2 JP 2006136761 A JP2006136761 A JP 2006136761A JP 2006136761 A JP2006136761 A JP 2006136761A JP 5052037 B2 JP5052037 B2 JP 5052037B2
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
- H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10431—Details of mounted components
- H05K2201/10507—Involving several components
- H05K2201/10515—Stacked components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10734—Ball grid array [BGA]; Bump grid array
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- H—ELECTRICITY
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
- H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
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- Engineering & Computer Science (AREA)
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
この出願は、2005年5月16日に出願された米国仮特許出願連続番号第60/594,887号の利益を主張する。
この発明は概して集積回路パッケージシステムに関し、より特定的には、積み重ねられたパッケージを有する集積回路パッケージシステムのためのシステムのためのシステムに関する。
集積回路を他の回路と接続するために、集積回路をリードフレームまたは基板に取付けることが一般的である。各々の集積回路は、極めて高純度の金またはアルミニウムのワイヤを使用してリードフレームのリードフィンガーパッドに個々に接続されるボンディングパッドを有する。このアセンブリは、次いで、成形されたプラスチックまたはセラミックの本体にアセンブリを個々に封入することによってパッケージ化されて、集積回路パッケージを作る。
この発明は、ベース基板を設けることと、コンタクトパッドのアレイをベース基板上に設けることと、能動構成要素および任意の受動構成要素をベース基板に取付けることと、モールドキャップをベース基板に射出することと、オフセットパッケージをベース基板およびモールドキャップに取付けることと、パッケージオンパッケージをベース基板から切離すこととを含むオフセット集積回路パッケージオンパッケージ積層システムを提供する。
以下の実施例は、当業者がこの発明をなし、使用することができるように十分詳細に記載される。この開示に基づいて他の実施例が明らかであろうということが理解されるべきであり、この発明の範囲から逸脱することなくプロセスまたは機械的な変更がなされ得ることが理解されるべきである。
原理的な利点は、この発明が印刷回路基板上でさらなる空間を消費することなく集積回路の密度の増加をもたらすことである。
104 ディスクリート構成要素
106 モールドキャップ
108 オフセットパッケージ
110 切離し線
112 セクション
Claims (11)
- 集積回路パッケージオンパッケージ積層システムを製造する方法であって、
ベース基板を設けることと、
コンタクトパッドのアレイを前記ベース基板上に設けることと、
能動構成要素を前記ベース基板に取付けることと、
モールドキャップを前記ベース基板の中央部上に形成することと、
複数の上部パッケージを前記ベース基板の周縁部に沿うように前記ベース基板と前記モールドキャップに取付けることとを含み、前記モールドキャップの上部面の一部であって、前記ベース基板の周縁部側に位置する部分を露出したままにすることを含み、前記方法はさらに、
上部パッケージ間の前記モールドキャップと前記ベース基板とを切断することでパッケージオンパッケージを切離すことを含む、方法。 - 厚みの異なる部分を有するモールドキャップを前記ベース基板上に設けることをさらに含む、請求項1に記載の方法。
- 前記上部パッケージと前記モールドキャップの薄肉部との間に隙間充填剤を与えることをさらに含む、請求項1に記載の方法。
- 前記上部パッケージと前記ベース基板上のコンタクトパッドの前記アレイとの間にシステム相互接続部を設けることをさらに含む、請求項1に記載の方法。
- 前記モールドキャップと前記上部パッケージとの間にオーバーラップ領域を設けることをさらに含む、請求項1に記載の方法。
- 前記ベース基板上に厚みの異なる部分を有するモールドキャップを設けることをさらに含み、前記モールドキャップは、外周に薄肉部を含む、請求項1に記載の方法。
- 集積回路パッケージオンパッケージ積層システムであって、
ベース基板と、
前記ベース基板上のコンタクトパッドのアレイと、
前記ベース基板上の能動構成要素と、
前記ベース基板の一方端上のモールドキャップと、
前記ベース基板の一方端側に位置する前記モールドキャップの上部面を露出させ、前記ベース基板の他方端上および前記モールドキャップ上の上部パッケージとを含み、
前記モールドキャップは、厚みの異なる部分を含む、システム。 - 前記上部パッケージと前記モールドキャップの薄肉部との間に隙間充填剤をさらに含む、請求項7に記載のシステム。
- 前記上部パッケージと前記ベース基板上のコンタクトパッドの前記アレイとの間にシステム相互接続部をさらに含む、請求項7に記載のシステム。
- 前記モールドキャップと前記上部パッケージとの間にオーバーラップ領域をさらに含む、請求項7に記載のシステム。
- 前記モールドキャップは、厚みの異なる部分を含み、外周に薄肉部を含む、請求項7に記載のシステム。
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
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US59488705P | 2005-05-16 | 2005-05-16 | |
US60/594,887 | 2005-05-16 | ||
US11/383,407 US7746656B2 (en) | 2005-05-16 | 2006-05-15 | Offset integrated circuit package-on-package stacking system |
US11/383,407 | 2006-05-15 |
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JP2006324666A JP2006324666A (ja) | 2006-11-30 |
JP2006324666A5 JP2006324666A5 (ja) | 2011-07-14 |
JP5052037B2 true JP5052037B2 (ja) | 2012-10-17 |
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US (1) | US7746656B2 (ja) |
JP (1) | JP5052037B2 (ja) |
KR (1) | KR101130330B1 (ja) |
TW (1) | TWI381515B (ja) |
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