TWI364091B - Techniques to reduce substrate cross talk on mixed signal and rf circuit design - Google Patents

Techniques to reduce substrate cross talk on mixed signal and rf circuit design Download PDF

Info

Publication number
TWI364091B
TWI364091B TW094109387A TW94109387A TWI364091B TW I364091 B TWI364091 B TW I364091B TW 094109387 A TW094109387 A TW 094109387A TW 94109387 A TW94109387 A TW 94109387A TW I364091 B TWI364091 B TW I364091B
Authority
TW
Taiwan
Prior art keywords
semiconductor
guard ring
ring
integrated circuit
substrate
Prior art date
Application number
TW094109387A
Other languages
English (en)
Chinese (zh)
Other versions
TW200612518A (en
Inventor
Cheisan J Yue
James D Seefeldt
Original Assignee
Honeywell Int Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell Int Inc filed Critical Honeywell Int Inc
Publication of TW200612518A publication Critical patent/TW200612518A/zh
Application granted granted Critical
Publication of TWI364091B publication Critical patent/TWI364091B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76283—Lateral isolation by refilling of trenches with dielectric material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/765—Making of isolation regions between components by field effect
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)
TW094109387A 2004-03-26 2005-03-25 Techniques to reduce substrate cross talk on mixed signal and rf circuit design TWI364091B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/811,207 US7851860B2 (en) 2004-03-26 2004-03-26 Techniques to reduce substrate cross talk on mixed signal and RF circuit design

Publications (2)

Publication Number Publication Date
TW200612518A TW200612518A (en) 2006-04-16
TWI364091B true TWI364091B (en) 2012-05-11

Family

ID=34963645

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094109387A TWI364091B (en) 2004-03-26 2005-03-25 Techniques to reduce substrate cross talk on mixed signal and rf circuit design

Country Status (6)

Country Link
US (2) US7851860B2 (enExample)
EP (1) EP1728275B1 (enExample)
JP (1) JP5209301B2 (enExample)
DE (1) DE602005026918D1 (enExample)
TW (1) TWI364091B (enExample)
WO (1) WO2005098937A1 (enExample)

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003044863A1 (en) * 2001-11-20 2003-05-30 The Regents Of The University Of California Methods of fabricating highly conductive regions in semiconductor substrates for radio frequency applications
US7851860B2 (en) * 2004-03-26 2010-12-14 Honeywell International Inc. Techniques to reduce substrate cross talk on mixed signal and RF circuit design
JP4974474B2 (ja) * 2004-06-22 2012-07-11 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP4689244B2 (ja) 2004-11-16 2011-05-25 ルネサスエレクトロニクス株式会社 半導体装置
US8188565B2 (en) * 2005-12-09 2012-05-29 Via Technologies, Inc. Semiconductor chip and shielding structure thereof
US7608913B2 (en) * 2006-02-23 2009-10-27 Freescale Semiconductor, Inc. Noise isolation between circuit blocks in an integrated circuit chip
JP4949733B2 (ja) * 2006-05-11 2012-06-13 ルネサスエレクトロニクス株式会社 半導体装置
US7691734B2 (en) * 2007-03-01 2010-04-06 International Business Machines Corporation Deep trench based far subcollector reachthrough
US7718514B2 (en) * 2007-06-28 2010-05-18 International Business Machines Corporation Method of forming a guard ring or contact to an SOI substrate
US7999320B2 (en) * 2008-12-23 2011-08-16 International Business Machines Corporation SOI radio frequency switch with enhanced signal fidelity and electrical isolation
US8026131B2 (en) * 2008-12-23 2011-09-27 International Business Machines Corporation SOI radio frequency switch for reducing high frequency harmonics
US7897477B2 (en) * 2009-01-21 2011-03-01 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming an isolation structure
US8133774B2 (en) * 2009-03-26 2012-03-13 International Business Machines Corporation SOI radio frequency switch with enhanced electrical isolation
JP5638205B2 (ja) * 2009-06-16 2014-12-10 ルネサスエレクトロニクス株式会社 半導体装置
WO2011086612A1 (ja) * 2010-01-15 2011-07-21 パナソニック株式会社 半導体装置
US8749018B2 (en) * 2010-06-21 2014-06-10 Infineon Technologies Ag Integrated semiconductor device having an insulating structure and a manufacturing method
CN102478620B (zh) * 2010-11-25 2013-09-11 上海华虹Nec电子有限公司 射频工艺中射频隔离度的表征方法
EP2602817A1 (en) 2011-12-05 2013-06-12 Nxp B.V. Integrated circuit and IC manufacturing method
US8896102B2 (en) * 2013-01-22 2014-11-25 Freescale Semiconductor, Inc. Die edge sealing structures and related fabrication methods
US9899477B2 (en) 2014-07-18 2018-02-20 Infineon Technologies Americas Corp. Edge termination structure having a termination charge region below a recessed field oxide region
US10438902B2 (en) 2017-09-07 2019-10-08 Globalfoundries Inc. Arc-resistant crackstop
JP7087336B2 (ja) * 2017-10-13 2022-06-21 株式会社デンソー 半導体装置
US11296031B2 (en) 2018-03-30 2022-04-05 Intel Corporation Dielectric-filled trench isolation of vias
JP7039411B2 (ja) 2018-07-20 2022-03-22 株式会社東芝 光検出器、光検出システム、ライダー装置及び車
DE102019117707B4 (de) * 2019-07-01 2021-12-30 RF360 Europe GmbH Halbleiter-Die und Antennentuner
JP7222851B2 (ja) 2019-08-29 2023-02-15 株式会社東芝 光検出器、光検出システム、ライダー装置、及び車
JP7153001B2 (ja) 2019-09-18 2022-10-13 株式会社東芝 光検出器、光検出システム、ライダー装置、及び車

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4819052A (en) * 1986-12-22 1989-04-04 Texas Instruments Incorporated Merged bipolar/CMOS technology using electrically active trench
US4980747A (en) * 1986-12-22 1990-12-25 Texas Instruments Inc. Deep trench isolation with surface contact to substrate
JPH02271567A (ja) * 1989-04-12 1990-11-06 Takehide Shirato 半導体装置
US5241211A (en) * 1989-12-20 1993-08-31 Nec Corporation Semiconductor device
US5264387A (en) * 1992-10-27 1993-11-23 International Business Machines Corporation Method of forming uniformly thin, isolated silicon mesas on an insulating substrate
KR950021600A (ko) * 1993-12-09 1995-07-26 가나이 쯔또무 반도체 집적회로장치 및 그 제조방법
JP3159237B2 (ja) * 1996-06-03 2001-04-23 日本電気株式会社 半導体装置およびその製造方法
JP3077592B2 (ja) * 1996-06-27 2000-08-14 日本電気株式会社 デジタル回路とアナログ回路が混在する半導体集積回路装置およびその製造方法
WO1998012750A1 (fr) * 1996-09-20 1998-03-26 Hitachi, Ltd. Composant de circuit integre a semi-conducteur
US6104054A (en) * 1998-05-13 2000-08-15 Texas Instruments Incorporated Space-efficient layout method to reduce the effect of substrate capacitance in dielectrically isolated process technologies
US6521947B1 (en) * 1999-01-28 2003-02-18 International Business Machines Corporation Method of integrating substrate contact on SOI wafers with STI process
US6355537B1 (en) * 1999-02-23 2002-03-12 Silicon Wave, Inc. Method of providing radio frequency isolation of device mesas using guard ring regions within an integrated circuit device
US6573565B2 (en) * 1999-07-28 2003-06-03 International Business Machines Corporation Method and structure for providing improved thermal conduction for silicon semiconductor devices
JP2001044277A (ja) * 1999-08-02 2001-02-16 Nippon Telegr & Teleph Corp <Ntt> 半導体基板および半導体装置
JP2001345428A (ja) * 2000-03-27 2001-12-14 Toshiba Corp 半導体装置とその製造方法
US6429502B1 (en) * 2000-08-22 2002-08-06 Silicon Wave, Inc. Multi-chambered trench isolated guard ring region for providing RF isolation
JP2002110990A (ja) * 2000-09-27 2002-04-12 Toshiba Corp 半導体装置およびその製造方法
US6563181B1 (en) * 2001-11-02 2003-05-13 Motorola, Inc. High frequency signal isolation in a semiconductor device
US6645796B2 (en) * 2001-11-21 2003-11-11 International Business Machines Corporation Method and semiconductor structure for implementing reach through buried interconnect for silicon-on-insulator (SOI) devices
JP2004153175A (ja) * 2002-10-31 2004-05-27 Nec Electronics Corp 半導体集積回路及びその半導体基板
JP2004207271A (ja) * 2002-12-20 2004-07-22 Nec Electronics Corp Ｓｏｉ基板及び半導体集積回路装置
US7851860B2 (en) * 2004-03-26 2010-12-14 Honeywell International Inc. Techniques to reduce substrate cross talk on mixed signal and RF circuit design

Also Published As

Publication number Publication date
US7851860B2 (en) 2010-12-14
US20110045652A1 (en) 2011-02-24
EP1728275B1 (en) 2011-03-16
EP1728275A1 (en) 2006-12-06
JP5209301B2 (ja) 2013-06-12
TW200612518A (en) 2006-04-16
US20050212071A1 (en) 2005-09-29
JP2007531281A (ja) 2007-11-01
DE602005026918D1 (de) 2011-04-28
WO2005098937A1 (en) 2005-10-20
US8058689B2 (en) 2011-11-15

Similar Documents

Publication Publication Date Title
TWI364091B (en) Techniques to reduce substrate cross talk on mixed signal and rf circuit design
KR100358629B1 (ko) 반도체 디바이스 구조물
KR101332116B1 (ko) 쓰루 웨이퍼 비아 및 이것의 제조 방법
US20120146193A1 (en) Thermal Conduction Paths for Semiconductor Structures
CN100466225C (zh) 半导体晶片及其制造方法
US8940596B2 (en) Method of making structure having a gate stack
US20130249011A1 (en) Integrated circuit (ic) having tsvs and stress compensating layer
US20040146701A1 (en) Semiconductor substrate having SOI structure and manufacturing method and semiconductor device thereof
US6638844B1 (en) Method of reducing substrate coupling/noise for radio frequency CMOS (RFCMOS) components in semiconductor technology by backside trench and fill
US20180358258A1 (en) Single mask level forming both top-side-contact and isolation trenches
TWI322504B (en) Semiconductor structure
US9257525B2 (en) Systems and methods for forming isolated devices in a handle wafer
US10903345B2 (en) Power MOSFET with metal filled deep sinker contact for CSP
KR100829404B1 (ko) 모놀리식으로 형성된 저항기-커패시터 부분을 갖는 정전기방전 보호 장치
WO2017125827A1 (en) Quasi-lateral diffusion transistor with diagonal current flow direction
CN111446365B (zh) 一种隔离电容器和用于形成隔离电容的方法
WO2006040738A1 (en) Semiconductor device having a frontside contact and vertical trench isolation and method of fabricating same
US7375397B2 (en) Semiconductor device having an SOI structure and method for manufacturing the same
US12166136B2 (en) Semiconductor device and method of manufacturing the same
US10679944B2 (en) Semiconductor structure with high resistivity wafer and fabricating method of bonding the same
JP2024115232A (ja) 半導体装置およびその製造方法
JP2012151230A (ja) 保護素子及び保護素子を備えた半導体装置

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees