TWI345822B - - Google Patents
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- TWI345822B TWI345822B TW096130961A TW96130961A TWI345822B TW I345822 B TWI345822 B TW I345822B TW 096130961 A TW096130961 A TW 096130961A TW 96130961 A TW96130961 A TW 96130961A TW I345822 B TWI345822 B TW I345822B
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- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73257—Bump and wire connectors
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- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
- H01L2224/85005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate being a temporary or sacrificial substrate
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- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18165—Exposing the passive side of the semiconductor or solid-state body of a wire bonded chip
Description
1345822 玖、發明說明: 【發明所屬之技術領域】 特別是有關於一種於 本發明係有關於一種封裝結構及其製造方法, —表面之置晶腔,從而使得晶 承載器上形成有一貫穿其第一表面及第 片之主動_下並與承載器之第—表_平齊之新式封裝結構及其製 造方法。 【先前技術】 隨著電子產品朝著多功能、高性能和小型化、輕型化的方向發展, 針對電子產品中之封裝件已具有多種封裝方式,例如,打線封裝(士e bonding)、覆晶封裝(flip chip)及晶片尺寸(物封襄等。 為了降低封裝結構之“與承載器_電子峨傳輸距離並縮小 封裝後的晶片封裝構造尺寸,可以將晶片哺晶之方式結合於承載器 上’如第1圖所示之習知封裝結構的剖面圖。習知之封裝結構⑽包 含-承載器110、-晶片12〇、多個凸塊⑽及_封膠^該承載器 no具有相對之-第-表面U1及一第二表面112,於其第一表面⑴ 上形成有多個鲜塾113。該晶片12〇具有相對之一主動面121及—背面 122 ’於其主動面121上係形成有多個銲塾123。凸塊13〇係用以電性 連接該承載器11〇之該些連接墊113與該晶片12〇之該些銲墊123。該 封膠14G係形成於該承載n 11Q與該晶片12()之間以保護該些凸塊 130。此封裝結構1〇〇更包含有錫球15〇,其係形成於承載器ιι〇之第 二表面112上,用以與一印刷電路板(未繪示)電性連接。 5 1345822 在上述習知封裝結構尚未填充娜14〇前,首先須於晶片i2〇 與承載器110之間形成凸塊130,然後對凸塊13〇進行 封朦140後,還需要於承載器11G之第二表面112上形成銲球⑽,然 後再對銲球15G進行迴銲。故,該f知封裝結構之製程相當複雜。 況且,該習知封裝結構⑽之晶片12〇係疊置於承載器ιι〇上並藉由 凸塊130連接於兩者之間,從而導致該習知封裝結構⑽之厚度較大,
佔據電子産品中的較大空間。 美國專利第6, 906, 4i4號、第5, 541,號及第5, 717,脱號均揭 示-種藉由—加強板或支撐板㈣晶片設置於基板上的封裝結構,儘 管該些封裝結構之高度她於[圖中所示之習知封裝結構之高度有 -些降低,惟其封裝結構複雜,且其封裝尺寸仍不符合目前電子產品 的發展趨勢,故有進一步改進之必要。 馨於以上習知技術之缺陷,美國專利第⑽6,·號揭示一種低構
=封裝結構’於該習知職結射,晶片背面向下並暴露於外界, °下並不適。目别的封裝需求,而且在該案巾並未詳細揭露此 種封裝結構之封裝方法,從科足轉廣使用。 【發明内容】 本發私轉目陳於提供__轉觀錄紗法,其可以簡 化封裝結構⑽程,域少封裝結構之厚度。 承胃’她提供—麵細,其包含有:一 ^ 一晶片、至少一銲線、一封膠、至少一第一銲球及至少一第 6 1345822
二銲球,其中該承載器具有一置晶腔、一第一表面及一第二表面,該 第一表面係相對於該第二表面,該置晶腔係貫穿該第一表面及該第二 表面,於該第一表面上具有至少一第一連接墊,而於該第二表面上具 有至少一第二連接墊;該晶片係設置於該承載器之置晶腔内,該晶片 具有相對之一主動面及一背面,且其主動面與該承載器之第一表面相 平齊,於該主動面上具有至少一第一銲墊,而於該背面上具有至少一 第二銲塾;該銲線係設置於該晶片及該承載器之間,用以電性連接該 晶片之第二銲墊與該承載器之第二連接墊;該封膠係設置於該承載器 之第二表面上,且填充該置晶腔,該封膠覆蓋部分之該晶片、該晶片 之第二銲墊、該銲線、該承載器之第二表面及該承載器之第二連接墊, 且暴露該晶片之主動面、該承載器之第一表面、該晶片之第一銲墊及 該承載器之第一連接墊;該第一銲球係設置於該晶片之主動面之第一 銲墊上;以及該第二銲球係設置於該承載器之第一表面之第一連接墊 上。
依據本發明之上述目的,本發明還提供一種封裝結構之製造方法, 其包含有如下步驟: 提供一承載器,該承載器具有一置晶腔、一第一表面及一第二表 面,該第一表面係相對於該第二表面,該置晶腔係貫穿該第一表面及 該第二表面,於該第一表面上具有至少一第一連接墊,而於該第二表 面上具有至少一第二連接墊; •^供一載帶,其位於該承載器之第一表面上,以封住該置晶腔之一 7 1345822 端開口; • 設置一晶片於該承載器之置晶腔内,該晶片具有相對之一主動面及 41面,且其主動面緊貼於該載帶上,於該主動面上具有至少一第— 銲墊,而於該背面上具有至少一第二銲墊; 形成至少一銲線於該晶片及該承載器之間,以電性連接該晶片之第 二銲墊與該承載器之第二連接墊; 馨 形成—封膠於該承載器之第二表面上,以填充該置晶腔,該封膠覆 蓋部分之該晶片、該晶片之第二銲塾、鱗線、該承載器之第二表面 及該承載器之第二連接塾; 移除該載帶,以暴露出該晶片之主動面、該承載器之第一表面、該 晶片之第一銲墊及該承載器之第一連接墊; 形成至少一第一銲球於該晶片之主動面之第一銲墊上;以及 形成至少一第二銲球於該承載器之第一表面之第一連接墊上。 • 與先前技術相比較,本發明封裝結構係於承載器上形成一貫穿其第 表面及第一表面之置晶腔,晶片則以主動面朝下並與承載器之第— 表面相平齊的方式設置,從而可以減少封裝結構之厚度、有效縮短電 性傳輪路徑、有利於提高散熱效果。在製造時,由於承載器之第一表 面及晶片之主動面均緊貼於載帶上,從而簡化封裝結構的製程。 【實施方式】 本實施例將會結合第二八至二〇圖所示之結構示意圖及第三圖所示 之流程圖對本發明封裝結構之製造方法作詳細介紹。 8 言月參照第二A圖及第1之步驟a所示,首先需要提供一承載器 1〇,該承議〇具有-第—表面211、—第:細2及一置晶腔 該第一表面211係相對於該第二表面批,該置晶腔213係貫穿 於第一表面211及第二表曝树容叫如^圖中所示)。 於該承綱0之第—表面211上具有多個第_連接她,而於其第 表面212上則具有多個第二連接塾215。本發明之該等第—連接塾 與第連接墊215-般係由金屬或金屬之組合做成的,如銅、錄、 錫、金等。在該實施例中,於該承載器210上具有至少—貫穿其第一 表面211及第二表面212的導電貫孔(未圖示),用以電性連接I中一 第-連·214及其中-第二連接墊215。 、 請參照第二Β圖及第三圖之步驟b所示提供一載帶咖,將 器210設置於該載帶220上,且該承載謂之第-表面211係與該 載帶220相接觸’且載帶220能夠封住該置晶腔213之位於第— 表面211上的—端開口。在該實施例中,該載帶220係一膠帶, 該承載器210係藉由其第一表面211黏著於該膠帶上。當然,該載帶 220可不限定爲膠帶,而可以在載帶22〇上設置一卡合結構(未圖示), 藉由該卡合結構將承載器21〇固定於載帶22〇上。 請參照第二C圖及第三圖之步驟c所示,設置-晶片230於該承載 器210之置晶腔213 β,該晶片23〇具有相對之一主動面及—背 面232 ’且其主動面231向下並緊貼於該載帶220上,於晶片23〇之主 動面231上具有多個第-銲塾233,而於晶片230之背面232上具有多 1345822 個第二銲塾234。在該實施例中,於該些第—鲜塾233與該些第二 鮮墊234之中均至少具有一輸入愚出鮮塾(未標示)。換言之,於該 晶片230之主動面231及背面232均至少具有一輸入/輸出銲墊。該晶 片230還具有至貫穿其主動面23!及背面232的導電貫孔(未圖 示)’用以電性連接其中一第一銲塾233及其中_第二鲜塾
請參照第二D圖及第三圖之步驟d所示,進行打線結合,形成複數 條銲請於該晶片咖及該承載器之間。採用打線結合係爲使 晶片230中之訊號連接至承載器別,而承載器21◦具有内部路由 (时—⑹’其藉由第—、第二連接塾214、加使得晶片刎 訊號連接至位於承載器21〇底面(即第一表面2ιι)上的鲜球(如第二 G圖中所示之第二銲球叫該些銲線⑽通常爲金線或轉,用以 電性連接位於該晶片咖上之第二銲墊既及位於該承載器⑽上並 刀別與該等第二銲墊234相對應之第二連接塾加。
β月參照第一 Ε圖及第二圖夕半锁 —圖之步驟e所不’域-封膠250於該承裁 口第二表面212上,以填充該置晶腔加,該封膝250覆蓋部分 ^晶片⑽如則〇之背面咖及其兩側面)、晶㈣之該些第 ^=34、該些銲線_、承載器21G之第二表面212及承載器210 〜第-連接塾215,藉此保護該些結構。 出曰:tr—F圖及第三圖之步驟f所示,移除該載帶220,以暴露 出日日片230之主動面23卜承載器21〇之第一 些第一銲墊2泊及承恭嬰 、曰日片230之該 3蝴請之㈣—趣當移除該載帶 10 1345822 220後,晶片230之主動面231係朝下暴露於外並與承載器21〇之第 表面211相平齊’藉此不但可降低整體封裝結構之高度,而且還可増 強散熱效果及提高電性傳輸效果。 請參照第二G圖及第三圖之步驟g與步驟h所示,設置多個第—銲 球260於該晶片230之主動面231之該些第一銲墊233上,並設置多 個第二銲球270於該承載器210之第一表面211之該些第一連接墊214 上,以形成一封裝結構200。 綜上所述,本發明確已符合發明專利之要件,爱依法提出專利申 請。惟’以上所述者僅爲本發明之較佳實施方式,舉凡熟習本案技術 之人士援依本發敗精神所狀粒料或變化,冑涵蓋於後附之申 請專利範圍内。 【圖式簡單說明】 第一圖係習知封裝結構之示意圖。 第二A圖係顯示本發明承載器之示意圖。 第二3圖侧示本發明設置承鑛於—鱗上之示意圖。 第二C圖係'顯示本發明設置—晶片於承載器及載帶上之示意圖。 第二D圖係顯示本發明形成複數條銲線的示意圖。 第二E圖係顯示本發明形成—封膠於承健之第二表面上的示意圖。 第-F圖侧示本發卿除餅後之示意圖。 第-G圖係顯示本發明封裝結構之示意圖。 第三圖係_本發明封裝結構之職方法之流程圖。 11 1345822
【主要元件符號說明】 封裝結構 100 、 200 承載器 110 、 210 第一表面 111 ' 211 第二表面 112 、 212 銲墊 113 、 123 凸塊 130 錫球 150 置晶腔 213 第一連接墊 214 第二連接墊 215 載帶 220 晶片 120 、 230 主動面 121 ' 231 背面 122 、 232 第一銲墊 233 第二銲墊 234 銲線 240 封膠 140 、 250 第一銲球 260 第二銲球 270
12
Claims (1)
1345822 100年丨月4曰修正本
100年1月26日替換頁 拾、申請專利範圍: 1.一種封裝結構之製造方法,其包含有: 提供-承載器,該承載器具有—置晶腔、—第—表面及一第二 表面,該第-表面係減於該第二表面,該置晶腔係貫穿該第一表 面及該第二表面,於該第-表面上具有至少—第—接墊,而於該 第二表面上具有至少一第二連接墊; 提供-載帶’其位於該承之第_表面上,以封住該置晶 腔之一端開口; 設置-晶片於該承脑之置晶_,該晶片具有相對之一主動 面及心’且其主動面$、貼於該載帶上,於該主動面上具有至少 一第一銲墊,而於該背面上具有至少一第二銲墊; 形成至少一銲線於該晶片及該承載器之間,以電性連接該晶片 之第二銲墊與該承載器之第二連接墊; 广-封膠於該承載器之第二表面上,以填充該置晶腔,該封 勝覆蓋部分之該“、該晶片之第二銲塾、鱗線該轉器之第 二表面及該承載器之第二連接墊; 移除該載帶’以暴露出該晶片之主動面、該承載器之第一表 面、該晶片之第一銲墊及該承載器之第一連接墊; 形成至少—第一銲球於該晶片之主動面之第一銲墊上;以及 形成至少-第二録球於該承載器之第—表面之第一連接塾上。 2 .如申請專__ 1顿狀結叙製造方法,其中 13 100年1月26日替換頁 該載帶設財—卡合、祕,祕載11储由該—-該載帶上。 ' 3. 如申請專利範園第1項所述之封裝結構之製造方法,其中 該載帶係一膠帶,該承截器係黏著於該膠帶上。 4. 如申請專利範園第1項所述之封裝結構之製造方法,其中 該承載器具有至少—導電貫孔,該導電訊貫穿H表面及第二 表面,用以電性連接其第一連接墊及第二連接墊。 5 ·如申請專利範圍第1項所述之封褒結構之製造方法,其中 該晶片具有至少一導電貫孔,該導電貫孔貫穿其主動面及背面,用 以電性連接其第一銲塾及第二銲墊。 6.如申請專利範圍第i項所述之封裝結構之製造方法其中 於該晶片之絲®及背面均具有—輸人/輸出辉塾。 14
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