TWI360217B - Stacked packaging module and method for manufactur - Google Patents

Stacked packaging module and method for manufactur Download PDF

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Publication number
TWI360217B
TWI360217B TW96141601A TW96141601A TWI360217B TW I360217 B TWI360217 B TW I360217B TW 96141601 A TW96141601 A TW 96141601A TW 96141601 A TW96141601 A TW 96141601A TW I360217 B TWI360217 B TW I360217B
Authority
TW
Taiwan
Prior art keywords
package
package substrate
electrically connected
chip
connection pads
Prior art date
Application number
TW96141601A
Other languages
Chinese (zh)
Other versions
TW200921886A (en
Inventor
Shih Ping Hsu
Chia Wei Chang
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to TW96141601A priority Critical patent/TWI360217B/en
Publication of TW200921886A publication Critical patent/TW200921886A/en
Application granted granted Critical
Publication of TWI360217B publication Critical patent/TWI360217B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Combinations Of Printed Boards (AREA)
  • Wire Bonding (AREA)

Description

1360217 • 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種堆疊式封裝模組及其製法，尤指— • 種能避免板彎翹，省略植球製程，利於縮小連接墊之尺寸 5 及間距’亦能降低封裝體高度之堆疊式封裝模組及其製法。 【先前技術】 • 隨著電子產業的蓬勃發展，電子產品亦逐漸進入多功 能、高性能的研發方向。為滿足半導體封裝件高積集度 10 (Integration)以及微型化（Miniaturization)的封裝要求，提供 多數主被動元件及線路連接之封裝基板，亦逐漸由單層板 演變成多層板，以使在有限的空間下，藉由層間連接技術 (Interlayer connection)擴大封裝基板上可利用的佈線面積 而配合高電子密度之積體電路（Integrated circuit)需求。此 15外’為符合產品小型化與多功能之要求，高腳數且效能佳 φ 之封裝結構成為現今封裝主流，同時亦促使廠商投入系統 整合型封裝（SIP)之發展，以將不同的晶片或其他電子元 件，整合於同一封裝模組内，俾能執行相當於系統層級之 功能。系統整合型封裝（SIP)具有微型化、高效能、及低成 20本之優勢；同時，更能減少或消除客戶對高速電路設計的 需求，並有效減少電磁干擾（EMI)的噪音。 為達成系統整合型封裝，請參見圖丨，習知之堆疊式封 裝模組主要係利用封裝疊加（Package 0n Package，p〇P)技 術，將兩個封裝結構整合於單一封裝模組中。此堆疊式封 5 1360217 裝2組包括一第—封裝結構1及一第二封裝結構第一封 裝結構1與第二封裝結構1，係形成打線接合型態之封袭結 構第一封裝結構1主要係由一封裝基板10、一晶片u、複 數金屬線14以及-封谬材料15所構成。在此該封裝基板 10之第一表面10a具有複數打線焊墊101及複數第一連接墊 1 曰02而相對之第二表面⑽具有複數第二連接塾M3。而該 晶片11則配置於該封裝基板狀第—表面⑽上且該晶片 U之作用面Ua具有複數電極墊⑴’其藉由該些金屬線14 而與該封裝基板1()之打線焊塾1G1電性連接。此外，該封膠 材料15係包覆該晶月11以及該些金屬線14。又，此第一封 裝結構1之第一連接墊102上接置有複數焊料球104,以疊加 第—封裝結構Γ於第—封裝結構1之上方。在此，第二封裝 結構Γ之封裝型態與第-封裝結構1相同。 、 15 一然而，上述堆疊式封裝模組卻有諸多缺點急需改善：其 此堆疊式封裝模組易因不對稱結構而有板㈣的問題 發生；其二’藉由焊料球電性連接兩封裝結構時，若助焊 ，未完整塗佈於焊接處，則會有虛焊的情況發生；其三， 豐加第二封裝結構於第一封裝結構上方時，封膠材料及所 有-定高度’限制了第二封裝結構與第一封裝結 ^的最小間距’不易降低該封裝模组高度，亦限制焊料 ，及對應連接墊之最小尺寸，不僅不利於減少焊料以節省 :本’亦不利於縮小連接墊之間距，而無法滿足產 化之需求。 20 1360217 據此，提供-種可解決上述缺點之堆疊式封裝模組係 本發明之重要目標。 【發明内容】 10 本發明之主要目的係在提供一種堆疊式封裝模組，其 可避免板魏的問題發生，此外，本發明可省略植球製程， 以避免以焊料球電性連接兩封裝結構時，因助焊劑未完整 塗佈於焊接處而導致虛焊之問題發生，再者，本發明亦有 利於縮小連接塾之間距，且能節省成本。最後，本發明能 降低封裝模組之整體高度，以達職品微小化之要求。 15 為達成上述目的，本發明提供一種堆疊式封裝模組， 其包括.一第一封裝結構，係包含有一第一晶月及一第一 封裝基板’其中第-晶片係與第一封裝基板電性連接，而 第一封裝基板具有一第一表面及相對之-第二表面，且第 一表面具有複數第-連接塾，第二表面具有複數第二連接 墊，一第二封裝結構，係包含有一第二晶片及一第二封裝 基板，其中第二晶片係與第二封裝基板電性連接，而第二 封裝基板具有-第-表面及相對之一第二表面，且第二表 20 =複數第二連接墊；一表面陶完化之鋁金屬板，係配 置於第-封裝結構與第二封裝結構之間，其中，第一 係設置於第-封裝基板之第_表面上，而該表面陶^之 鋁金屬板具有一第一開口，俾以容置第一晶片，且該表面 陶究化之紹金屬板復具有複數通孔，該些通孔之相對兩端 係刀別對應第-封裝結構之該些第一連接塾及第二封裝結 7 1360217 構之該些第二連接塾；以及-金屬膏，係填充於該表面陶 瓷化之鋁金屬板之該些通孔中，以電性連接第—封穿纟士構 之該些第一連接墊與第二封裝結構之該些第二連接墊。 於本發明之堆疊式封裝模組中’第一封裝結構與第二 5 封裝結構可為任意型式之封裝結構，例如，覆晶封裝結構、 打線封裝結構等等之型式，其中，若第一封裝結構係第一 晶片設置於第一封裝基板之第一表面上之封裝結構（如覆 晶封裝結構或打線封裝結構）’則該表面陶瓷化之鋁金屬板 可復具有一第一開口，俾以容置第一晶片。同樣地，若第 10 —封裝結構係第二晶片設置於第二封裝基板之第二表面上 之封裝結構（如，覆晶封裝結構或打線封裝結構），則該表面 陶瓷化之鋁金屬板復可具有一第二開口，俾以容置第二晶 片。此外，第一封裝結構之封裝型式可與第二封装結構相 同或不同。 15 於本發明之堆疊式封裝模組中，若第一封裝基板之第 一表面上復具有至少一第一被動元件，則該表面陶瓷化之 铭金屬板復可具有至少一第三開口，俾以容置該至少一第 一被動元件《同樣地，若第二封裝基板之第二表面上復具 有至少一第一被動元件’則該表面陶究化之銘金屬板復可 20 具有至少一第四開口，俾以容置該至少一第二被動元件。 於本發明之堆疊式封裝模組中，該金屬膏之材料不 限，較佳為’銅膏或銀膏》 本發明復提供一種堆疊式封裝模組之製法，包括：提 供一表面陶瓷化之鋁金屬板，係具有一第一開口及複數通 8 1360217 10 15 20 孔；填充一金屬膏於該些通孔内；以及接置一.第一封裝結 構及一第一封裝結構於該表面陶瓷化之鋁金屬板之兩相對 表面，並使該金屬膏電性連接第一封裝結構與第二封裝結 構，其中’第一封裝結構係包含有一第一晶片及一第一封 裝基板，第一晶片係與第一封裝基板電性連接且容置於該 表面陶瓷化之鋁金屬板之第一開口，而第一封裝基板具有 一第一表面及相對之一第二表面，且第一表面具有複數第 一連接墊，第二表面具有複數第二連接墊；第二封笨結構 係包含有一第二晶片及一第二封裝基板，第二晶片係與第 二封裝基板電性連接，而第二封裝基板具有一第一表面及 相對之一第二表面，第二表面具有複數第二連接墊；且該 表面陶瓷化之鋁金屬板之該些通孔之相對兩端係分別對應 第一封裝結構之該些第一連接墊及第二封裝結構之該些第 一連接墊，俾使第二封裝結構之該些第二連接墊係藉由該 金屬膏與第一封裝結構之該些第一連接墊電性連接。 盘於本發明之堆疊式封裝模組之製法中，帛一封裝結構 與第-封裝結構之接置順序並無限制，其中，可先接置第 :封裝結構於表面陶竟化之铭金屬板之一表面，再接置第 =封裝結構於表面陶竞化之銘金屬板之另一相對表面；或 面先接置第一封裝結構於表面陶瓷化之鋁金屬板之一表 再接置第封裝結構於表面陶瓷化之铭金屬板之另一 相對表面。 9 1360217 於本發明之堆疊式封裝模組之製法中，該金屬膏可藉 由任何方法填充於該些通孔内，較佳為，藉由印刷或點膠 法，將金屬膏填充於該些通孔内。 據此，本發明因具有剛性強之表面陶瓷化之鋁金屬 5 板’故可避免板彎翹的問題發生，此外，此表面陶瓷化之 鋁金屬板具有填入金屬膏之複數通孔以電性連接兩封裝結 構，不僅可省略植球製程’以避免以焊料球電性連接兩封 裝結構時，因助焊劑未完整塗佈於焊接處而導致虛焊之問 題發生’亦避免直接使用焊料球電性連接兩封裝結構，對 10 於焊料球及對應連接墊之最小尺寸限制，有利於縮小連接 墊之尺寸及間距，且能減少金屬膏用量以節省成本。此外， 本發明之表面陶瓷化之鋁金屬板更具有容置晶片或被動元 件之開口，俾能降低封裝模組之整體高度，以達到產品微 小化之要求。 15 【實施方式】 以下係藉由特定的具體實施例說明本發明之實施方 式，熟習此技藝之人士可由本說明書所揭示之内容輕易地 了解本發明之其他優點與功效。本發明亦可藉由其他不同 2〇的具體實施例加以施行或應肖，本說明書中的各項細節亦 可基於不同觀點與應用’在不,障離本發明之精神下進行各 種修姊與變更。 實施例1 10 1360217 凊參考圖2A至2C，係為本發明一較佳實施例之堆疊式 封裝模組製法剖示圖。 .首先，如圖2A所示，提供一表面陶瓷化之鋁金屬板3， 其具有複數通孔31及一第一開口32 ;接著，填充一金屬膏4 5於該些通孔31内，該金屬膏4可藉由印刷或點膠法填充於該 些通孔31内，此外，該金屬膏4之材料不限，於本實施例中， 該金屬膏4係以銅膏藉由點膠法填充於該些通孔31内。 接著，如圖2B所示，接置一第一封裝結構2於表面陶瓷 化之鋁金屬板3之一表面，其中，第一封裝結構2包含有一 10第一晶片21及一第一封裝基板20，第一晶片21係與第一封 裝基板20電性連接，而第一封裝基板2〇具有一第一表面 及相對之一第二表面20b’且第一表面2〇a具有複數第一連 接墊202，第二表面20b具有複數第二連接墊2〇3。更詳述 之，第一封裝結構2主要係由一第一封裝基板2〇、一第一晶 15片21、複數金屬線24以及一封膠材料25所構成。第一晶片 21係配置於第一封裝基板2〇之第一表面2〇a上，且第一晶片 21之作用面21a具有複數電極墊叫，關由該些金屬線24 而與第一封裝基板20之打線焊墊2〇1電性連接。此外，該封 膠材料25係包覆第一晶片21以及該些金屬線24。如圖2Bm 20示，該些通孔31係對應第一封裝結構2之該些第一連接墊 202，且金屬膏4與第一封裝結構2之第一連接墊2〇2電性連 接，而第一開口 32係用以容置第一晶片21。 最後，如圖2C所示，接置一第二封裝結構2，於該表面 陶究化之鋁金屬板3之另一相對表面，其中第二封裝結構2, 11 1360217 5 2丨η 一封裝結構2相同，其係包含有-第二晶片 2= -第二封裝基板2G，，第二晶片21，係與第二封裝基板 2〇電性連接’而第二封裝基板2〇,具有一第一表面2〇a，及相 對之-第二表面2Gb，，第二表面脚具有複數第二連接塾 203，，且第二封裝結構2，之該些第二連接塾2()3，係與該金屬 膏4電性連接’俾使第二封裝結構2，之該些第二連接塾2〇3, 藉由該金屬膏4與第一封裝結構2之該些第一連接墊2〇2電 性連接。1360217 • Nine, invention description: [Technical field of invention] The present invention relates to a stacked package module and a method for manufacturing the same, in particular, a type can avoid bending of a board, omitting a ball-planting process, and facilitating the reduction of the size of the connection pad 5 and pitch' can also reduce the height of the package and the method of manufacturing the stacked package. [Prior Art] • With the booming electronics industry, electronic products are gradually entering the direction of multi-functional and high-performance research and development. In order to meet the packaging requirements of semiconductor package high integration 10 and miniaturization, most active and passive components and circuit-connected package substrates are provided, and gradually evolved from single-layer boards to multi-layer boards to make them limited. In the space, the interlayer area available on the package substrate is expanded by the interlayer connection technology to meet the demand for a high electron density integrated circuit. In order to meet the requirements of product miniaturization and multi-function, the high-capacity and high-efficiency package structure has become the mainstream of today's packaging, and it has also prompted manufacturers to invest in the development of system-integrated package (SIP) to different chips. Or other electronic components, integrated into the same package module, can perform functions equivalent to the system level. System-integrated package (SIP) has the advantages of miniaturization, high efficiency, and low cost. At the same time, it can reduce or eliminate the customer's demand for high-speed circuit design and effectively reduce electromagnetic interference (EMI) noise. In order to achieve a system-integrated package, please refer to the figure. The conventional stacked package module mainly uses Package 0n Package (p〇P) technology to integrate two package structures into a single package module. The stacked package 5 1360217 is provided with a first package structure 1 and a second package structure. The first package structure 1 and the second package structure 1 form a wire bonding type of the sealed structure. It consists of a package substrate 10, a wafer u, a plurality of metal wires 14 and a sealing material 15. The first surface 10a of the package substrate 10 has a plurality of wire bonding pads 101 and a plurality of first connection pads 1 曰 02 and a second surface (10) opposite to the second surface 塾 M3. The wafer 11 is disposed on the package substrate-like surface (10), and the active surface Ua of the wafer U has a plurality of electrode pads (1)' which are soldered to the package substrate 1 by the metal wires 14. 1G1 is electrically connected. Further, the encapsulant 15 coats the crystal 11 and the metal wires 14. Moreover, a plurality of solder balls 104 are attached to the first connection pads 102 of the first package structure 1 to superimpose the first package structure over the first package structure 1. Here, the package pattern of the second package structure is the same as that of the first package structure 1. However, the above-mentioned stacked package module has many shortcomings that need to be improved: the stacked package module is susceptible to the problem of the board (4) due to the asymmetrical structure; and the second is electrically connected to the two packages by solder balls. In the case of soldering, if the soldering is not completely applied to the soldering, there will be a case of solder joint; thirdly, when the second package structure of Fengjia is above the first package structure, the sealing material and all-fixed heights Limiting the minimum spacing between the second package structure and the first package structure is not easy to reduce the height of the package module, and also limits the solder and the minimum size of the corresponding connection pads, which is not only conducive to reducing solder to save: this is also not conducive to shrinking The distance between the pads is not enough to meet the needs of production. 20 1360217 Accordingly, it is an important object of the present invention to provide a stacked package module that solves the above disadvantages. SUMMARY OF THE INVENTION The main object of the present invention is to provide a stacked package module, which can avoid the problem of the board. In addition, the present invention can omit the ball placement process to avoid electrically connecting the two package structures with solder balls. At the same time, the problem of the solder joint is caused by the flux being not completely applied to the soldering portion. Furthermore, the present invention is also advantageous for reducing the distance between the ports and saving costs. Finally, the present invention can reduce the overall height of the package module to meet the requirements of miniaturization of the product. In order to achieve the above object, the present invention provides a stacked package module, comprising: a first package structure, comprising a first crystal and a first package substrate, wherein the first wafer and the first package are electrically The first package substrate has a first surface and an opposite second surface, and the first surface has a plurality of first connection ports, the second surface has a plurality of second connection pads, and a second package structure includes a second chip and a second package substrate, wherein the second chip is electrically connected to the second package substrate, and the second package substrate has a -first surface and a second surface, and the second table 20 = plural a second connection pad; a surface-finished aluminum metal plate disposed between the first package structure and the second package structure, wherein the first system is disposed on the first surface of the first package substrate, and the surface The aluminum metal plate of the ceramic has a first opening for accommodating the first wafer, and the surface of the metal plate has a plurality of through holes, and the opposite ends of the through holes are corresponding to the first The first connection of the package structure And the second bonding layer formed by the second package junction 7 1360217; and the metal paste is filled in the through holes of the surface ceramized aluminum metal plate to electrically connect the first sealing layer The first connection pads of the first connection pad and the second connection pads of the second package structure. In the stacked package module of the present invention, the first package structure and the second 5 package structure may be any type of package structure, for example, a flip chip package structure, a wire bond package structure, etc., wherein, if the first package The first wafer of the structure is disposed on the first surface of the first package substrate (such as a flip chip package structure or a wire package structure). The surface ceramized aluminum metal plate may have a first opening. The first wafer is housed. Similarly, if the 10th package structure is a package structure (eg, a flip chip package structure or a wire bond package structure) on which the second wafer is disposed on the second surface of the second package substrate, the surface ceramized aluminum metal plate is There may be a second opening to accommodate the second wafer. In addition, the package pattern of the first package structure may be the same as or different from the second package structure. In the stacked package module of the present invention, if the first surface of the first package substrate has at least one first passive component, the surface ceramized metal plate may have at least one third opening, Having the at least one first passive component "samely, if the second surface of the second package substrate has at least one first passive component", the surface of the metal plate 20 can have at least one The four openings are configured to receive the at least one second passive component. In the stacked package module of the present invention, the material of the metal paste is not limited, preferably 'copper paste or silver paste'. The invention provides a method for manufacturing a stacked package module, comprising: providing a surface ceramization The aluminum metal plate has a first opening and a plurality of holes 13 1360217 10 15 20 holes; filling a metal paste in the through holes; and connecting a first package structure and a first package structure on the surface ceramic The two opposite surfaces of the aluminum metal plate are electrically connected to the first package structure and the second package structure, wherein the first package structure comprises a first chip and a first package substrate, the first chip The first package substrate is electrically connected to the first package substrate and is received in the first opening of the surface ceramized aluminum metal plate, and the first package substrate has a first surface and a second surface, and the first surface has a plurality of a first connection pad, the second surface has a plurality of second connection pads; the second package structure comprises a second chip and a second package substrate, the second chip is electrically connected to the second package substrate, and the second package is The plate has a first surface and a second surface opposite to each other, and the second surface has a plurality of second connecting pads; and opposite ends of the through holes of the surface ceramized aluminum metal plate respectively correspond to the first package structure The first connection pads of the first connection pads and the second package structure, such that the second connection pads of the second package structure are formed by the metal paste and the first connection pads of the first package structure Electrical connection. In the method of manufacturing the stacked package module of the present invention, the order of connection between the first package structure and the first package structure is not limited, wherein the first: the package structure is mounted on the surface of the ceramic tile One surface, and then the other opposite surface of the metal plate on the surface of the ceramic tile; or the surface of the first package structure on the surface of the tempered aluminum metal plate The package structure is on the opposite surface of the surface ceramized metal plate. 9 1360217 In the method of the stacked package module of the present invention, the metal paste may be filled in the through holes by any method, preferably, the metal paste is filled in the printing or dispensing method. Inside the through hole. Accordingly, the present invention can avoid the problem of bending of the plate due to the rigid aluminum cermetized aluminum metal 5 plate. In addition, the surface ceramized aluminum metal plate has a plurality of through holes filled with the metal paste for electricity. Sexual connection of two package structures, not only can the ball placement process be omitted to avoid the problem of solder joints caused by the flux being not completely applied to the solder joint when the solder balls are electrically connected to the two package structures. The electrical connection of the two package structures, the minimum size limitation of the solder balls and the corresponding connection pads, helps to reduce the size and spacing of the connection pads, and can reduce the amount of metal paste to save costs. In addition, the surface ceramized aluminum metal plate of the present invention has an opening for accommodating the wafer or the passive component, and the overall height of the package module can be reduced to meet the requirements of product miniaturization. [Embodiment] The embodiments of the present invention are described by way of specific embodiments, and those skilled in the art can readily understand the other advantages and advantages of the present invention as disclosed in the present disclosure. The present invention may also be implemented or embodied by other specific embodiments, and the details in the specification may also be based on different viewpoints and applications, and the various modifications may be made without departing from the spirit of the invention. change. Embodiment 1 10 1360217 Referring to Figures 2A to 2C, a schematic cross-sectional view of a stacked package module in accordance with a preferred embodiment of the present invention is shown. First, as shown in FIG. 2A, a surface ceramized aluminum metal plate 3 is provided, which has a plurality of through holes 31 and a first opening 32. Then, a metal paste 45 is filled in the through holes 31. The metal paste 4 can be filled in the through holes 31 by printing or dispensing. In addition, the material of the metal paste 4 is not limited. In the embodiment, the metal paste 4 is made of copper paste by dispensing. Filled in the through holes 31. Then, as shown in FIG. 2B, a first package structure 2 is disposed on a surface of the surface ceramized aluminum metal plate 3, wherein the first package structure 2 includes a first wafer 21 and a first package substrate 20. The first chip 21 is electrically connected to the first package substrate 20, and the first package substrate 2 has a first surface and a second surface 20b' and the first surface 2a has a plurality of first connection pads. 202, the second surface 20b has a plurality of second connection pads 2〇3. More specifically, the first package structure 2 is mainly composed of a first package substrate 2, a first crystal chip 21, a plurality of metal wires 24, and an adhesive material 25. The first wafer 21 is disposed on the first surface 2〇a of the first package substrate 2, and the active surface 21a of the first wafer 21 has a plurality of electrode pads called the metal wires 24 and the first package substrate. 20 wire bonding pads 2〇1 electrical connection. Further, the sealant 25 covers the first wafer 21 and the metal wires 24. As shown in FIG. 2Bm, the through holes 31 correspond to the first connection pads 202 of the first package structure 2, and the metal paste 4 is electrically connected to the first connection pads 2〇2 of the first package structure 2, and The first opening 32 is for accommodating the first wafer 21. Finally, as shown in FIG. 2C, a second package structure 2 is disposed on the opposite surface of the surface of the aluminum metal plate 3, wherein the second package structure 2, 11 1360217 5 2 丨 a package structure 2 is the same, comprising - the second wafer 2 = - the second package substrate 2G, the second wafer 21 is electrically connected to the second package substrate 2 and the second package substrate 2 has a first a surface 2〇a, and an opposite second surface 2Gb, the second surface leg has a plurality of second ports 203, and the second package structure 2, the second ports 2()3, The metal paste 4 is electrically connected to the second package structure 2, and the second connections 塾2〇3 are electrically connected by the metal paste 4 and the first connection pads 2〇2 of the first package structure 2. connection.

10 1510 15

20 據此，本實施例提供一種堆疊式封裝模組，請參考圖 2C’其包括：一第一封裝結構2，係包含有一第一晶片。及 一第一封裝基板20，其中第一晶片21係與第—封裝基板加 電性連接，*第-封裝基板2G具有―第―表㈣认相對之 一第二表面20b，且第一表面20a具有複數第一連接墊2〇2， 第二表面20b具有複數第二連接墊2〇3 ; 一第二封裝結構 2’，係包含有一第二晶片21，及一第二封裝基板2〇，，其中第 二晶片21’係與第二封裝基板20’電性連接，而第二封裝棊板 20’具有一第一表面20a’及相對之一第二表面2〇b’，且第二 表面20b’具有複數第二連接塾203,； 一表面陶竟化之紹金屬 板3，係配.置於第一封裝結構2與第二封裝結構2，之間，且 該表面陶瓷化之鋁金屬板3具有複數通孔31及一第一開口 32，該些通孔31之相對兩端係分別對應第一封裝結構2之該 些第一連接塾202及第二封裝結構2’之該些第二連接塾 203’，而第一開口32内容置有第一晶片21 ;以及一金屬膏 4’係填充於該表面陶瓷化之鋁金屬板3之該些通孔31令， 12 1360217 以電性連接第一封裝結構2之該些第一連接墊2〇2與第二封. 裝結構2’之該些第二連接墊2〇3,。 又如圖2C’所示係本實施例之另一態樣，其結構與圖2c 大致相同，惟不同處在於，第一封裝結構5與第二封裝結構 5 5為覆晶封裝結構。 實施例2 本實施例大致與實施例丨相同，惟不同處在於，請參見 圖3A，本實施例之第二晶片21’係設置於第二封裝基板 之第二表面20b’上，而該表面陶瓷化之鋁金屬板3復具有一 10 第二開口 33，俾以容置第二晶片21，。 又如圖3A，所示係本實施例之另一態樣，其結構與圖 3A大致相同，惟不同處在於，第一封裝結構5與第二封裝結 構5’為覆晶封裝結構。 實施例3 15 本實施例大致與實施例2相同，惟不同處在於，請參見 圖3B，本實施例之第一封裝基板2〇之第一表面2如上復具有 至少一第一被動元件23,而該表面陶瓷化之鋁金屬板3復具 有至少一第三開口 34,俾以容置該至少一第一被動元件Μ、。 又如圖3B，所示係本實施例之另一態樣，其結構與圖邛 20 大致相同，惟不同處在於，第一封裝結構5與第二封裝結構 5為覆晶封裝結構。 實施例4 本實施例大致與實施例3相同，惟不同處在於，請參見 圖3C，本實施例之第二封裝基板20’之第二表面2〇b，上復具 13 1360217 有至少一第二被動元件23’，而該表面陶瓷化之鋁金屬板3 復具有至少一第四開口35，俾以容置該至少一第二被動元 件 23’。 又如圖3C’所示係本實施例之另一態樣，其結構與圖3c 5 大致相同，惟不同處在於，第一封裝結構5與第二封裝結構 5’為覆晶封裝結構。 上述實施例僅係為了方便說明而舉例而已，本發明所 主張之權利範圍自應以申請專利範圍所述為準，而非僅限 於上述實施例。 10 【圖式簡單說明】 圖1係習知之堆疊式封裝模組剖視圖。 圖2A至2C係本發明一較佳實施例之堆疊式封裝模組製作 流程剖視圖。 15 圖3A至圖3C’係本發明其他較佳實施例之堆疊式封裝模組 剖視圖。 【主要元件符號說明】 1,2,5 1’，2’,5’ 10 10a，20a，20a，，50a，50a’ l〇b,20b,20b5,50b,50b* 101,201 102,202,502 第一封裝結構 第二封裝結構 封裝基板 第一表面 第二表面 打線焊墊 第一連接墊 1360217 103,203,203*,503,5035 第二連接墊 104 焊料球 11 晶片 1 la,21a,5 la 作用面 111,211,511 電極墊 14,24 金屬線 15,25 封膠材料 20,50 第一封裝基板 20，，50’ 第二封裝基板 21,51 第一晶片 21，，51， 第二晶片 23,53 第一被動元件 23，，53’ 第二被動元件 3 表面陶瓷化之鋁金屬板 31 通孔 32 第一開口 33 第二開口. 34 第三開口 35 第四開口 4 金屬膏 504 第三連接墊 56 焊料凸塊 57 底膠材料 15According to this embodiment, the present invention provides a stacked package module. Referring to FIG. 2C', the first package structure 2 includes a first wafer. And a first package substrate 20, wherein the first wafer 21 is electrically connected to the first package substrate, and the first package substrate 2G has a second surface 20b opposite to the first surface, and the first surface 20a The second surface 20b has a plurality of second connection pads 2〇3, and the second package structure 2' includes a second chip 21 and a second package substrate 2? The second chip 21 ′ is electrically connected to the second package substrate 20 ′, and the second package 20 20 ′ has a first surface 20 a ′ and a second surface 2 〇 b ′, and the second surface 20 b 'There is a plurality of second ports 203, a surface metal plate 3, which is placed between the first package structure 2 and the second package structure 2, and the surface is ceramized aluminum metal plate 3 has a plurality of through holes 31 and a first opening 32, and the opposite ends of the through holes 31 respectively correspond to the second connecting ports 202 of the first package structure 2 and the second portions of the second package structure 2' Connecting the crucible 203', and the first opening 32 is provided with the first wafer 21; and a metal paste 4' is filled with The through holes 31 of the surface ceramized aluminum metal plate 3 are such that the 12 1360217 electrically connects the first connection pads 2 〇 2 of the first package structure 2 and the second package structure 2 ′ Two connection pads 2〇3,. 2C' is another aspect of the embodiment, and its structure is substantially the same as that of FIG. 2c, except that the first package structure 5 and the second package structure 5 5 are a flip chip package structure. Embodiment 2 This embodiment is substantially the same as the embodiment, except that, in FIG. 3A, the second wafer 21' of the embodiment is disposed on the second surface 20b' of the second package substrate, and the surface is The ceramized aluminum metal plate 3 has a 10 second opening 33 for accommodating the second wafer 21. 3A, another embodiment of the present embodiment is shown, and its structure is substantially the same as that of FIG. 3A except that the first package structure 5 and the second package structure 5' are a flip chip package structure. The first embodiment 2 of the first package substrate 2 of the present embodiment has at least one first passive component 23 as described above, and the difference is that the first surface 2 of the first package substrate 2 of the present embodiment has at least one first passive component 23 as described above. The surface ceramized aluminum metal plate 3 has at least one third opening 34 for receiving the at least one first passive component. 3B, another aspect of the embodiment is shown, the structure of which is substantially the same as that of FIG. 20, except that the first package structure 5 and the second package structure 5 are a flip chip package structure. Embodiment 4 This embodiment is substantially the same as Embodiment 3. The difference is that, referring to FIG. 3C, the second surface 2〇b of the second package substrate 20' of the present embodiment has at least one first 13 1360217 The second passive component 23', and the surface ceramized aluminum metal plate 3 has at least one fourth opening 35 for receiving the at least one second passive component 23'. Another embodiment of the present embodiment is shown in Fig. 3C', and its structure is substantially the same as that of Fig. 3c, except that the first package structure 5 and the second package structure 5' are flip chip packages. The above-described embodiments are merely examples for the convenience of the description, and the scope of the claims is intended to be limited by the scope of the claims. 10 [Simple description of the drawings] Fig. 1 is a cross-sectional view of a conventional stacked package module. 2A to 2C are cross-sectional views showing a manufacturing process of a stacked package module according to a preferred embodiment of the present invention. 15A through 3C are cross-sectional views of a stacked package module in accordance with another preferred embodiment of the present invention. [Description of main component symbols] 1,2,5 1',2',5' 10 10a,20a,20a,,50a,50a' l〇b,20b,20b5,50b,50b* 101,201 102,202,502 First package structure Second package structure package substrate first surface second surface wire bonding pad first connection pad 1360217 103, 203, 203*, 503, 5035 second connection pad 104 solder ball 11 wafer 1 la, 21a, 5 la active surface 111, 211, 511 electrode pad 14, 24 metal Line 15, 25 sealing material 20, 50 first package substrate 20, 50' second package substrate 21, 51 first wafer 21, 51, second wafer 23, 53 first passive component 23, 53' Two passive elements 3 surface ceramized aluminum metal plate 31 through hole 32 first opening 33 second opening. 34 third opening 35 fourth opening 4 metal paste 504 third connection pad 56 solder bump 57 primer material 15

Claims (1)

1360217 第96141601號，100年9月修正頁 十、申請專利範圍： ι· 一種堆疊式封裝模組，包括： ~ ~! 一第一封裝結構，係包含有一第一晶片及一第一封裝 基板’其中第一封裝基板具有一第一表面及相對之一第二 5 表面，而第一晶片係設置於第一封裝基板之第一表面上並 與第一封裝基板電性連接，且第一封裝基板之第一表面具 有複數第一連接墊，而第二表面具有複數第二連接墊； 一第二封裝結構，係包含有一第二晶片及一第二封裝 基板其中第一封裝基板具有一第一表面及相對之一第二 10表面，而第二晶片係設置於第二封裝基板之第二表面上並 與第二封裝基板電性連接，且第二封裝基板之第二表面具 有複數第二連接墊並面向第一封裝基板之第一表面； 一表面陶瓷化之鋁金屬板，係配置於第一封裝結構與 第一封裝結構之間，其中，該表面陶瓷化之鋁金屬板具有 15 一第一開口及一第二開口，俾以分別容置第一晶片及第二 曰曰片，且該表面陶瓷化之鋁金屬板復具有複數通孔，該些 通孔之相對兩端係分別對應第一封裝結構之該些第一連接 塾及第二封裝結構之該些第二連接墊；以及 金屬膏，係填充於該表面陶瓷化之鋁金屬板之該些 通孔中以電性連接第一封裝結構之該些第一連接墊與第 一封裝結構之該些第二連接墊。 2·如申請專利範圍第1項所述之封裝模組，其令，第 封裝基板之第一表面復包括複數打線焊墊，且第一晶片 1360217 係藉由複數金屬線而與第一封裝基板之打線焊墊電性連 接。 3. 如申請專利範圍第丨項所述之封裝模組，其中，第 一封裝基板之第一表面復包括複數第三連接墊，且第一晶 5 片係藉由複數焊料凸塊以覆晶方式而與第一封裝基板之第 三連接墊電性連接。 4. 如申請專利範圍第1項所述之封裝模組，其中，第 二封裝基板之第二表面復包括複數打線焊墊，且第二晶片 係藉由複數金屬線而與第二封裝基板之打線焊墊電性連 10 接。 5.如申請專利範圍第1項所述之封裝模組，其中，第 二封裝基板之第二表面復包括複數第三連接墊，且第二晶 片係藉由複數焊料凸塊以覆晶方式而與第二封裝基板之第 三連接墊電性連接。 15 6.如申請專利範圍第1項所述之封裝模組，其中，第 一封裝基板之第一表面上復具有至少一第一被動元件而 該表面陶瓷化之鋁金屬板復具有至少一第三開口，俾以容 置該至少一第一被動元件。 7. 如申請專利範圍第6項所述之封裝模組’其中，第 20二封裝基板之第二表面上復具有至少一第二被動元件，而 該表面陶瓷化之鋁金屬板復具有至少一第四開口俾以容 置該至少一第二被動元件。 & 8. 如申請專利範圍第丨項所述之封裝模組，其中，該 金屬膏為銅膏及銀膏之其中一者。 Μ 17 1360217 9. 一種堆疊式封裝模組之製法，包括： 提供一表面陶瓷化之鋁金屬板，係具有一第一開口、 一第二開口及複數通孔； 填充一金屬膏於該些通孔内；以及 5 接置一第一封裝結構及一第二封裝結構於該表面陶瓷 化之鋁金屬板之兩相對表面，並使該金屬膏電性連接第一 封裝結構與第二封裝結構，其中，第一封裝結構係包含有 一第一晶片及一第一封裝基板，第一封裝基板具有一第一 表面及相對之一第二表面，而第一晶片係接置於第一封裝 10 基板之第一表面上並與第一封裝基板電性連接，且第一晶 片係容置於該表面陶瓷化之鋁金屬板之第一開口，又第一 封裝基板之第一表面具有複數第一連接墊，而第二表面具 有複數第二連接墊；第二封裝結構係包含有一第二晶片及 一第二封裝基板，第二封裝基板具有一第一表面及相對之 15 一第二表面，而第二晶片係接置於第二封裝基板之第二表 面上並與第二封裝基板電性連接，且第二晶片係容置於該 表面陶瓷化之鋁金屬板之第二開口，又第二封裝基板之第 二表面具有複數第二連接墊並面向第一封裝基板之第一表 面；且該表面陶瓷化之鋁金屬板之該些通孔之相對兩端係 20 分別對應第一封裝結構之該些第一連接墊及第二封裝結構 之該些第二連接墊，俾使第二封裝結構之該些第二連接墊 係藉由該金屬膏與第一封裝結構之該些第一連接墊電性連 接。 1360217 10. 如申請專利範圍第9項所述之製法，其中，該金屬 膏係藉由印刷或點膠法而填充於該些通孔内。 11. 如申請專利範圍第9項所述之製法，其中，第一封 裝基板之第一表面復包括複數打線焊墊，且第一晶片係藉 5 由複數金屬線而與第一封裝基板之打線焊墊電性連接。S 12·如申請專利範圍第9項所述之製法，其中，第一封 裝基板之第一表面復包括複數第三連接墊，且第一晶片係 藉由複數焊料凸塊以覆晶方式而與第一封裝基板之第三連 接墊電性連接。 10 13.如申請專利範圍第9項所述之製法，其中，第二封 裝基板之第二表面復包括複數打線焊墊，且第二晶片係藉 由複數金屬線而與第二封裝基板之打線焊塾電性連接。 14. 如申請專利範圍第9項所述之製法，其中，第二封 裝基板之第二表面復包括複數第三連接整*，且第二晶片係 I5 藉由複數焊料凸塊以覆晶方式而與第二封裝基板之第三連 接墊電性連接。 15. 如申請專利範圍第9項所述之製法，其中，第一封 裝基板之第一表面上復接置有至少一第一被動元件，而該 表面陶瓷化之鋁金屬板復具有至少一第三開口，俾以容置 20 該至少一第一被動元件。 16. 如申請專利範圍第15項所述之製法，其中，第二封 裝基板之第二表面上復接置有至少一第二被動元件，而該 表面陶瓷化之鋁金屬板復具有至少一第四開口，俾以容置 該至少一第二被動元件。 1360217 17.如申請專利範圍第15項所述之製法，其中，該金屬 膏為銅膏及銀膏之其中一者。 201360217 No. 96111601, revised in September, 100. Patent application scope: ι· A stacked package module comprising: ~~! A first package structure comprising a first chip and a first package substrate The first package substrate has a first surface and a second surface, and the first chip is disposed on the first surface of the first package substrate and electrically connected to the first package substrate, and the first package substrate The first surface has a plurality of first connection pads, and the second surface has a plurality of second connection pads; a second package structure includes a second chip and a second package substrate, wherein the first package substrate has a first surface And a second surface of the second package, the second chip is disposed on the second surface of the second package substrate and electrically connected to the second package substrate, and the second surface of the second package substrate has a plurality of second connection pads And facing the first surface of the first package substrate; a surface ceramized aluminum metal plate disposed between the first package structure and the first package structure, wherein the surface ceramized aluminum The slab has a first opening and a second opening, respectively, for accommodating the first wafer and the second cymbal, and the surface ceramized aluminum metal plate has a plurality of through holes, and the through holes are opposite The second connection pads respectively corresponding to the first connection ports and the second package structures of the first package structure; and the metal paste are filled in the through holes of the surface ceramized aluminum metal plate The first connection pads of the first package structure and the second connection pads of the first package structure are electrically connected. 2. The package module of claim 1, wherein the first surface of the package substrate comprises a plurality of wire bonding pads, and the first chip 1360217 is connected to the first package substrate by a plurality of metal wires. The wire bonding pad is electrically connected. 3. The package module of claim 1, wherein the first surface of the first package substrate comprises a plurality of third connection pads, and the first crystal 5 is covered by a plurality of solder bumps. The method is electrically connected to the third connection pad of the first package substrate. 4. The package module of claim 1, wherein the second surface of the second package substrate comprises a plurality of wire bonding pads, and the second chip is formed by the plurality of metal wires and the second package substrate The wire bonding pad is electrically connected to 10 wires. 5. The package module of claim 1, wherein the second surface of the second package substrate comprises a plurality of third connection pads, and the second chip is flip chip by a plurality of solder bumps. The third connection pad of the second package substrate is electrically connected. The package module of claim 1, wherein the first surface of the first package substrate has at least one first passive component and the surface ceramized aluminum metal plate has at least one The three openings are configured to receive the at least one first passive component. 7. The package module of claim 6, wherein the second surface of the 20th package substrate has at least one second passive component, and the surface ceramized aluminum metal plate has at least one The fourth opening is configured to receive the at least one second passive component. < 8. The package module of claim 2, wherein the metal paste is one of a copper paste and a silver paste. Μ 17 1360217 9. A method of manufacturing a stacked package module, comprising: providing a surface ceramized aluminum metal plate having a first opening, a second opening and a plurality of through holes; filling a metal paste in the through holes And a second package structure and a second package structure are disposed on the opposite surfaces of the surface ceramized aluminum metal plate, and the metal paste is electrically connected to the first package structure and the second package structure, The first package structure includes a first chip and a first package substrate. The first package substrate has a first surface and a second surface, and the first chip is connected to the first package 10 substrate. The first surface is electrically connected to the first package substrate, and the first wafer is received in the first opening of the surface ceramized aluminum metal plate, and the first surface of the first package substrate has a plurality of first connection pads The second surface has a plurality of second connection pads; the second package structure includes a second chip and a second package substrate, the second package substrate has a first surface and an opposite first surface and a second surface And the second chip is connected to the second surface of the second package substrate and electrically connected to the second package substrate, and the second wafer is received in the second opening of the surface ceramized aluminum metal plate, The second surface of the second package substrate has a plurality of second connection pads facing the first surface of the first package substrate; and the opposite ends of the through holes of the surface ceramized aluminum metal plate respectively correspond to the first package The first connection pads of the structure and the second connection pads of the second package structure, such that the second connection pads of the second package structure are formed by the metal paste and the first package structure The connection pads are electrically connected. The method of claim 9, wherein the metal paste is filled in the through holes by printing or dispensing. 11. The method of claim 9, wherein the first surface of the first package substrate comprises a plurality of wire bonding pads, and the first chip is bonded to the first package substrate by a plurality of metal wires. The pads are electrically connected. The method of claim 9, wherein the first surface of the first package substrate comprises a plurality of third connection pads, and the first wafer is flipped by a plurality of solder bumps. The third connection pad of the first package substrate is electrically connected. The method of claim 9, wherein the second surface of the second package substrate comprises a plurality of wire bonding pads, and the second chip is bonded to the second package substrate by the plurality of metal wires. Solder joints are electrically connected. 14. The method of claim 9, wherein the second surface of the second package substrate comprises a plurality of third connections, and the second wafer system I5 is flipped by a plurality of solder bumps. The third connection pad of the second package substrate is electrically connected. 15. The method of claim 9, wherein the first surface of the first package substrate is multiplexed with at least one first passive component, and the surface ceramized aluminum metal plate has at least one The three openings are configured to receive the at least one first passive component. 16. The method of claim 15, wherein the second surface of the second package substrate is multiplexed with at least one second passive component, and the surface ceramized aluminum metal plate has at least one The four openings are configured to receive the at least one second passive component. The method of claim 15, wherein the metal paste is one of a copper paste and a silver paste. 20
TW96141601A 2007-11-02 2007-11-02 Stacked packaging module and method for manufactur TWI360217B (en)

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