TWI341461B - Programmable delay cell and a controller, a printed circuit board and a computer apparatus having the same, methods for using the same and an article holding instructions for testing timing of signals between a controller and a devices - Google Patents

Programmable delay cell and a controller, a printed circuit board and a computer apparatus having the same, methods for using the same and an article holding instructions for testing timing of signals between a controller and a devices

Info

Publication number
TWI341461B
TWI341461B TW093130739A TW93130739A TWI341461B TW I341461 B TWI341461 B TW I341461B TW 093130739 A TW093130739 A TW 093130739A TW 93130739 A TW93130739 A TW 93130739A TW I341461 B TWI341461 B TW I341461B
Authority
TW
Taiwan
Prior art keywords
controller
same
signals
circuit board
printed circuit
Prior art date
Application number
TW093130739A
Other languages
English (en)
Other versions
TW200525349A (en
Inventor
Tsvika Kurts
Zelig Wayner
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of TW200525349A publication Critical patent/TW200525349A/zh
Application granted granted Critical
Publication of TWI341461B publication Critical patent/TWI341461B/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/405—Coupling between buses using bus bridges where the bridge performs a synchronising function
    • G06F13/4059—Coupling between buses using bus bridges where the bridge performs a synchronising function where the synchronisation uses buffers, e.g. for speed matching between buses

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Logic Circuits (AREA)
  • Pulse Circuits (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Dram (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
TW093130739A 2003-10-16 2004-10-11 Programmable delay cell and a controller, a printed circuit board and a computer apparatus having the same, methods for using the same and an article holding instructions for testing timing of signals between a controller and a devices TWI341461B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/685,418 US20050083095A1 (en) 2003-10-16 2003-10-16 Adaptive input/output buffer and methods thereof

Publications (2)

Publication Number Publication Date
TW200525349A TW200525349A (en) 2005-08-01
TWI341461B true TWI341461B (en) 2011-05-01

Family

ID=34465468

Family Applications (1)

Application Number Title Priority Date Filing Date
TW093130739A TWI341461B (en) 2003-10-16 2004-10-11 Programmable delay cell and a controller, a printed circuit board and a computer apparatus having the same, methods for using the same and an article holding instructions for testing timing of signals between a controller and a devices

Country Status (6)

Country Link
US (1) US20050083095A1 (zh)
JP (1) JP2007509541A (zh)
CN (3) CN1894679B (zh)
DE (1) DE112004003057B4 (zh)
TW (1) TWI341461B (zh)
WO (1) WO2005038657A2 (zh)

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US7529955B2 (en) * 2005-06-30 2009-05-05 Intel Corporation Dynamic bus parking
US8819474B2 (en) * 2009-04-03 2014-08-26 Intel Corporation Active training of memory command timing
TWI489718B (zh) * 2009-10-14 2015-06-21 Inventec Appliances Corp 儲存裝置及其運作方法
US8806093B2 (en) * 2010-04-01 2014-08-12 Intel Corporation Method, apparatus, and system for enabling a deterministic interface
US20140380000A1 (en) * 2013-06-20 2014-12-25 Silicon Motion, Inc. Memory controller and accessing system utilizing the same
KR102628533B1 (ko) * 2016-08-16 2024-01-25 에스케이하이닉스 주식회사 반도체장치 및 반도체시스템
CN108009372B (zh) * 2017-12-15 2020-07-31 中国科学院计算技术研究所 一种ddr内存虚拟写电平校准响应的方法
US11079946B2 (en) 2018-10-26 2021-08-03 Micron Technology, Inc. Write training in memory devices
CN109857684B (zh) * 2019-01-04 2020-11-06 烽火通信科技股份有限公司 通信设备板卡槽位地址和类型识别的装置、方法和系统
CN112035520A (zh) * 2019-06-03 2020-12-04 吕纪竹 一种实时判断流数据自身给定延迟重复性的方法
CN112069768B (zh) * 2020-09-08 2024-07-16 飞腾信息技术有限公司 一种针对双端口sram输入输出延时优化的方法

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Also Published As

Publication number Publication date
CN102880582A (zh) 2013-01-16
WO2005038657A2 (en) 2005-04-28
CN1894679B (zh) 2012-09-19
CN1894679A (zh) 2007-01-10
JP2007509541A (ja) 2007-04-12
US20050083095A1 (en) 2005-04-21
TW200525349A (en) 2005-08-01
WO2005038657A3 (en) 2005-06-16
DE112004003057B4 (de) 2011-09-15
DE112004003057A1 (de) 2008-12-18
CN104978297A (zh) 2015-10-14
CN102880582B (zh) 2016-04-27
CN104978297B (zh) 2019-06-28

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees