TWI312544B - Semiconductor device, cmos device and p-type semiconductor device - Google Patents

Semiconductor device, cmos device and p-type semiconductor device Download PDF

Info

Publication number
TWI312544B
TWI312544B TW095129773A TW95129773A TWI312544B TW I312544 B TWI312544 B TW I312544B TW 095129773 A TW095129773 A TW 095129773A TW 95129773 A TW95129773 A TW 95129773A TW I312544 B TWI312544 B TW I312544B
Authority
TW
Taiwan
Prior art keywords
region
substrate
source
field effect
effect transistor
Prior art date
Application number
TW095129773A
Other languages
English (en)
Other versions
TW200713467A (en
Inventor
Chung-Hu Ke
Chih-Hsin Ko
Hung-Wei Chen
Wen-Chin Lee
Min-Hwa Chi
Original Assignee
Taiwan Semiconductor Mfg
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Mfg filed Critical Taiwan Semiconductor Mfg
Publication of TW200713467A publication Critical patent/TW200713467A/zh
Application granted granted Critical
Publication of TWI312544B publication Critical patent/TWI312544B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/8252—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using III-V technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/8258—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213, H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H01L27/1207—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Description

1312544 九、發明說明： 【發明所屬之技術領域】 本發明係有關於半導體製造’並且特別有關於一種 具有金屬一半導體及源極/汲極接面之互補型金氧半導體 (complimentary metal oxide semiconductor; CMOS)裝置之 製造方法。 【先前技術】 現今裝置所普遍使用之電性接面（contact)係金屬 半導體接面。根據材料而定，接面可能為歐姆 或整流型（rectifying)。一歐姆型接面不論所流通的 1C) 向為何，皆具有低電阻 體相同 整流型接面’其行為 電流方 與 柘
，這是由於其在某一方向能夠讓電流自由流通 然而卻在另一方向具有一會阻擔電流之能障。# 障’即所謂的肖特基（Sch〇ttky)能障，是電子從金屬〜 至半導體所需要的電位能，並且是決定金屬〜半導= 面之電性的一項重要參數。 近來，先進半導體裝置係使用金屬一半導體接甸 即肖特基接面，來作為CMOS之源極和/或汲極。 有肖特基源極/汲極之CMOS，對於45奈米以下之聲置:、 縮目標，乃擁有眾多利益。此源極/j：及極之金屬/石夕化物^ 有低電阻值，並且在原子尺寸級上不連續。這使得其戽 對於傳統雜質摻雜之源極/汲極技術而言，能夠戽有相 的裝置速率以及尺寸可加以微縮等優點。此種金屬^ IG 接 高 0503-A31336TWF/Ching Yen 5 1312544 物源極/汲極對通道而言會形成一肖特基能障，.因而能使 得切斷漏電流降低。肖特基源極/汲極技術降低了通道區 所需的摻雜量，因而使通道產生較高之移動率 (Mobility)。此外，肖特基源極/没極製程可能包含當今最 優良之CMOS技術，包括：單晶片系統（SOI)上之CMOS、 束缚石夕（strained Si)技術、金屬閘極以及高介電質閘極， • 矽鍺張力技術，以及其餘更多的半導體製造技術。 • 雖然肖特基源極/汲極擁有顯而易見的優點，將肖特 • 基源極/汲極技術整合至現今的製造方法仍面臨眾多挑 戰。舉例而言，源極處的高肖特基能障會大幅降低肖特 基CMOS的驅動電流。為了解決這個問題，源極接面之 肖特基能障低於〇.2eV是有必要的。許多新的源極/汲極 材料，比方是製造NMOS之ErSi2或製造PMOS之PtSi， 已經被加以研究。然而，這些材料並非時時都能成功地 整合。新材料導致現有製造步驟必須再度最佳化，這些 製程步驟譬如是金屬沉積、石夕化（Silicidation)、以及# • 刻…等等於肖特基源極/汲極方法前所實行之步驟。 鑒於這些以及其餘問題，有必要改善肖特基源極/汲 極之製造方法。金屬一半導體之電性必須加以控制，但 是新方法不應當額外地引起其他製造方法所出現的問 題。可進行的方向是利用現有的材料來開發新的肖特基 源極/汲極方法，藉此以儘量減少那些會妨礙傳統方法之 整合問題。 0503-A31336TWF/Ching Yen 6 ' 1312544 » - 【發明内容】 藉由本發明之較佳實施例，其中肖特基源極/汲極係 使用一混合基板（hybrid substrate)以降低NMOS及PMOS 之肖特基能障，能夠廣泛地解決上述及其餘問題，並且 達到技術性的優點。 本發明之較佳實施例中係提供一半導體裝置。該半 • 導體裝置係包括一基板，該基板具有一第一區域及一第 . 二區域，該第一區域具有一第一晶向，該第一晶相係利 φ 用一組米勒指數（Miller indices){i,j,k}來加以表示，該第 二區域係具有一第二晶向，該第二晶相係利用一組米勒 指數{l，m,n}來加以表示。在本發明之較佳實施例中， l2+m2+n2 > i2+j2+k2。替代實施例更包括一 NMOS場效電 晶體形成於該第一區域上，以及一第二PMOS場效電晶 體形成於該第二區域上。實施例更包括一與NMOS場效 電晶體或PMOS場效電晶體共同形成之肖特基接面。 替代實施例係更包括一互補型金氧半裝置（CMOS) • 裝置。該CMOS裝置係包括一基板，該基板係具有一第 一區域及一第二區域，該第一區域具有一第一晶向，該 第二區域係具有一第二晶向，該第一晶向與第二晶向係 不相同。替代實施例更包括一 NMOS場效電晶體形成於 該第一區域上，該NMOS場效電晶體係包括一 NMOS源 極，一NMOS汲極，以及一肖特基接面，該肖特基接面 係與該NMOS源極與NMOS汲極至少當中之一共同形 成；以及一 PMOS場效電晶體形成於該第二區域上，該 0503-A31336TWF/Ching Yen 7 1312544 PMOS場效電晶體係包括一 PMOS源極，一 PMOS汲極， 以及一肖特基接面，該肖特基接面係與該PMOS源極與 PMOS汲極至少當中之一共同形成。 更多其他的實施例係包括一 P型半導體裝置。實施 例包括一基板’一 ΡΜΌS源極於該基板上，以及一 PMOS 没極於該基板上。較佳之情況為，該PMOS源極與該 ' PMOS汲極至少當中之一係包括一肖特基接面，其中該 • PMOS源極與該PMOS汲極係在兩者之間定義出一通 • 道。較佳之情況為該通道之晶向係利用一組米勒指數 〇山]^}來表示，其中12+尸+]^〉1(或12+1112+112>2)。 【實施方式】 本發明較佳實施例之製造和使用係於以下討論。然 而，應當理解的是，本發明所提供之眾多可應用之創造 性觀念，可使用廣泛之各種特定文句加以具體化。在此 所討論之特定實施例係僅用來說明本發明之製造和使用 # 之特定方式，而不限制本發明之範圍。 當一金屬接觸一半導體時，金屬一半導體介面處會 建立出一能障。此能障（或能障高度）係與金屬和半導體功 函數之差異、介面狀態密度（state density)以及半導體之 摻雜級(doping level)有關。當狀態密度不存在時，能障高 度係主要由金屬和半導體功函數之差異來決定。如果金 屬的表面狀態密度很大時，能障高度則由半導體表面來 決定，而與金屬的功函數無關。而如果半導體表面之表 0503-A31336TWF/Ching Yen 8 1312544 面狀態密度很大時，則費米能階（Fermi level)會被這些表 面狀態固定住，而能障高度就介於這些極限之間。較佳 上，電子或電洞的能障高度約不高於〇.4eV。 表面狀態密度係與表面晶向密切相關。在矽材料 内，{100丨晶向的表面狀態密度約較{111}晶向之狀態密 度小了約1個數量級（即約小了 10倍）。影響表面狀態密 度之已知因素當中之一是矽表面上單位面積内之鍵結數 量。 本發明將利用特定之文句並針對較佳實施例來加以 描述，即混合基板上CMOS之製作，其中該基板之晶向 之決定係考量到NMOS與PMOS兩者能具有低的肖特基 能障。為了方便起見，一包括一互相接合之金屬及一半 導體之結構，即使在本領域内普遍被稱為肖特基二極體 或肖特基能障接面，在此係稱為肖特基接面。而在此所 謂的肖特基能障意指金屬/半導體接面。 普遍而言，於ULSI電路内，主要之構成區塊係CMOS 邏輯閘，該CMOS邏輯閘係包括至少一 N型場效電晶體 或至少一 P型場效電晶體。絕緣層上覆矽 (silicon-on-insulator)之基板可用來製造一 CMOS邏輯 閘，當中之P型場效電晶體與N型場效電晶體中係具有 不同晶向，用以提供最佳電洞與電子移動率。裝置可為 平面結構或多閘結構，譬如是三閘結構(trigate)或是鰭式 場效電晶體(FinFET)。一較佳實施例之優點之一係在於： 當載子移動率增加時，邏輯閘之實際面積（real estate)會 0503-A31336TWF/Ching Yen 9 1312544 減少。因此，藉由最佳化晶向以改善載子移動率，可大 幅卽省整個半導體晶片之實際面積。此外，製造成本也 能有效降低。較佳貫施例之另一優點在於浮體效應 (floating body effect)可緩和下來。 現參考第1A至1Η圖’其說明本發明較佳實施例之 循序製造步驟。第1Α至1Η圖顯示一標準絕緣層上覆石夕 (silicon on insulator ; SOI)結構之剖面圖，該s〇I係根據 以下所述之傳統技術來與一矽基板相結合。該 係包括一矽材料層’其厚度約介於2至200奈求之門 較佳上約為40奈米。依據本發明所提供之較佳實於曰 第1A圖係包括一石夕基板202 ’其具有一經過選擇之a 表面晶向與一掺雜級。位於該基板上方的是—八 質（氧化物）層BOX 204〇BOX204的厚度可約為1〇 ;1屯 奈米，較佳上為50奈米。位於BOX204上方的是—2()() 矽基板206，其具有一經過選擇之第二表面晶向與 1 雜級。最後’位於SOI矽基板206上方的是—氮化物換 成之硬遮罩層208。未以调例顯不之替代實施例之替、 實施例包括由鍺（Ge)、碳化矽（SiC)、砷化鎵（GaAs)代性 化鋁鎵（GaAlAs)、磷化銦（InP)、氮化鎵（GaN)、石夕錯（s .申 以及SiGe等漸變緩衝(grader buffer)材料所構成之 e) 板。混合基板可有一部分區域具有如{1〇〇}及{1 ▲狀基 向。更者’ BOX 204除了包括氧化物外，可包括人曰曰 質層，譬如是氮化矽（Silicon Nitride)。 ；丨電 接下來，於第1B圖中，光阻210係被涂# '復、製作圖 0503-A31336TWF/Ching Yen 10 1312544 案以及顯影。開口 212係激袢士办办從ή明 一 、基1^成牙越應遮罩層208及第 一石夕基板層2G6,而變成第lc圖所顯示之開口 212。開 口 212繼而被填滿—適宜的隔離用絕緣材料214,如二氧
化石夕，用以與主動區域作電性 M 〜印电性隔離，以猎此避免接面短 路，如弟1D圖所示。 斤接下來’於第1E圖中’ _第二光阻層216被塗覆。 該第f光阻層216被製作圖案以及關，而成為第1F 圖並且開口 218係製造成穿越隔離用絕緣材料aw中 所選擇的部分區域。隔離用絕緣層料214當中部分係於 第2£圖所示步驟實行後係留存下來，以用作淺溝槽隔離 (shallow t職h lsolati〇n; STI)，即最終元件中的區域㈣。 、接下來’於f1G圖中，一由石夕構成之蟲晶層222係 成長於石夕基板202上。蠢晶層222之晶向與石夕基板搬 之晶向相同。接下來，第1Η圖所示之多層結構係進行一 平坦化（planarized)製程’藉此以形成一具有多晶向而 合用於製造裝置之基板。 在形容種種不同的實施例時，使用晶學領域之慣用 術語與命名是有助益的。舉例而言，為人熟知的米勒指 數在此係用來描述晶面及晶向。由於此處所揭露之較^ 貝靶例包含矽材料，具本領域之通常技術者明瞭米勒指 數指的是面心立方晶體結構。繼續使用晶學領域之^ 名’ [xyz]與（xyz)係分別描述特定方向與平面，<xyz>與 {xyz}則係分別描述一種或一組方向與平面。舉例而古， [_1，〇，1]、[0，1，1]、[0，-1，0]以及[1，0，1]係屬<11〇>方向級合 0503-A31336TWF/Ching Yen 11 1312544 中之特定方向。具本領域之通常技術者亦能明瞭，藉由 參考特定的米勒指數來描述一實施例有時是有助益的。 然而’除非文句能明白指出’參考特定方向和平面僅僅 是為了方便與清晰之目的而已。當參考其餘相似類型之 晶向或方向也是同樣適用時’一實施例係不限制至單一 晶向或單一方向。 參考第2圖，圖中顯示本發明所提供一 CMOS裝置 • 之較佳實施例。該CMOS裝置係包括一 pm〇S場效電晶 _ 體251於一 PMOS場效電晶體混合基板252上，以及— NMOS場效電晶體253於一 NMOS場效電晶體混合基板 256上。不同混合基板係彼此隔離，譬如是利用淺溝槽隔 離（STI) 258。CMOS裝置250内係包含一閘極介電質層 259與一閘極261。 適合作為閘極介電質259之材料包含：多晶矽或完 全石夕化錄多晶石夕、金屬氧化物，譬如為Al2〇3、Zr02、 Hf02、Y2O3、La203、Ti02、Ta205 ;或是矽酸鹽類 • (silicates)，譬如為 ZrSi04、ZrSiN、HfSi04、HfSiON、 HfSiN;或是氧化物，譬如為二氧化矽（Si02)及氮氧化矽 (silicon oxynitride)。 適合作為閘極261之材料包含：金屬閘，其包括Mo、 Ru、Ti、Ta、W或Hf;氮化金屬堆疊閘；金屬氧化物閘， 譬如為Ru〇2或Ir02 ;金屬氮化物閘，譬如為MoN，WN、 TiN、TaN、TaAIN、TASiN ;多晶矽；或多晶 SiGe 閘。 替代實施例亦包括石夕化物閘，譬如為CoSi2或NiSi。 0503-A31336TWF/Ching Yen 12 1312544 * » 接著參考第2圖，於較佳實施例中，PMOS場效電晶 體251包含源極263及汲極266，其中源極263及汲極 266係包括一肖特基接面。同樣地，NMOS場效電晶體 253包含源極269及汲極272，其中源極269及汲極272 係包括一肖特基接面。在替代實施例中，未以圖示顯示， 僅有PMOS場效電晶體或僅有NMOS場效電晶體包含一 • 肖特基接面。在另外之替代實施例中，未以圖示顯示， • 僅有源極或僅有汲極包含一肖特基能障。為了方便起 φ 見，肖特基源極/汲極係用來稱呼一包含一肖特基接面之 沒極，或是一包含一肖特基接面之源極，或是兩者之組 合。 較佳的情況是，PMOS場效電晶體混合基板252具有 {110}晶向而NMOS場效電晶體混合基板256具有{100} 晶向。於{110}晶向的矽基板上形成一肖特基源極/汲極 PMOS場效電晶體是較佳的，這是因為這個晶向能使電洞 的肖特基能障高度降至最低。同樣地，於{100}晶向的矽 • 基板上形成一肖特基源極/汲極NMOS場效電晶體是較佳 的，這是因為這種晶向能使電子的肖特基能障高度降至 最低。此源極/沒極係藉由沉積一金屬或一金屬碎化物而 形成，較佳的情況是使用單一金屬以降低N型或P型裝 置之能障高度。 與該基板共同形成之肖特基接面可包括：一耐火金 屬矽化物，譬如為 ErSi、CoSi、NiSi、TiSi、Wsi ; —耐 火金屬，譬如為Mo、Ru、Ti、Ta、W、Hf ; — N型摻質 0503-A31336TWF/Ching Yen 13 1312544 (如 Li、Sb、P、As)，一 P 型摻質（如 B、A卜 Ga、In)， 或是兩者的組合。當這些材料用作一肖特基接面（或是似 肖特基接面）時，較佳的情況是，這些材料的功函數高於 約4eV，並且具有一高度低於0.4eV之肖特基能障。肖特 基接面的厚度較佳是低於約500埃（Angstroms)。 在考慮上述能影響介面狀態的介面參數後，本發明 • 之替代實施例係包括一 NMOS場效電晶體’其形成於一 基板上，該基板的的晶向係利用一組密勒指數來表 • 示，以及一 PM0S場效電晶體，其形成於一基板上，該 基板的的晶向係利用一組密勒指數來表示，其中 l2+m2+n2〉i2+j2+k2。如之前所注意者，一特佳實施例係 包括一 NM0S場效電晶體形成於一 {110}基板上，以及一 PM0S場效電晶體形成於一 {100}基板上。替代的實施例 包括一 NM0S場效電晶體形成於一 {110}或{100}基板上 以及一 PM0S場效電晶體形成於一 {111}、{211}、或{311} 基板上。 • 繼續參照第2圖，於本發明之更多其餘替代實施例 中，一 PM0S場效電晶體通道275以及一 NM0S場效電 晶體通道278係朝向一挑選後之晶向。在傳統CMOS技 術中，裝置通常形成於一具有單一晶向的特定半導體基 板上。然而，在矽中，電子於{100}方向的平面組上擁有 最大的移動率，而電洞於{110}方向的平面組上擁有最大 的移動率。普遍而言，一 P型場效電晶體或一 N型場效 電晶體係以這種最佳晶向來製造，然而N型場效電晶體 0503-A31336TWF/Ching Yen 14 1312544 係以低於最佳移動率之移動率來運作，這是由於其係以 相同的晶向來製造。Kinugawa所提出之美國專利案號 4,857,986，在此納入參考文件，當中描述晶向對於載子 移動率之幾種效應。研究者已經知悉當中問題所在，並 也已開發於多晶向之混合基板上製造CMOS裝置之技 術。舉例而言，由Yoshikawa等人所提出之美國專利案 號5,384,473，在此亦納入參考文件，描述利用晶圓結合 . 與選擇性磊晶技術來於（Π0)表面上製造P型場效電晶體 • 之方法，以及於（100)表面上製造N型場效電晶體之方法。 鑒於以上考量，PMOS場效電晶體251以及NMOS 場效電晶體253較佳的情況是形成於一混合基板上，而 個別載子濃度在基板之晶向上係具有最大值。因為這樣 能夠使載子移動率達到最大而使肖特基能障高度達到最 小，因此這是一種特別良好的結構（如以上實施例所描述 者）。再度依據較佳實施例，NMOS場效電晶體通道278 之晶向係沿<1〇〇>方向，對{100}晶向而言，電子移動率 • 在此方向係具有最大值。 在次佳實施例（未以圖例顯示）中，PMOS場效電晶體 275係沿<110〉方向，對{110}晶向而言，電洞移動率在此 方向係具有最大值。{11〇}<11〇>之結構為次佳的原因係 考量到對稱性之原因，當中牽涉到{110}晶向的基板。在 此晶向上，僅有兩個< 11 〇>方向與基板面相平行。因此， 這種{110}<110>結構導致混合基板製造中，PMOS場效 電晶體的元件佈局選擇性降低。PMOS場效電晶體251 0503-A31336TWF/Ching Yen 15 1312544 之較佳佈局係顯示於第2圖中。 如第2圖所示，pmo場效電晶體通道275係沿晶向 <U1>對準。雖然在此{110}<111>基板/通道結構中，電 洞移動率僅有其最大值之約70%，於{110}平面内，相較 於<11〇>有兩個方向，<111>有四個方向。因此，僅降低 30%移動率’就換來能使pM〇s場效電晶體之佈局選擇 f生蚤成雙倍之利益。因此，在經過這些考量以及上述對 於肖特基能障高度之考量下，PMOS場效電晶體251之較 Φ 佳佈局係顯示於第2圖中。 除了上述實施例，本發明之替代實施例係提供先進 平面裝置以及先進多閘裝置之製造方法。此種替代實施 例當中之一係顯示於第3圖中。 第3圖係依結合本發明第一實施例之半導體裝置之 一透視圖。在第3圖中’ 一平面電晶體330,譬如是一超 薄體絕緣體上覆矽場效電晶體（UTBS〇IFET)，以及一多 閘電晶體320，譬如是鰭式場效電晶體(FinFET)，如圖所 示，係形成於一半導體上覆矽0〇1)基板結構34〇上。該 SOI基板結構340係包括一基板342，一絕緣層344，以 及一半導體層364。該平面電晶體33〇係具有第一主動區 域331，其大體上為薄的平坦形狀。該多閘電晶體32〇係 具有第二主動區域322，其大體上為高的鰭狀。該第一及 第二主動區域331及332係自該S0I基板結構34〇之同 一半導體層形成。第一主動區域331係具有第一厚度ti。 第二主動區域322係具有第二厚度t2。第二厚度t2係大 0503-A31336TWF/Ching Yen 16 1312544 於第一厚度h。 日1 :&旱度車乂佳上係小於約400埃（angstroms)，並 矢更仏弟一；度心可約為平面電晶體3〇〇 之閘極長度1的—车，4f α ϊ ^ — \ 更佳。 ^ +並且小於二分之一之閘極厚度lg a牛1 5，如果平面電晶體300之閘極長度i為 300埃（3〇奈米），則第 8 幻弟尽度U可小於150埃，而小於 一埃，佳。當第一厚度t!較閘極長度1g的-半或三分 之一還小時，平面電晶體33〇可被視為是一超薄體 (thln b〇dy，UTB)電晶體。第一閘極S36係位於一 ，介電f 334的上方。平面電晶體330之源極和汲極區 ，337、338係形成於第一主動區域331内而與第一閑極 336之另一面鄰接。 _仍 > 考第3圖’第二主動區域322之鰭狀結構之第 二厚度h(即hf)較佳上係大於約1〇〇埃，並且舉例而言， 大於400埃更佳。鰭狀結構之寬度Wf較佳上係大於約细 埃。第二閘介電質324係位於第二主動區域322内通道 區域之上方。第二閘介電質324至少將鰭狀物的第二通 道區域部分圍繞。第二閘極326係位於第二閘介電質 的上方。第二閘介電質324將第二閘極326與第二主動 區域一322電性隔離開來。第3圖所示之多閘電晶體似 係-三間電晶體，因為第二間極326沿著鰭狀物的第二 通道區域的三邊延伸（沿著鰭狀物兩側壁之至少一部分以 及沿鰭狀物的上表面）。多間電晶體32〇之源極與汲極區 域327與328係形成於第二主動區域322内，而與第二 0503-A31336TWF/Ching Yen 17 1312544 閘極326之另一面鄰接。由於自源極327通往汲極328 之驅動電流當中之絶大部分係在侧壁表面流動，多閘電 晶體320具有一個高的鰭狀物往往是有利的（舉例而言， 可參見上述的尺寸）。 儘管圖中並未顯示，然而第3圖中的平面電晶體330 和/或多閘電晶體320亦可能具有間隙層（spacers)形成於 • 閘極326及336之側壁上。這種間隙層舉例而言，可能 - 於源極與没極區域的摻雜過程中有所助益。此外，平面 • 電晶體330和/或多閘電晶體320之一實施例可能具有抬 升的源極和没極區域，即提高的源極和汲極區域（未以圖 例顯示）。源極和汲極區域亦可能利用一矽化物之類的導 電材料來包圍。在此種情況中，間隙層能防範源極和汲 極區域上的導電碎化物材料與閘極間形成電性接觸》这 種電性接觸會導致源極和汲極區域與閘極之間發生不欲 發生的短路現象。 第4圖係第3圖所示裝置之平面圖，但係依據本發 • 明之一較佳實施例，而具有一 N型鰭式場效電晶體(N型 FinFET)320與一 P型超薄體絕緣體上覆矽場效電晶體（P 型TBSOIFET) 330。於第4圖中，兩個裝置皆位於{110} 之SOI非混合基板上。鰭狀物矽沿一 <110>方向對準，亦 即，源極327往汲極328之方向係<110>，以及鰭狀物的 側壁表面係朝向{110}。依據本發明之較佳實施例（參見第 2圖之NM0S場效電晶體253)，在給定佈局下，鰭狀物 的兩個側壁形成一 {100}之肖特基源極/汲極矽化物。同樣 0503-A31336TWF/Ching Yen 18 1312544 地’ P型UTBSOIFET 330係位於一 {110}基板上，該基板 具有一<111〉方向之通道。根據以上所討論者，在一佈局 彈性非主要因素之實施例中，P型UTBSOIFET之通道方 向是<110〉，這個方向係擁有最大的電洞移動率。 第5圖係本發明所提供一 N型FinFET 320與一 P型 FinFET 420之一平面圖之一實施例。如第4圖所示，兩 裝置係皆位於{110}之SOI非混合基板上，亦即，源極327 往汲極328之方向是<11 〇>，以及鰭狀物的侧壁表面係朝 向{110}。在此實施例中，P型FinFET 420相對於N型 FinFET 320 係旋轉了約 55。。因此，P 型 FinFET 420 之 鰭狀物係沿<211〉方向對準，亦即源極427往汲極428之 方向是<211 >，以及，鰭狀物的侧壁表面係朝向{111}。此 外，P型FinFET 420鰭狀物之端點430勢必形成一 {211} 肖特基源極/没極介面。回溯先前的討論，{211}介面較 {111}介面擁有較低的肖特基能障高度。因此，本實施例 由於具有超凡的肖特基源極/汲極結構，因而能夠改善裝 置的性能表現。 第4及5圖所顯示之實施例係次佳的原因在於其並 未對珍貴的晶片實際面積作有效率的應用。因此，在第6 圖所示之較佳實施例中，第5圖之P型FinFET 420及N 型FinFET 320係分別形成於{211}及{100}晶向之混合 SOI基板上。在此結構中，N型FinFET 320内面向{100} 之金屬矽化物以及P型FinFET 420内面向{110}之肖特 基源極/汲極能障能夠降低。 〇503-A31336TWF/Ching Ye】 19 1312544 “官本發明與其優點已詳加描述，對具本領域之通 常技術者將能輕易了解晶向以及方向可以變改並仍屬於 本發明之_内。舉例而言，以上所述關於CMOS製造 的許多特徵與功能能與其餘提升移動率方法相結合。° 用於例之以上討論中，許多參照號:馬係使 ;、土接面、接面以及二極體中。雖然理想的肖 =面是"的’本發_制預先考量 特基能障金屬之間可以插人—中間層。具本領域之通^ 技術者能明瞭這樣的肖特基接面被稱作「似肖特美 因而’本發明特別預料到似肖特基接面以及其他^價接 =見本發明時是有用的。此外，該 =妾 例中，此中間層係包括緣料性。在較佳實施 雖然本發明已以較佳實施例揭露如上， 以限定本發明，任何熟 瀚j非用 精神和範圍内，當可作此，在不脫縣發明之 之伴替目:更動與_ ’因此本發明 之保心㈣視後附之申請專圍所界定者為準。 0503-A31336TWF/Ching Yen 20 1312544 【圖式簡單說明】 第1A至1H圖係本發明所提供之一於一具有多晶向 之混合基板上製造一 CMOS之剖面圖之實施例； 第2圖係顯示一 CMOS佈局之剖面圖之實施例； 第3圖係顯示本發明所提供之一 SOI晶片之部分剖 面圖之實施例，該SOI晶片具有一平面電晶體與一多閘 電晶體； 第4圖係顯示本發明所提供之UTB、平面電晶體與 ⑩ 一多閘電晶體之平面圖之實施例； 第5圖係顯示本發明所提供之兩個多閘電晶體之平 面圖之實施例；以及 第6圖係顯示本發明所提供之兩個多閘電晶體之平 面圖之實施例，該等多閘電晶體係與一肖特基源極/汲極 CMOS混合基板共同形成。 主要元件符號說明】 204〜掩埋介電質層； 208〜硬遮罩層； 212〜開口； 216〜第二光阻層； 250~ CMOS 裝置；
2 02〜碎基板； 206〜SOI梦基板， 210〜光阻； 214〜隔離用絕緣材料； 218〜開口， 251〜PM0S場效電晶體； 252〜PM0S場效電晶體混合基板； 253〜NM0S場效電晶體； 0503-A31336TWF/Ching Yen 21 1312544 電晶體混合基板， ; 259〜閘極介電質層 2 6 3〜源極； 269〜源極； 275~ PMOS 通道； 278-NMOS場效電晶體通道； 320〜多閘電晶體/N型鰭式場效電晶體； 322〜第二主動區域； 324〜第二閘介電質；
326〜第二閘極； 328〜汲極； 330〜平面電晶體/ P型TBSOIFET ; 331〜第一主動區域； 332〜第二主動區域； 334〜第一閘介電質； 336〜第一閘極； 338〜汲極； 342〜基板； 364〜半導體層； 42 6〜閘極；
256〜NMOS場效 258〜淺溝槽隔離 2 61〜閘極； 266〜汲極； 272〜汲極； 3 37〜源極； 340〜SOI基板結構； 344〜絕緣層； 420〜P 型 FinFET ; 427〜源極； 430〜鰭狀物之端點； hf〜鰭狀物高度； wf〜鰭狀物寬度。 428〜汲極； lg〜閘極長度； trt2〜第一厚度、第二厚度; 0503-A31336TWF/Ching Yen 22

Claims (1)

1312544 修正日期：98.2.20 第95Π9773號申請專利範圍修正TCF]修(更)正替換頁 十、申請專利範圍： 1· 一種半導體裝置，包括： 一基板，具有第一區域及第二區域，該第一區域具 有（110}之第一晶向，該第二區域係具有一 {21丨}之第 -晶向 ， 一 NMOS場效電晶體形成於該第一區域上，以 第二PM0S場效電晶體形成於該第二區域上；以及 一似肖特基接面（Sch〇ttky-like contact)盥該基板一 同形成。 ' ^ 4申明專利範圍第1項所述之半導體裝置，其中 該似肖特基接面係包括—M0S場效電晶體源極/汲極。 如申明寸利範圍第1項所述之半導 ，立 該似肖特基接面係包括—妊祖甘、衣1 /、甲 人闲 匕牯材枓’其砥自退火金屬、退火 i萄矽化物、一 Ν型摻質、一 ρ型摻質，以及 之組合。 、，如申叫專利範圍第1項所述之半導體裝置，其中 該似肖特基接面伟句托 八 按卸係包括—材料，其選自Mo、Ru、Ti、Ta、 …丄、ΕΓ、C〇、Ni、Pt、以上材料之矽化物，以及以 上材料之組合。 兮/丄·如申請專利範圍第1項所述之半導體裝置，豆中 该似宵特基接面之厚度係小於埃。 該基半導體裝置’其中 厚度係介於料至2^=，。其+該掩时面質層之 0503-A31336TWFl/jamngw〇 23 131Eti3號權綱修正妒’㈣麵正替換頁I修正_ w 7. —互補型金氧半（CMOS)裝置，包括： 一基板，具有第一區域及第二區域，該第一區域具 有一 {110}晶向，該第二區域係具有一 {211}晶向； 一 NM0S場效電晶體形成於該第一區域上，包括一 NM0S源極以及一 NM0S汲極，其中該NM0S源極與 NM0S汲極至少當中之一包括一似肖特基接面；以及 • 一 PM0S場效電晶體形成於該第二區域上，包括一 ..PM0S源極以及一 PM0S汲極，其中該PM0S源極與 # PM0S汲極至少當中之一係包括一似肖特基接面。 8. 如申請專利範圍第7項所述之CMOS裝置，其中 該似肖特基接面係包括一材料，其選自退火金屬、退火 金屬矽化物、一 N型摻質、一 P型摻質’以及以上材料 之組合。 9. 如申請專利範圍第7項所述之CMOS裝置，其中 該似肖特基接面之厚度係小於500埃。 10. 如申請專利範圍第7項所述之CMOS裝置’其 ® 中該基板係包括一掩埋介電質層，其中該掩埋介面質層 之厚度係介於1〇埃至200埃之間。 11. 一種P型半導體裝置，包括： 一基板’其具有{110}之晶向， 一 P型鰭式場效電晶體（FinFET)，包括一鰭狀物沿 <211 >方向對準，以及該鰭狀物的側壁表面朝向{111}; 以及 一源極和一汲極於該基板上，沿<211〉方向； 0503-A31336TWFl/jamngwo 24 1312544 第95129773號申請專利範圍修正本 料年，月，修(更)正替換頁 修正日期·· 98.2.20 ---ι·Μ_·_^»ιιι·ι Hr- x、中至少該源極與該汲極當中之一係包括一肖特基 接面’以及其中該源極與該汲極係在兩者之間定義出一 通遏，以及其中一通道晶向係用一組米勒指數{211}表 示。 1 2.如申睛專利範圍第1 1項所述之p型半導體裝 置其中該似肖特基接面係包括一材料，其選自退火金 屬、退火金屬矽化物、一 N型摻質、一 p型摻質，以及 以上材料之組合。 班I3.如申請專利範圍第11項所述之P型半導體裝 置’其中該肖特基接面係包括—功函 屬材料。 Μ.如申请專利範圍第n項所述之p 置，其中該似肖特基接面之厚度係小於埃Λ衣 —種半導體裝置，包括： -基板’具有第—區域及第二區域，該第一區域且 有一 {110}之第一 a， 八 晶向 曰向 曰曰 5亥第二區域係具有一 {211}之第 N型鰭式％效電晶體(Fi咖 a於 上；以及 d 4 二，式場效電晶體形成於該第二區域上；以及 同形Γ 基接面（Schottky-Uke c〇福)與該基板一 0503-A31336TWFl/jamn gwo 25
TW095129773A 2005-09-06 2006-08-14 Semiconductor device, cmos device and p-type semiconductor device TWI312544B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/220,176 US7737532B2 (en) 2005-09-06 2005-09-06 Hybrid Schottky source-drain CMOS for high mobility and low barrier

Publications (2)

Publication Number Publication Date
TW200713467A TW200713467A (en) 2007-04-01
TWI312544B true TWI312544B (en) 2009-07-21

Family

ID=37829268

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095129773A TWI312544B (en) 2005-09-06 2006-08-14 Semiconductor device, cmos device and p-type semiconductor device

Country Status (4)

Country Link
US (1) US7737532B2 (zh)
JP (1) JP4639172B2 (zh)
CN (1) CN1929139A (zh)
TW (1) TWI312544B (zh)

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7575975B2 (en) * 2005-10-31 2009-08-18 Freescale Semiconductor, Inc. Method for forming a planar and vertical semiconductor structure having a strained semiconductor layer
JP4960007B2 (ja) * 2006-04-26 2012-06-27 株式会社東芝 半導体装置及び半導体装置の製造方法
US7897994B2 (en) * 2007-06-18 2011-03-01 Texas Instruments Incorporated Method of making (100) NMOS and (110) PMOS sidewall surface on the same fin orientation for multiple gate MOSFET with DSB substrate
US7863712B2 (en) * 2007-10-30 2011-01-04 International Business Machines Corporation Hybrid orientation semiconductor structure with reduced boundary defects and method of forming same
EP2073267A1 (en) * 2007-12-19 2009-06-24 INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM vzw (IMEC) Method of fabricating multi-gate semiconductor devices and devices obtained
US20090206416A1 (en) * 2008-02-19 2009-08-20 International Business Machines Corporation Dual metal gate structures and methods
US7943479B2 (en) * 2008-08-19 2011-05-17 Texas Instruments Incorporated Integration of high-k metal gate stack into direct silicon bonding (DSB) hybrid orientation technology (HOT) pMOS process flow
US8241970B2 (en) 2008-08-25 2012-08-14 International Business Machines Corporation CMOS with channel P-FinFET and channel N-FinFET having different crystalline orientations and parallel fins
JP2010258124A (ja) 2009-04-23 2010-11-11 Renesas Electronics Corp 半導体装置及び半導体装置の製造方法
JP5700621B2 (ja) * 2009-04-24 2015-04-15 株式会社半導体エネルギー研究所 半導体装置の作製方法
US8232627B2 (en) * 2009-09-21 2012-07-31 International Business Machines Corporation Integrated circuit device with series-connected field effect transistors and integrated voltage equalization and method of forming the device
CN101771088A (zh) * 2010-01-21 2010-07-07 复旦大学 Pn结和肖特基结混合式二极管及其制备方法
US9209180B2 (en) * 2010-02-10 2015-12-08 Taiwan Semiconductor Manufacturing Company, Ltd. Field effect transistor with conduction band electron channel and uni-terminal response
US9184050B2 (en) * 2010-07-30 2015-11-10 Taiwan Semiconductor Manufacturing Company, Ltd. Inverted trapezoidal recess for epitaxial growth
US8378394B2 (en) 2010-09-07 2013-02-19 International Business Machines Corporation Method for forming and structure of a recessed source/drain strap for a MUGFET
US8236634B1 (en) * 2011-03-17 2012-08-07 International Business Machines Corporation Integration of fin-based devices and ETSOI devices
US9082751B2 (en) * 2011-09-14 2015-07-14 Broadcom Corporation Half-FinFET semiconductor device and related method
US8871600B2 (en) 2011-11-11 2014-10-28 International Business Machines Corporation Schottky barrier diodes with a guard ring formed by selective epitaxy
US9406518B2 (en) * 2011-11-18 2016-08-02 Taiwan Semiconductor Manufacturing Company, Ltd. (110) surface orientation for reducing fermi-level-pinning between high-K dielectric and group III-V compound semiconductor substrate
WO2013095656A1 (en) * 2011-12-23 2013-06-27 Intel Corporation Common-substrate semiconductor devices having nanowires or semiconductor bodies with differing material orientation or composition
US8941187B2 (en) * 2012-01-13 2015-01-27 Globalfoundries Inc. Strain engineering in three-dimensional transistors based on strained isolation material
US9059044B2 (en) 2012-11-15 2015-06-16 International Business Machines Corporation On-chip diode with fully depleted semiconductor devices
KR102069609B1 (ko) 2013-08-12 2020-01-23 삼성전자주식회사 반도체 소자 및 그 제조 방법
US9490161B2 (en) * 2014-04-29 2016-11-08 International Business Machines Corporation Channel SiGe devices with multiple threshold voltages on hybrid oriented substrates, and methods of manufacturing same
EP3158586A4 (en) * 2014-06-20 2018-01-17 Intel Corporation Monolithic integration of high voltage transistors&low voltage non-planar transistors
US11610887B2 (en) * 2019-01-09 2023-03-21 Intel Corporation Side-by-side integration of III-n transistors and thin-film transistors
DE102020112203A1 (de) * 2020-03-13 2021-09-16 Taiwan Semiconductor Manufacturing Co. Ltd. Verfahren zum einbetten planarer fets mit finfets

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6292361A (ja) 1985-10-17 1987-04-27 Toshiba Corp 相補型半導体装置
JPH04372166A (ja) * 1991-06-21 1992-12-25 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
JP3017860B2 (ja) 1991-10-01 2000-03-13 株式会社東芝 半導体基体およびその製造方法とその半導体基体を用いた半導体装置
JP3217015B2 (ja) * 1996-07-18 2001-10-09 インターナショナル・ビジネス・マシーンズ・コーポレーション 電界効果トランジスタの形成方法
US6261932B1 (en) 1999-07-29 2001-07-17 Fairchild Semiconductor Corp. Method of fabricating Schottky diode and related structure
US6303479B1 (en) 1999-12-16 2001-10-16 Spinnaker Semiconductor, Inc. Method of manufacturing a short-channel FET with Schottky-barrier source and drain contacts
CN100401528C (zh) 2002-01-23 2008-07-09 斯平内克半导体股份有限公司 具有与应变半导体基片形成肖特基或肖特基类接触的源极和/或漏极的场效应晶体管
US6974737B2 (en) 2002-05-16 2005-12-13 Spinnaker Semiconductor, Inc. Schottky barrier CMOS fabrication method
US6869868B2 (en) 2002-12-13 2005-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating a MOSFET device with metal containing gate structures
US7329923B2 (en) * 2003-06-17 2008-02-12 International Business Machines Corporation High-performance CMOS devices on hybrid crystal oriented substrates
US6911383B2 (en) 2003-06-26 2005-06-28 International Business Machines Corporation Hybrid planar and finFET CMOS devices
WO2005022637A1 (ja) * 2003-08-28 2005-03-10 Nec Corporation フィン型電界効果トランジスタを有する半導体装置
JP2005079277A (ja) * 2003-08-29 2005-03-24 Toshiba Corp 電界効果トランジスタ
JP4439358B2 (ja) * 2003-09-05 2010-03-24 株式会社東芝 電界効果トランジスタ及びその製造方法
US7235433B2 (en) * 2004-11-01 2007-06-26 Advanced Micro Devices, Inc. Silicon-on-insulator semiconductor device with silicon layers having different crystal orientations and method of forming the silicon-on-insulator semiconductor device
US7298009B2 (en) * 2005-02-01 2007-11-20 Infineon Technologies Ag Semiconductor method and device with mixed orientation substrate
JP2006278818A (ja) * 2005-03-30 2006-10-12 Renesas Technology Corp 半導体装置

Also Published As

Publication number Publication date
US7737532B2 (en) 2010-06-15
TW200713467A (en) 2007-04-01
US20070052027A1 (en) 2007-03-08
JP4639172B2 (ja) 2011-02-23
JP2007073960A (ja) 2007-03-22
CN1929139A (zh) 2007-03-14

Similar Documents

Publication Publication Date Title
TWI312544B (en) Semiconductor device, cmos device and p-type semiconductor device
US11848242B2 (en) Method of manufacturing a semiconductor device and a semiconductor device
US11031297B2 (en) Multiple gate length vertical field-effect-transistors
CN110718588B (zh) 高性能mosfet
US7619300B2 (en) Super hybrid SOI CMOS devices
US10043878B2 (en) Vertical field-effect-transistors having multiple threshold voltages
US20150380481A1 (en) Conversion of strain-inducing buffer to electrical insulator
US20160071977A1 (en) Apparatus and Method for Forming Semiconductor Contacts
TWI624932B (zh) ３ｄ鰭式穿隧場效電晶體
US20150041858A1 (en) 3d transistor channel mobility enhancement
TWI577015B (zh) 半導體裝置及製造半導體裝置的方法
JP2009032955A (ja) 半導体装置、およびその製造方法
US20220302135A1 (en) Semiconductor device with gate recess and methods of forming the same
US11557652B2 (en) Metal source/drain-based MOSFET and method for fabricating the same
US20120261744A1 (en) Microelectronic device structure and manufacturing method thereof
JP2006060045A (ja) 半導体装置
WO2015054914A1 (zh) 一种非对称FinFET结构及其制造方法
US20160035574A1 (en) Metal semiconductor alloy contact resistance improvement
JP2005079277A (ja) 電界効果トランジスタ
US20220406909A1 (en) Field effect transistor with dual silicide and method
CN114927470A (zh) 半导体装置
JP2006100387A (ja) 電界効果トランジスタ及びその製造方法
TWI835165B (zh) 半導體裝置及其形成方法
TWI711073B (zh) 半導體裝置的製造方法及半導體裝置
US11508807B2 (en) Semiconductor device having nanosheet transistor and methods of fabrication thereof